A Universal Test Pattern Generator for DDR SDRAM *

Transcription

1 A Universal Test Pattern Generator for DDR SDRAM * Wei-Lun Wang ( ) Department of Electronic Engineering Cheng Shiu Institute of Technology Kaohsiung, Taiwan, R.O.C. wlwang@cc.csit.edu.tw used to detect all the faults. To test effectively the memories, at least two march algorithms are used, however increasing the hardware cost. The double data rate synchronous dynamic random access memory (DDR SDRAM) is one of the promising memory products of today. To meet the market requirements, various specifications of DDR SDRAMs are manufactured. In this paper, a universal test pattern generator has been proposed for testing the various DDR SDRAMs.. Introduction To respond the memory chip market demand of high speed/price, the double data rate synchronous dynamic random access memory (DDR SDRAM) achieves high speed double-data-rate transfer rates of up to 533 Mb/sec/pin (i.e., DDR-533). Typical faults in memories include the address decoder faults (AFs), stuck-at faults (SAFs), transition faults (TFs), stuck open faults (SOFs), coupling faults Abstract (CFs), neighborhood pattern sensitive faults (NPSFs), and data retention faults (DRFs) []. For Because the memory cores can be used to save the instructions/data, the memory cores are frequently used within the system-on-a-chips (SOCs). The quality of the SOCs is mainly determined by the memory cores. However, due to the complicated fabrication process, the fault models of the memories are more complicated than the fault models of the logical cores. So far, more than 40 march algorithms have been proposed; however; no any single march algorithm can be *This work was supported in part by the National Science Council of R.O.C. under contract NSC E testing such faults of the memories, it is shown that the march algorithms are superior to the non-march algorithms [2]. So far, for testing all the faults in the memories, no 00% fault coverage can be obtained by any single march algorithm [3]. To obtain a satisfied high fault coverage, several march algorithms are required to test a single memory chip. In [4], a controller-based programmable built-in self-test (BIST) core with three march algorithms, MATS++, March X, and March C_, for embedded EDO DRAM is presented. We have previously presented a low cost cyclic shift register () based test pattern generator (TPG) to test the SRAMs/DRAMs [5]. The test patterns of any

2 march algorithm can be generated by using such a high flexible TPG. Although the based TPG can generate the various read/write operations of the march algorithms, however, for testing the DDR (SDRAM), not only the read/write commands but also the various characteristics including the CAS latency (CL), burst length (BL), initialization, activation, and refresh operations, are also considered. Besides, various specifications of DDRs with various data transfer speeds, CLs and BLs are manufactured to meet the market requirements. In this paper, extending the based TPG, a universal TPG is proposed to test the DDRs. To avoid the data overlapping problem in the DDR, some NOP commands are required to interleave between two consecutive READ/WRITE commands. The number of required interleaved NOP commands is dependent on the lengths of BL and CL of the various DDRs. In the proposed TPG, not only the test patterns of any march algorithm can be generated but also the interleaved NOP commands can be produced to test the various DDRs. The organization of this paper is as follows. The DDRs are firstly introduced in Section 2. Section 3 reviews the commonly used notations of march algorithms and introduces previous work. Sections 4 and 5 detail the proposed test flow and test pattern generator. Finally the conclusions are given in Section Characteristics of DDRs Before discussing the BIST scheme, the characteristics of the DDR are introduced. The simplified functional block diagram of DDR is shown in Fig.. Three kinds of buses, Command, Address, and Data, are used to handle the DDR and access the data. In the Command Bus, the control lines, CS, RAS, CAS, and WE, are used to trigger the actions of chip select, row address strobe, column address strobe, and write enable, respectively. From the most significant bit (MSB) to the least significant bit (LSB), the addresses of the DDR are divided into three parts, i.e., bank address (BA), row address (RA), and column address (CA). In the DDR, the bit number of BA is two. The RA and CA are multiplexed by using the same bus wires. Via the Command and Address Buses, eight commands, NOP (no operation), ACT (to activate selected bank/row address), READ (to start read operation), WRITE (to start write operation), BST (to terminate burst operation), PRE (to start pre-charge operation), AR (to start auto refresh), and LMR (to load mode register), are used to handle the DDR. { CS RAS Command CAS Data DDR WE SDRAM BA Address { RA/CA CK Fig.. Simplified functional block diagram of DDR. At the first time, the DDR is initialized by running the NOP, PRE, LMR, LMR, PRE, AR, AR, and ACT commands in order. Then the normal read/write operations are proceeded. Due to the characteristics of CAS latency and burst length, some NOP commands are required to interleave between the consecutive read/write operations to avoid the data-overlapping problem. During the normal read/write operation, some ACT commands are required to activate the row addresses. Besides, one AR and several NOP commands are required to auto refresh the whole DDR. To test the DDR completely, the above procedure must be gone through. To save the testing time, the number of interleaved NOP commands between consecutive read/write commands should be minimized. Table tabulates the BLs, CLs, and required minimal number of NOP commands of Micron s DDR [6]. Table. Characteristics of Micron s DDR. BL CL Read-Read Write-Write Read-Write Write-Read 2 The values of BLs and CLs may be different for different manufacturers. For example, the values of BLs and CLs of DDR manufactured by Etron Technology, Inc. are (, 2, 4, 8) and (, 2, 3),

3 respectively [7]. Therefore, the required minimal number of NOP commands is distinct. To test the DDRs efficiently, the based TPG in [5] is extended in this paper. For different BLs and CLs, the proposed TPG can be used to test the various DDRs. Before discussing such a TPG, the march algorithms and the based TPG are reviewed in the next section. 3. Related Work 3. Review of March Algorithms Without loosing of generality, assume an m-step march algorithm with each step (denoted by S i ) having at most k read/write operations is expressed as: <march algorithm> ::= {<S i > i =,, m} () <S i > ::= <address order> ((<op j > j =,, k)) or del <address order> ::= (up) or (down) or (either up or down) <op j > ::= r0 or r or w0 or w where the notation r (w) is the read (write) operation and notation 0 () is the non-inverted (inverted) data backgrounds (DBs) [], respectively. For a W-bit memory chip, G (= log2 W +) inverted (non-inverted) data backgrounds are required. For example, the 4-bit non-inverted (inverted) data backgrounds are (0, 0, 0, 0), (0,, 0, ), and (0, 0,, ) ((,,, ), (, 0,, 0), and (,, 0, 0)). Thereafter we call the r (w) and 0 () in Eq. (), the r/w signals and the r/w data, respectively. The number of operations within a step is called its operation length. For example, in the following, the operation lengths of the st, 2 nd, and 3 rd march step of the MATS+ algorithm is one, two, and two, respectively. MATS+ algorithm []: { (w0); (r0, w); (r, w0)}. (2) To reduce the testing time, few march algorithms are presented in [8, 9] where the data backgrounds for each march step may be different. The march algorithms can also be implemented by the based TPG. However, the most algorithms are still used to test the memories by the following procedure: Test Procedure for Word-Oriented Memories: Step (): Choose an un-used data background. Step (2): Run march algorithm. Step (3): When the march algorithm is gone through, if there is any data background is un-used then repeat from Step (), else exit. In this paper, the above procedure will be extended to test the DDRs. 3.2 Cyclic Shift Registers In [5], a pair of cyclic shift registers (s) are used to generate the read/write signals and data, respectively. As shown in Fig. 2, a k-stage cyclic shift register () is composed of (k-) 2-to- multiplexers (MUXs) and k D flip-flops (F/Fs). Each MUX is controlled by the variable, c i (i =, 2,, k-). Only the variable c L (where L is the operation length) is one and the remaining variables are zero such that the output signal from Q is feedback to D L. Thus, two s with a seed of r/w data and signals can be used to generate the r/w operations of steps. For example, two 2-stage s are used for the MATS+ algorithm. The r/w operations of the st (2 nd ) step, (w0) ((r0, w)), can be generated by a pair of 2-stage s with a seed of (w0) ((r0, w)) and the variable (c ) = () ((0)). clk k c k- 0 k c 2 c Fig. 2 A k-stage cyclic shift register. output A simplified block diagram of based TPG is shown in Fig. 3, a pair of s, RW and DATA, are used to generate the r/w operations of each march step. The data backgrounds and the up/down consecutive addresses are generated by the DB and, respectively. The whole process of the march algorithm is handled by the Test Controller. 4. Design of Test Pattern Generator for DDRs 4. Test Flow for DDRs

4 Test Controller RW DATA DB Fig. 3 Simplified block diagram of based TPG. DRAM / SRAM During the DDR testing, not only the read/write operations of the march algorithms but also some conditions, including the initialization, auto-refresh, activation, BLs, CLs, and the number of NOP commands required to interleave between the read/write operations, are considered. In the following, a systematic test flow for the DDR is proposed. Test Procedure for DDRs: Step (): Initialize the DDR by running the NOP, PRE, LMR, LMR, PRE, AR, AR, and ACT commands in order. Step (2): Choose the un-used combinations of BL and CL. Step (3): Choose the un-used data background. Step (4): According to the march steps of the desired march algorithm, apply READ/WRITE commands, the interleaved NOP commands, and data to the DDR. Step (5): Perform the auto-refresh action by running the AR commands. Step (6): Perform the row address activation by running the ACT and two NOP commands in order. Step (7): If the march algorithm is not finished then repeat from Step (4) else continue. Step (8): If the data backgrounds are not exhausted then repeat from Step (3) else continue. Step (9): If the combinations of BL and CL are not exhausted then repeat from Step (2) else exit this procedure. interleaved NOP generator (ING) is presented and shown in Fig. 4 where the NOP ROM is used to store the number of interleaved NOP commands. When the inputs of NOP ROM, BL, CL, the first operation p and the second operation p 2 of, are ready, then the number of interleaved NOP command between p and p 2 is appeared at the NOP ROM output. For example, in Table, the number of interleaved NOP command between the READ/WRITE command is four when BL = 8 and CL = 2. The operation of ING is stated. At first, the first r/w operation in the, p = OP, is fed to the output via the MUX, then the MUX is switched to the opposite data input and the nop signal is applied to the output. The number of nop appeared at the output is the same as the content of the NOP Counter. When the content of the counter is equal to the output value of the NOP ROM. The MUX is switched again to the opposite data input. Meanwhile, an output signal from the Comparator is used to trigger the to shift right one bit (now, p = OP 2 ) and reset the NOP Counter, respectively. Such a procedure is generated repeatedly until all the r/w operations of the march algorithm are exhausted. Then the r/w operations of the and the nop signal will be proceeded to generate the READ, WRITE, and NOP commands in the next stage. For different specifications of BLs and CLs, only the contents of NOP ROM are required to update, thus the additional hardware overhead can be reduced. nop op k op 2 op p 2 p BL NOP ROM CL Comparator MUX Output 4.2 Interleaved NOP Generator As described previously, distinct combinations of BLs and CLs of DDRs may be existed by different semiconductor manufactures. To meet the test requirements of different BLs and CLs, an NOP Counter Fig. 4 The interleaved NOP generator. 4.3 Up/Down Address Generator Compared to the consecutive address generation

5 of the SRAM, the address is generated at BL intervals to test the DDR. The up/down addresses are expressed as follows: ( address) present + BL, if order is up ( address) next = (3) ( address) present - BL, if order is down As shown in Fig. 5, to generate the up/down addresses, a register array and a full adder/subtracter are utilized. When the address order is up (down), the register is initialized to all-zero (all-one) and use a full adder (subtracter) such that the next content of the register array is the present content of the register array plus (minus) the value of burst length (BL). BL Up/Dw Seed Full Adder / Subtracter Next Address Register Array Present Address Fig. 5 Block diagram of Address Generator. Meanwhile, the Burst Type of the mode register (MR) in the DDR is set to be sequential (interleaved) with an all-zero (all-one) starting column address, when the address order of the march step is up (down). Then the burst addresses in up (down) order are i, i+,, i+bl- (i, i-,, i-bl+) where i is the present address. After describing the generators of NOP commands and up/down addresses, the architecture of the proposed TPG will be stated in the next section. 5. Architecture of the Proposed TPG As shown in Fig. 6, eight main blocks, () Test Controller, (2) RW, (3) ING, (4) Command ROM, (5) ROM, (6) DATA, (7) DB, and (8), are used to constitute the proposed TPG for testing the DDRs. Test Controller RW DATA ROM Other Commands ING DB MUX MUX Command ROM Command Dat a Address Fig. 6 Block diagram of DDR TPG. DDR SDRAM The Test Controller block is used to control the overall testing procedure as stated in Subsection 4.. During the DDR testing, except the read/write/nop signals (commands), the other commands (signals) including the initialization, auto refresh, and activation signals are generated by the Test Controller. The RW block is used to generate the read/write operations of each march step, then the read/write and the interleaved nop signals are generated by the ING block. These signals are converted into the commands by the Command ROM and ROM. The commands of DDR are tabulated in Table 2. To apply the commands to the DDR, the Command Bus and Address Bus are needed. Therefore, as tabulated in Table 2, the blocks, Command ROM and ROM, are used to store the command messages and address messages, respectively. The read/write data of each march step, i.e., 0 and, are generated by the DATA, then the non-inverted and inverted data backgrounds are produced by the DB. As detailed in Subsection 4.3, the up/down addresses are generated by the. Table 2. The commands of DDR [6]. Command ROM Name ROM Command Bus CS RAS CAS WE Bus NOP 0 X ACT 0 0 BA/RA READ 0 0 BA/CA WRITE BA/CA BST 0 0 X PRE AR X LMR MR 3. X means don t care. 2. A 0 is high and the remaining bits of are don t care. 3. The BL and CL are defined in the MR by using the BA, RA, and CA. For testing a 52Mb (32M*6) Micron DDR chip with three march algorithms, MATS++, March X, and March C_, the proposed test pattern generator has been implemented by a hardware description language - Verilog and incorporated into an Altera device, EPF0K0TC44-3. In the following, a simulated timing diagram is shown in Fig. 7. According to the report of 0.35 µ m cell library of Glax! Inc, the gate count is 953. Compared to the BIST logic overhead of Mb*4

6 Extended Data-Out (EDO) DRAM in [4], which requires between 2000 to 3000 gates, the hardware overhead of the proposed TPG is acceptable. Fig. 7 The simulated timing diagram of proposed TPG. 6. Conclusions To meet the market requirements, various DDRs have been manufactured. Moreover, different NOP commands are required to interleave between two consecutive READ/WRITE commands. Therefore, the conventional march algorithms are required to extend to test the DDR, i.e., minimal NOP commands are needed to interleave between read/write operations. In this paper, a test flow of DDR is firstly discussed. Then a universal test pattern generator for various DDRs is presented. The architecture of the proposed TPG has been realized for testing a 52Mb DDR and it is reported that the associated hardware overhead is acceptable. [4] C. T. Huang, J. R. Huang, C. F. Wu, C. W. Wu, and T. Y. Chang, "A Programmable BIST Core for Embedded DRAM," IEEE Design and Test of Computers, pp , Jan.-March 999. [5] W. L. Wang, K. J. Lee, and J. F. Wang, An On-Chip March Pattern Generator for Testing Embedded Memory Cores, IEEE Trans. on VLSI, vol. 9, no. 5, Oct. 200, pp [6] [7] etron.com. [8] C. W. Wang, C. F. Wu, J. F. Li, C. W. Wu, T. Teng, K. Chiu, H. P. Lin, A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM, Proc. of Asian Test Symposium, 2000, pp [9] A. J. van de Goor, I. B. S. Tlili, March Tests for Word-Oriented Memories, Proc. Design, Automation and Test in Europe, 998, pp REFERENCES [] A. J. van de Goor, Testing Semiconductor Memories, Theory and Practice, Gouda, The Netherlands: ComTex, 998. [2] V. K. Kim and T. Chen, On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing, IEEE Trans. on CAD, vol. 8, no., pp , Nov [3] K. L. Cheng, M. F. Tsai, and C. W. Wu, Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories, Proc. of 9 th VLSI Test Symposium, 200, pp