Τί είναι η αριθµητική Η/Υ?

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1 ΗΜΥ ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ ΔΙΑΛΕΞΕΙΣ 14-15: Αριθμητική Η/Υ Διδάσκουσα: ΜΑΡΙΑ Κ. ΜΙΧΑΗΛ Αναπληρώτρια Καθηγήτρια, ΗΜΜΥ [Προσαρµογή από Computer Architecture, Computer Organization and Design, Patterson & Hennessy, 2005 και Drs. Mary Jane Irwin + Ali R. Hurson, Penn State University] Τί είναι η αριθµητική Η/Υ? Hardware Design of efficient circuits for arithmetic operations (+, -, x, /, sqrt, log, sine, ) Software Numerical methods for solving systems of equations Issues» Algorithm» Accuracy» Speed/power/area/ reliability trade-offs» Test/verification Issues» Algorithm» Error analysis» Computational complexity» Test/verification ΗΜΥ 312 Δ14-15 Αριθµητική.2 1

2 Εφαρµογές Γενικά Συστήµατα» Γρήγορες και µικρές βασικές πράξεις του επεξεργαστή Ειδικά Συστήµατα» Επεξεργασίες εικόνων και σηµάτων» Real-time 3D graphics» HDTV, συµπίεση εικόνας, ήχου και video» Network processors (data compression, encryption/decryption)» ΗΜΥ 312 Δ14-15 Αριθµητική.3 Άξονες Σχεδίασης interrelated Architectural innovations» Systolic arrays, wave pipelining, MMX, razor pipelines Technological advancements» 3D, multivalued gates, nanotechnology, Representation (encoding) systems» Redundant, residue, Arithmetic algorithms» SD arithmetic, serial arithmetic (lsb and msb first), saturating arithmetic, MACs, parallel multipliers, ΗΜΥ 312 Δ14-15 Αριθµητική.4 2

3 Αντιπροσώπευση Αριθµών infinite (real numbers) finite (machine representation) ΗΜΥ 312 Δ14-15 Αριθµητική.5 Fixed-radix Positional # Systems Binary: r=2, d [0,1] Decimal Equilavent? Balanced ternary: r=3, d [ - 1,0,1] Negabinary: r=-2, d [0,1] Redundant (signed digit): r=2, d [ - 1,0,1] Fractional radix: r=1/2, d [0,1] Irrational radix: r=sqrt(2), d [0,1] Complex-radix: r=2j, d [0,1,2,3] ΗΜΥ 312 Δ14-15 Αριθµητική.6 3

4 Fixed-radix Positional # Systems Binary: r=2, d [0,1] Balanced ternary: r=3, d [ - 1,0,1] Negabinary: r=-2, d [0,1] Redundant (signed digit): r=2, d [ - 1,0,1] Fractional radix: r=1/2, d [0,1] Decimal Equilavent? Irrational radix: r=sqrt(2), d [0,1] Complex-radix: r=2j, d [0,1,2,3] ¾ ΗΜΥ 312 Δ14-15 Αριθµητική.7 Real Number Representations Floating point (approximation) Slash (rational) representations» Keep numbers as num/denom pairs Exact arithmetic (e.g., 2/3) Division is multiplication Logarithmic representation» Keep numbers as log 2 A Easy multiply and divide Large dynamic range, but low precision ΗΜΥ 312 Δ14-15 Αριθµητική.8 4

5 Μετατροπή Βάσεων Assume that you are familiar with techniques for» converting to/from radix 2, 4, 8, 10, 16,» doing arithmetic in the old radix» doing arithmetic in the new radix» doing conversion between radices ΗΜΥ 312 Δ14-15 Αριθµητική.9 Διαλέγοντας την Καλύτερη Βάση Μετατροπή» I/O is in decimal, so r=10 (BCD) would require no conversion, but wastes storage space and arithetic unit area and delay Συµβατότητα» CMOS circuitry supports two states (on, off) only, so r=2 (or some power of 2) Αξιοπιστία» circuitry supports binary logic only (as opposed to multivalued logic) ΗΜΥ 312 Δ14-15 Αριθµητική.10 5

6 Διαλέγοντας την Καλύτερη Βάση (Συν.) Αποτελεσµατικότητα The # of different representations is M = r n Assuming the component cost for repr is proportional to r (with binary logic it s really prop. to log 2 r for r a power of 2), then the cost of the repr is $ = K 1 n r $ = K 1 (ln M)/(ln r) r = K 2 r/(ln r) To minimize $, take derivative at zero wrt r d$/dr = (K 2 (ln r -1))/ (ln r 2 ) 0 So, ln r = 1 (r = e = ) is the most efficient radix! Cost of r=2 and r=4 are about equal. ΗΜΥ 312 Δ14-15 Αριθµητική.11 Indirect Signed Arithmetic When hardware uses unsigned operands» some multiplication and division schemes» floating point mantissa units Sign logic Sign removal Unsigned operation Adjustment Other examples of pre/post operand processing» dealing with unacceptable or inconvenient operands infinity, NAN sin(2π + X) = sin(π - X) = sin X» more efficient division when divisor can be scaled (along with the dividend) to be in a certain range ΗΜΥ 312 Δ14-15 Αριθµητική.12 6

7 Shifters Two kinds: logical-- value shifted in is always "0" "0" msb lsb "0" arithmetic-- on right shifts, sign extend msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! ΗΜΥ 312 Δ14-15 Αριθµητική.13 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier 1001 = Product = 72 n bits x n bits = 2n bit product Binary makes it easy: 0 => place 0 1 => place a copy ( 0 x multiplicand) ( 1 x multiplicand) 4 versions of multiply hardware & algorithm: successive refinement ΗΜΥ 312 Δ14-15 Αριθµητική.14 7

8 Unsigned Combinational Multiplier A 3 A 2 A 1 A 0 B 0 A 3 A 2 A 1 A 0 B 1 A 3 A 2 A 1 A 0 B 2 A 3 A 2 A 1 A 0 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 Stage i accumulates A * 2 i if B i == 1 Q: How much hardware for 32 bit multiplier? ΗΜΥ 312 Δ14-15 Αριθµητική.15 How does it work? A 3 A 2 A 1 A 0 B 0 A 3 A 2 A 1 A 0 B 1 A 3 A 2 A 1 A 0 B 2 A 3 A 2 A 1 A 0 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 at each stage shift A left ( x 2) use next bit of B to determine whether to add in shifted multiplicand accumulate 2n bit partial product at each stage ΗΜΥ 312 Δ14-15 Αριθµητική.16 8

9 Unsigned shift-add multiplier (version 1) 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Multiplicand 64 bits Shift Left 64-bit ALU Multiplier 32 bits Shift Right Product 64 bits Write Control Multiplier = datapath + control ΗΜΥ 312 Δ14-15 Αριθµητική.17 Multiply Algorithm Version 1 Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to product & place the result in Product register Product Multiplier Multiplicand Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit n th repetition? No: < n repetitions ΗΜΥ 312 Δ14-15 Αριθµητική.18 Yes: n repetitions Done 9

10 Observations on Multiply Version 1 1 clock cycle per step => 100 clocks per multiply 1/2 bits in multiplicand always 0 => 64-bit adder is wasted 0 s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed Instead of shifting multiplicand to left, shift product to right. ΗΜΥ 312 Δ14-15 Αριθµητική.19 MULTIPLY HARDWARE Version 2 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32-bit ALU 32 bits Multiplier 32 bits Shift Right Product 64 bits Shift Right Write Control ΗΜΥ 312 Δ14-15 Αριθµητική.20 10

11 Multiply Algorithm Version 2 Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Product Multiplier Multiplicand : : : : : : : : : : : : Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. n th repetition? No: < n repetitions Yes: n repetitions Done ΗΜΥ 312 Δ14-15 Αριθµητική.21 Still more wasted space! Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Product Multiplier Multiplicand : : : : : : : : : : : : Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. n th repetition? No: < n repetitions Yes: n repetitions Done ΗΜΥ 312 Δ14-15 Αριθµητική.22 11

12 Observations on Multiply Version 2 Product register wastes space that exactly matches size of multiplier Both Multiplier register and Product register require right shift Combine Multiplier register and Product register ΗΜΥ 312 Δ14-15 Αριθµητική.23 MULTIPLY HARDWARE Version 3 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Multiplicand 32 bits 32-bit ALU Product (Multiplier) 64 bits Shift Right Write Control ΗΜΥ 312 Δ14-15 Αριθµητική.24 12

13 Multiply Algorithm Version 3 Start Multiplicand Product Product0 = 1 1. Test Product0 Product0 = 0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions ΗΜΥ 312 Δ14-15 Αριθµητική.25 Yes: 32 repetitions Done Observations on Multiply Version 3 2 steps per bit because Multiplier & Product combined MIPS registers Hi and Lo are left and right half of Product Gives us MIPS instruction MultU What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) apply definition of 2 s complement - need to sign-extend partial products and subtract at the end Booth s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles - can be modified to handle multiple bits at a time ΗΜΥ 312 Δ14-15 Αριθµητική.26 13

14 Multiplication of signed numbers n Booth s algorithm o Invented for speed l Shifting was faster than addition at the time l Objective: reduce the number of additions required o Fortunately, it works for signed numbers as well o Basic idea: the additions from a string of 1 s in the multiplier can be converted to a single addition and a single subtraction operation o Example: is equivalent to requires additions for each of these bit positions requires an addition for this bit position ΗΜΥ 312 Δ14-15 Αριθµητική.27 and a subtraction for this bit position Motivation for Booth s Algorithm Example 2 x 6 = 0010 x 0110: 0010 x shift (0 in multiplier) add (1 in multiplier) add (1 in multiplier) shift (0 in multiplier) ALU with add or subtract gets same result in more than one way: 6 = = For example 0010 x shift (0 in multiplier) 0010 sub (start string of 1 s) 0000 shift (mid string of 1 s) add (end string of 1 s) ΗΜΥ 312 Δ14-15 Αριθµητική.28 14

15 Booth s Algorithm middle " end of run of run beginning of run Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s sub 1 1 Middle of run of 1s none 0 1 End of run of 1s add 0 0 Middle of run of 0s none Originally for Speed (when shift was faster than add) Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one ΗΜΥ 312 Δ14-15 Αριθµητική.29 Booth s Algorithm ΗΜΥ 312 Δ14-15 Αριθµητική.30 15

16 Booth s algorithm q Starting from right to left, look at two adjacent bits of the multiplier ü Place a zero at the right of the LSB to start q If bits = 00, do nothing q If bits = 10, subtract the multiplicand from the product ü Beginning of a string of 1 s q If bits = 11, do nothing ü Middle of a string of 1 s q If bits = 01, add the multiplicand to the product ü End of a string of 1 s q Shift product register right one bit When shifting the product right, you must preserve the sign of the intermediate result. ΗΜΥ 312 Δ14-15 Αριθµητική.31 Arithmetic Right Shift (vs. logical right shift) Example: 0010 x 1101 = Example of Booth s Algorithm ΗΜΥ 312 Δ14-15 Αριθµητική.32 16

17 Booths Example (2 x 7) Operation Multiplicand(m) Product next? 0. initial value > sub 1a. P = P - m shift P (sign ext) 1b > nop, shift > nop, shift > add 4a shift 4b done Indicates operation to be performed next = Q -1 ΗΜΥ 312 Δ14-15 Αριθµητική.33 Booths Example (2 x -3) Operation Multiplicand(m) Product next? 0. initial value > sub 1a. P = P - m shift P (sign ext) 1b > add a shift P 2b > sub a shift 3b > nop 4a shift 4b done ΗΜΥ 312 Δ14-15 Αριθµητική.34 17

18 Booth Sequential Multiplier S Cin Cin A B MULTIPLIER AR QR QF MUX Sel MR w Control Signals AR_Op QR_Op MR_Op Clr_Bar Sel Cin Halt MULTIPLICAND ΗΜΥ 312 Δ14-15 Αριθµητική.35 Booth Algorithm MR Multiplicand QR Multiplier AR 0 QF 0 = 10 QR 0 QF = 01 odd AR [AR] - [MR] AR [AR] + [MR] even = 00 = 11 ashr(ar & QR & QF) 2n+1 CNT = 2n+1 HALT ΗΜΥ 312 Δ14-15 Αριθµητική.36 18

19 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize 0 ΗΜΥ 312 Δ14-15 Αριθµητική.37 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP 1 ΗΜΥ 312 Δ14-15 Αριθµητική.38 19

20 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR 2 ΗΜΥ 312 Δ14-15 Αριθµητική.39 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP 3 ΗΜΥ 312 Δ14-15 Αριθµητική.40 20

21 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP ASHR 4 ΗΜΥ 312 Δ14-15 Αριθµητική.41 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP ASHR Sub MR 5 ΗΜΥ 312 Δ14-15 Αριθµητική.42 21

22 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP ASHR Sub MR ASHR 6 ΗΜΥ 312 Δ14-15 Αριθµητική.43 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP ASHR Sub MR ASHR NOP 7 ΗΜΥ 312 Δ14-15 Αριθµητική.44 22

23 Booth Multiplication Overflow Example MR AR QR QF Function Cnt Initialize NOP ASHR NOP ASHR Sub MR ASHR NOP ASHR 8 ΗΜΥ 312 Δ14-15 Αριθµητική.45 Modified Booth's Algorithm n Check 3 bits of multiplier at a time and take proper steps as follows: 000 no action shift right twice 001 add multiplicand shift right twice 010 add multiplicand shift right twice 011 add 2*multiplicand shift right twice 100 sub 2*multiplicand shift right twice 101 sub multiplicand shift right twice 110 sub multiplicand shift right twice 111 no action shift right twice ΗΜΥ 312 Δ14-15 Αριθµητική.46 23

24 Modified Booth's Algorithm n Any version of Booth's algorithm allows a sequence of consecutive 1 s to be bypassed. n Modified Booth's Algorithm is faster than Booth's Algorithm. n Booth's Algorithm can be further extended by looking at 4 bits, (5 bits,...) at a time and taking proper actions according to the proper encoding table. ΗΜΥ 312 Δ14-15 Αριθµητική.47 Modified Booth's Algorithm n Example * Extension add B, shift twice 100 sub 2B, shift twice 011 add 2B, shift twice Answer ΗΜΥ 312 Δ14-15 Αριθµητική.48 24

25 Fast Multiplication n Reduction of Summands n Generate matrix of summands (partial products). n Go over several reduction stages using 2-2 and 3-2 adders. n In final stage (2 rows) use a fast adder to generate the result. ΗΜΥ 312 Δ14-15 Αριθµητική.49 Fast Multiplication n Reduction of Summands Partial Products Final Stage use a fast adder * * * * * * * * * * * * { * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ΗΜΥ 312 Δ14-15 Αριθµητική.50 25

26 Fast Multiplication n Reduction of Summands ΗΜΥ 312 Δ14-15 Αριθµητική.51 n Reduction of Summands Fast Multiplication n It is suitable for unsigned numbers. n Number of reduction stages depends on the length of the multiplier. n Execution time: T RS = Δt + m * (4 Δt) + P Time to generate matrix of summands No. of reduction stages Execution time of the fast adder ΗΜΥ 312 Δ14-15 Αριθµητική.52 26

27 Fast Multiplication n Iterative Method n Multiplication of 2 n-bit numbers can be converted into four multiplications of n/2-bit numbers and two additions. n This scheme can be iteratively applied to all multiplication terms ΗΜΥ 312 Δ14-15 Αριθµητική.53 Fast Multiplication n Iterative Method X = 2 n/2 a + b, Y = 2 n/2 c + d X*Y=(2 n/2 a+b)*( 2 n/2 c+d)= 2 n (ac)+ 2 n/2 (ad+bc)+bd ΗΜΥ 312 Δ14-15 Αριθµητική.54 27

28 n Iterative Method Fast Multiplication ΗΜΥ 312 Δ14-15 Αριθµητική.55 Fast Multiplication n Iterative Method An Example x = a 3 a 2 a 1 a 0 y = b 3 b 2 b 1 b 0 x*y = 2 4 (a 3 a 2 )( b 3 b 2 )+ 2 2 [(a 3 a 2 )( b 1 b 0 )+( a 1 a 0 )( b 3 b 2 )]+ ( a 1 a 0 )( b 1 b 0 ) ΗΜΥ 312 Δ14-15 Αριθµητική.56 28

29 Fast Multiplication n Iterative Method An Example x = 1010 y = 1100 ΗΜΥ 312 Δ14-15 Αριθµητική.57 Fast Multiplication a 7 a 6 a 5 a 4 a 3 a 2 a 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 a 7 b 0 a 6 b 0 a 5 b 0 a 4 b 0 a 3 b 0 a 2 b 0 a 1 b 0 a 7 b 1 a 6 b 1 a 5 b 1 a 4 b 1 a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 a 7 b 2 a 6 b 2 a 5 b 2 a 4 b 2 a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 a 7 b 3 a 6 b 3 a 5 b 3 a 4 b 3 a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3 a 7 b 4 a 6 b 4 a 5 b 4 a 4 b 4 a 3 b 4 a 2 b 4 a 1 b 4 a 0 b 4 a 7 b 5 a 6 b 5 a 5 b 5 a 4 b 5 a 3 b 5 a 2 b 5 a 1 b 5 a 0 b 5 a 7 b 6 a 6 b 6 a 5 b 6 a 4 b 6 a 3 b 6 a 2 b 6 a 1 b 6 a 0 b 6 a 7 b 7 a 6 b 7 a 5 b 7 a 4 b 7 a 3 b 7 a 2 b 7 a 1 b 7 a 0 b ΗΜΥ 312 Δ14-15 Αριθµητική.58 29

30 Fast Multiplication n Full Adder Tree n Generate matrix of summands. n Use a binary tree of full-adders to calculate the result in a pipeline fashion ΗΜΥ 312 Δ14-15 Αριθµητική.59 Fast Multiplication n Full Adder Tree Carry ******** ******** ******** ******** ******** ******** ******** ******** FA FA FA FA FA FA FA P 2n-1... P 0 ΗΜΥ 312 Δ14-15 Αριθµητική.60 30

31 Fast Multiplication n Column Compression n Assume that a population counter is available that can count the number of 1 s in an n-bit word, producing a 1+ log 2 n bit result. n Similar to the reduction of summands technique one can go through several reduction stages to compress the number of bits in each column. ΗΜΥ 312 Δ14-15 Αριθµητική.61 Fast Multiplication n Column Compression n Generate matrix of summands. n Go over several stages using population counters. n In final stage (2 elements in each column) use a fast adder to generate the result. ΗΜΥ 312 Δ14-15 Αριθµητική.62 31

32 n Column Compression Fast Multiplication Matrix of Summands st Compression Stage ΗΜΥ 312 Δ14-15 Αριθµητική.63 n Column Compression Fast Multiplication 2nd Compression Stage (Final Stage) Result ΗΜΥ 312 Δ14-15 Αριθµητική.64 32

33 Array Multipliers Conventional CSM x 4 x 3 x 2 x 1 x 0 y 4 y 3 y 2 y 1 y 0 1 W 40 W 30 W 20 W 10 W 00 W 41 W 31 W 21 W 11 W 01 W 42 W 32 W 22 W 12 W 02 W 43 W 33 W 23 W 13 W 03 1 W 44 W 34 W 24 W 14 W 04 Z 9 Z 8 Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 ΗΜΥ 312 Δ14-15 Αριθµητική.65 Array Multipliers(2) Conventional CSM W 44 W = AND( X, Y ) ij i j W' ij = NAND( X i, Y ) j W' 43 FA W' 42 W' 41 FA W 32 W FA 33 W FA 23 FA W' W W 40 W W W 20 W W FA FA FA 0 FA 0 W FA 22 FA W12 W 13 FA W' 34 FA W' 24 W' FA 14 FA W' 04 Z 3 FA W 03 Z 2 W 02 Z 1 In1 In2 FA Cin Cout Sum W 00 Z 0 FA FA FA FA 1 Z 4 Z Z Z Z ΗΜΥ 312 Δ14-15 Αριθµητική.66 Z 5 33

34 Integer Division o Similar to multiplication, one can develop a routine to perform division as a sequence of subtractions. o However, such an algorithm is very inefficient and slow. o Instead one can develop an algorithm which performs division as a sequence of Compare, Shift and Subtract operations. ΗΜΥ 312 Δ14-15 Αριθµητική.67 Integer Division n Paper and pencil binary division (divisor) 1000 n Steps in hardware o Shift the dividend left one position o Subtract the divisor from the left half of the dividend o If result positive, shift left a 1 into the quotient o Else, shift left a 0 into the quotient, and repeat from the beginning o Once the result is positive, repeat the process for the partial remainder o Do n iterations where n is the size of the divisor ΗΜΥ 312 Δ14-15 Αριθµητική (quotient) (dividend) (remainder) 34

35 n Methods of Division n There are several different algorithms for division: n Restoring Method n Non-Restoring Method n Direct Comparison Division ΗΜΥ 312 Δ14-15 Αριθµητική.69 n Methods of Division Division n In the restoring method, the contents of the partial remainder is restored whenever it is detected that the divisor is larger than the partial remainder. ΗΜΥ 312 Δ14-15 Αριθµητική.70 35

36 n Methods of Division Division n In non-restoring method, if it is detected that the divisor is larger than the partial remainder, its contents are not restored. n However, in the next iteration, instead of subtracting the divisor from the partial remainder, it is added to the partial remainder. ΗΜΥ 312 Δ14-15 Αριθµητική.71 n Methods of Division Division n Naturally, restoring and non-restoring techniques are equivalent. n Consider the consecutive sequence of iterations for both techniques (next slide). n As can be seen, both schemes generate the same value as the partial remainder. However, the nonrestoring technique should be faster than the restoring method since it requires fewer number of operations. ΗΜΥ 312 Δ14-15 Αριθµητική.72 36

37 Division n Methods of Division n Restoring n Non-Restoring Shifting Restoring (2 ( (A-B)+B) -B) =2A-B 2 nd Iteration 2 nd Iteration 2 (A-B) +B =2A-B S ubtraction Shifting ΗΜΥ 312 Δ14-15 Αριθµητική.73 Division n Methods of Division n In direct comparison approach, first the divisor is compared against the partial remainder. n If it is smaller than or equal to the partial remainder, it will be subtracted and quotient digit is set to 1. n Otherwise, just the quotient is set to zero. ΗΜΥ 312 Δ14-15 Αριθµητική.74 37

38 n Recall: Binary Division o Dividend=Quotient*Divisor + Remainder n Let s assume that both the dividend and divisor are positive and hence the quotient and the remainder are nonnegative n The division operands and both results are 32-bit values and we will ignore the sign for now ΗΜΥ 312 Δ14-15 Αριθµητική.75 Divide: Paper & Pencil Quotient Divisor Dividend Remainder (or Modulo result) Notice that there is no way to get a 1 in leading digit! (this would be an overflow, since quotient would have n+1 bits) ΗΜΥ 312 Δ14-15 Αριθµητική.76 38

39 Unsigned Divide: Paper & Pencil 1001 Quotient Divisor Dividend Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder 3 versions of divide, successive refinement ΗΜΥ 312 Δ14-15 Αριθµητική.77 Signed Division n Simplest solution: remember the signs of the divisor and the dividend and then negate the quotient if the signs disagree n The dividend and the remainder must have the same signs Considerations n The same hardware can be used for both multiply and divide o Requirement: 64-bit register that can shift left or right and a 32-bit ALU that can add or subtract ΗΜΥ 312 Δ14-15 Αριθµητική.78 39

40 Divide Algorithm Version 1 Takes n+1 steps for n-bit Quotient & Rem. Remainder Quotient Divisor Remainder 0 Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. Test Remainder Remainder < 0 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to Shift the Divisor register right 1 bit. ΗΜΥ 312 Δ14-15 Αριθµητική.79 n+1 repetition? Done No: < n+1 repetitions Yes: n+1 repetitions (n = 4 here) First Hardware Design for Divider Initialize the Quotient register to 0, initialize the left-half of the Divisor register with the divisor, and initialize the Remainder register with the dividend (right-aligned) ΗΜΥ 312 Δ14-15 Αριθµητική.80 40

41 DIVIDE HARDWARE Version 1 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Divisor 64 bits Shift Right 64-bit ALU Quotient 32 bits Shift Left Remainder 64 bits Write Control ΗΜΥ 312 Δ14-15 Αριθµητική.81 Observations on Divide Version 1 1/2 bits in divisor always 0 => 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted Instead of shifting divisor to right, shift remainder to left? 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration ΗΜΥ 312 Δ14-15 Αριθµητική.82 41

42 Divide Algorithm Version 2 Remainder Quotient Divisor Start: Place Dividend in Remainder 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. Remainder 0 Test Remainder Remainder < 0 3a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. ΗΜΥ 312 Δ14-15 Αριθµητική.83 nth repetition? Done No: < n repetitions Yes: n repetitions (n = 4 here) Second Hardware Design for Divider Also, the algorithm must be changed so the remainder is shifted left before the subtraction takes place ΗΜΥ 312 Δ14-15 Αριθµητική.84 Much like with the multiplier, the divisor and ALU can be reduced to 32-bits if we shift the remainder right instead of shifting the divisor to the left 42

43 DIVIDE HARDWARE Version 2 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Divisor 32-bit ALU 32 bits Quotient 32 bits Shift Left Remainder 64 bits Shift Left Write Control ΗΜΥ 312 Δ14-15 Αριθµητική.85 Observations on Divide Version 2 Eliminate Quotient register by combining with Remainder as shifted left Start by shifting the Remainder left as before. Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many. Thus the final correction step must shift back only the remainder in the left half of the register ΗΜΥ 312 Δ14-15 Αριθµητική.86 43

44 Divide Algorithm Version 3 Remainder Divisor Start: Place Dividend in Remainder 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. Remainder 0 Test Remainder Remainder < 0 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. ΗΜΥ 312 Δ14-15 Αριθµητική.87 nth repetition? No: < n repetitions Yes: n repetitions (n = 4 here) Done. Shift left half of Remainder right 1 bit. Third Hardware Design for Divider Shift the bits of the quotient into the remainder register Also, the last step of the algorithm is to shift the left half of the remainder right 1 bit ΗΜΥ 312 Δ14-15 Αριθµητική.88 44

45 DIVIDE HARDWARE Version 3 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg) Divisor 32 bits 32-bit ALU HI LO Remainder (Quotient) 64 bits Shift Left Write Control ΗΜΥ 312 Δ14-15 Αριθµητική.89 Observations on Divide Version 3 Same Hardware as Multiply: just need ALU to add or subtract, and 63-bit register to shift left or shift right Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary Note: Dividend and Remainder must have same sign Note: Quotient negated if Divisor sign & Dividend sign disagree e.g., 7 2 = 3, remainder = 1 Possible for quotient to be too large: if divide 64-bit interger by 1, quotient is 64 bit ΗΜΥ 312 Δ14-15 Αριθµητική.90 45

46 Notation ΗΜΥ 312 Δ14-15 Αριθµητική.91 Introduction to Computer Architecture n Division n Restoring Method ΗΜΥ 312 Δ14-15 Αριθµητική.92 46

47 Introduction to Computer Architecture n Division n Non-Restoring Method ΗΜΥ 312 Δ14-15 Αριθµητική.93 Introduction to Computer Architecture n Fast Division SRT (Sweeney, Robertson, Tocher) Method n Faster direct division can be developed on normalized numbers by observing sequences of more than one bit of the dividend or partial remainder - i.e., sequences of 0 s and 1 s can be skipped. n This method was proposed to improve binary floating-point arithmetic. ΗΜΥ 312 Δ14-15 Αριθµητική.94 47

48 SRT Outline n Divisor normalized to d ½ n Restrict partial remainder to [ -½, ½) instead of [-d,d) n Initially may need to shift z to right, then double q and s at end n All subsequent partial remainders in range [ -½, ½) using quotient digit selection rule: n If 2s (j-1) < - ½ n Then q j = -1 n Else if 2s (j-1) - ½ n then q j = 1 n else q j = 0 n endif n endif n Just two comparisons needed with constants ½ and + ½ ΗΜΥ 312 Δ14-15 Αριθµητική.95 Intel Pentium Floating-Point Division Bug, 1994 Enter the following equation into your PC's calculator: ΗΜΥ 312 Δ14-15 Αριθµητική.96 ( / ) * If the answer is zero, your computer is just fine. If you get anything else, you have an old Intel Pentium (P5) CPU with a floating-point division bug (SRT algorithm!), a software bug burned into a computer chip and reproduced over and over in the manufacturing process. On October 30, 1994, Dr. Thomas R. Nicely of Lynchburg (Virginia) College traced an unexpected result from one of his experiments to an incorrect answer by a division problem solved on his Pentium PC. He posted his finding on the Internet and soon afterward a firestorm erupted as numerous other people duplicated his problem and found additional situations that resulted in wrong answers. Fortunately, these cases were rare and resulted in wrong answers only for extremely math-intensive, scientific, and engineering calculations 48

49 Floating-Point ( What can be represented in N bits? Unsigned 0 to 2 N -1 2s Complement - 2 N-1 to 2 N-1-1 But, what about? very large numbers? 9,349,398,989,787,762,244,859,087, x very small number? x fractional values? 0.35 Mixed numbers? Irrationals? π ΗΜΥ 312 Δ14-15 Αριθµητική.97 Recall Scientific Notation decimal point exponent Sign, magnitude x x 10 Mantissa Sign, magnitude Issues: Representation radix (base) Arithmetic operations(+, -, *, / ) Range and Precision Rounding IEEE F.P. ± 1.M x 2 e Exceptions (e.g., divide by zero, overflow, underflow) Errors On most general purpose computers, these issues are addressed by the IEEE 754 floating point standard. ΗΜΥ 312 Δ14-15 Αριθµητική.98 49

50 IEEE-754 Single Precision Floating-Point Numbers single precision (32 bits, float in C) actual exponent is e = E sign S E M exponent: excess 127 binary integer 0 < E < 255 S E-127 X = (-1) 2 (1.M) Mantissa or significand sign + magnitude, normalized binary significand w/ hidden one bit: 1.M Magnitude of numbers that can be represented is in the range: (1.0) to ( ) which is approximately: 1.8 x to 3.40 x Why use a biased exponent? Why are floating point numbers normalized? ΗΜΥ 312 Δ14-15 Αριθµητική.99 IEEE-754 Double Precision Floating-Point Numbers double precision (64 bits, double in C) ΗΜΥ 312 Δ14-15 Αριθµητική.100 actual exponent is e = E sign S E M exponent: excess 1023 binary integer 0 < E < 2048 S E-1023 X = (-1) 2 (1.M) Magnitude of numbers that can be represented is in the range: (1.0) to ( ) which is approximately: 2.2 x to 1.8 x Mantissa or significand sign + magnitude, normalized binary significand w/ hidden one bit: 1.M The IEEE 754 standard also supports extended single-precision (more than 32 bits) and extended double-precision (more than 64 bits). Special values for the exponent and mantissa are used to indicate other values, like zero and infinity. 50

51 Converting from Binary to Decimal Floating Point What is the decimal single-precision floating point number that corresponds to the bit pattern ? Use the equation X = (-1) S x 2 E-127 x (1.M) where S = 0 E = = M = = = so X = (-1) 0 x x = 804 = 8.04 x 10 2 ΗΜΥ 312 Δ14-15 Αριθµητική.101 Converting from Decimal to Binary Floating Point What is the binary representation for the single-precision floating point number that corresponds to X = ? What is the normalized binary representation for the number? = = x 2 3 What are the sign, stored exponent, and normalized mantissa? S = 1 (since the number is negative) E = = 130 = = M = X = What is the binary representation for the double-precision floating point number that corresponds to X = ? ΗΜΥ 312 Δ14-15 Αριθµητική

52 Special cases: Denormalized Numbers The first special case deals with very small values. The small numbers for an 8-bit IEEE 754 representation gives the distribution illustrated below. Smallest representable positive number is 2 7 = 1/128 ( ) and largest representable negative number is 2 7 = 1/128 ( ), however, they are separated by a large gap (which skips over zero!) To handle this, small numbers (drawn as hollow blue circles above) are Represented differently in order to be spread evenly across the range, yielding the hollow red points below. ΗΜΥ 312 Δ14-15 Αριθµητική.103 Special cases: Denormalized Numbers To handle this, small numbers (drawn as hollow blue circles above) are Represented differently in order to be spread evenly across the range, yielding the hollow red points below. Denormalized numbers have an exponent (E) of zero, which is then fixed to -6 (for 8-bit representations), and the mantissa (M) has and implied 0 before it (instead of 1). ex denormalized format: normalized format: ΗΜΥ 312 Δ14-15 Αριθµητική

53 Special cases: Zero, Infinity and NaNs Zero is represented using 0 for the exponent and 0 for the mantissa. Either, +0 or -0 can be represented, based on the sign bit. Result of operation overflows, i.e., is larger than the largest number that can be represented overflow is not the same as divide by zero (raises a different exception) +/- infinity S It may make sense to do further computations with infinity e.g., X/0 > Y may be a valid comparison Not a number, but not infinity (e.q. sqrt(-4)) invalid operation exception (unless operation is = or =) NaN S non-zero NaNs propagate: f(nan) = NaN HW decides what goes here ΗΜΥ 312 Δ14-15 Αριθµητική.105 Basic Addition Algorithm For addition (or subtraction) this translates into the following steps: (1) compute Ye - Xe (getting ready to align binary point) Xe-Ye (2) right shift Xm that many positions to form Xm 2 Xe-Ye (3) compute Xm 2 + Ym if representation demands normalization, then normalization step follows: (4) left shift result, decrement result exponent (e.g., 0.001xx ) right shift result, increment result exponent (e.g., 11.1xx ) continue until MSB of data is 1 (NOTE: Hidden bit in IEEE Standard) (5) if result is 0 mantissa, may need to zero exponent by special step Note: Book also gives algorithm for floating point multiplication - look over. and see ΗΜΥ 312 Δ14-15 Αριθµητική

54 Rounding Digits normalized result, but some non-zero digits to the right of the significand --> the number should be rounded E.g., Base = 10, p = 3: = * 10 2-bias 2-bias = * 10 2-bias = * 10 IEEE Standard 754: four rounding modes: round to nearest (default) round towards plus infinity round towards minus infinity round towards 0 See ΗΜΥ 312 Δ14-15 Αριθµητική.107 Table Lookup Arithmetic Def n Given an m-variable function f(x m-1, x m-2,, x 1, x 0 ) the table lookup evaluation of f requires the construction of a 2 u x n table that holds, for each combination of input values (needing a total of u-bits to represent), the desired n-bit result. The u-bit string is obtained by concatenating the input values to form the table address. The n-bit value is the content of the table corresponding to that address. ΗΜΥ 312 Δ14-15 Αριθµητική

55 Arithmetic by Table Lookup Advantages» memory is denser and can be made more robust than random logic» reduces the cost of hardware development» more flexible (allows last minute design changes)» reduces the number of building blocks Disadvantages» slow for large tables» table size grows exponentially in input size ΗΜΥ 312 Δ14-15 Αριθµητική.109 Direct Table Lookup Operand(s) u bits 2 u x n Table (ROM or RAM) Result(s) n bits Unary (single variable) functions (1/x, ln x, x 2 ) limited to 12 to 16 bits of operand precision (2 12 to 2 16 table) Binary functions (xy, x/y, x y ) limited to 8 bits of operand precision (2 8+8=16 table) ΗΜΥ 312 Δ14-15 Αριθµητική

56 Indirect Table Lookup One way to reduce the table size is to see if the binary function can be converted into a unary function (requires pre- and postprocessing logic) Operand(s) u bits Preprocessing Logic Smaller Table(s) (ROM or RAM) ΗΜΥ 312 Δ14-15 Αριθµητική.111 Much smaller than u! Postprocessing Logic Result(s) n bits Indirect Table Lookup Example Pre- and post-processing hardware should be simple and fast Consider the multiplication identity that converts the problem to one of squaring X * Y = ¼ [(X + Y) 2 (X Y) 2 ]» Preprocessing does X+Y and X-Y» Two tables to lookup (X+Y) 2 and (X-Y) 2» Post-processing does subtract and 2-bit right shift ΗΜΥ 312 Δ14-15 Αριθµητική

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