# ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

Save this PDF as:

Size: px
Start display at page:

Download "ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015"

## Transcription

1 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name (please print) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions of the Honor Code. Signed total

2 Problem 1 (20 points) Optimization Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f and g are pure functions that each return an integer with no side effects to other data structures. int mycode(int w, int z) { int x = 256; int y = 1; while (y<x+z) { if (x) z = f(w*x, y, z+w*x); else z = g(z+w*x, y, w*x); printf("y:%d, z:%d\n",y,z); y += z; while (x>0) printf(%d\n, g(y, --x, z); return y; Briefly describe which standard compiler optimizations you applied:

3 Problem 2 (2 parts, 20 points) Conditionals: Compound Predicates Part A (8 points) Consider the following MIPS code fragment. The comment indicates which variable each register holds. These variables are of type int and are initialized elsewhere. Label Instruction Comment slt \$8, \$3, \$0 bne \$8, \$0, Next slti \$8, \$3, 26 beq \$8, \$0, Next addi \$9, \$9, 1 Next: addi \$2, \$2, 1 # \$2: I, \$3: C, \$9: Count, \$8: temp What is the equivalent C code fragment? For maximum credit, use a compound logical predicate wherever possible. Part B (12 points) Turn this C code fragement into the equivalent MIPS code. Assume \$1 holds A, \$2 holds B, \$3 holds C and \$4 holds D. For maximum credit, include comments and use a minimal number of instructions. if (A && B) C = C D; else C = C & D; D = C * 8; Label Instruction Comment 3

4 Problem 3 (3 parts, 24 points) Associative Sets and 3D Arrays Part A (8 points) Suppose we have an associative set of 125 (key, value) pairs implemented as a sorted singly linked list. An application performs 1500 lookups of various keys: 1200 of the lookups find the key in the list and 300 lookups fail to find the key. The keys that are found are distributed throughout the list so that each position is equally likely to be where a key is found. What is the average number of key comparisons that would be needed for a lookup in this list implementation? (Show work. Note: you may not have to use all data provided.) number of comparisons: Part B (8 points) Suppose the associative set is reimplemented as an open hash table. The same 125 (key, value) pairs are stored in the hash table and are evenly distributed across 25 buckets, each implemented as an unsorted singly linked list. An application performs the same 1500 lookups in which 1200 find the key being searched for and 300 do not. The keys that are found are distributed throughout the bucket lists so that each bucket and each position in the bucket lists is equally likely to be where a key is found. What is the average number of key comparisons that would be needed for a lookup in this hash table implementation? (Show work. Note: you may not have to use all data provided.) number of comparisons: Part C (8 points) Suppose we have a video snippet containing L image frames, where each frame has width w and height h pixels. Complete the following procedure which sets a pixel at position(x, y)in frame number f to Color, where y gives the row and x gives the column, with (0, 0) at the top lefthand corner of the image frame, as in Project 3. Assume L, w and h are globally defined. VideoPixels is a pointer to the base of the video pixel array containing all L image frames in a contiguous linear sequence starting with the first pixel in the first row of frame 0 and ending with the last pixel in the last row of frame L-1. void SetPixel(int x, int y, int f, uint32_t* VideoPixels, uint32_t Color){ 4

7 Problem 6 (40 points) Activation Frames The function Bar (below left) calls function Foo after completing code block 1. Write MIPS assembly code that properly calls Foo. Include all instructions between code block 1 and code block 2. Symbolically label all required stack entries and give their values if they are known (below right). int Bar() { int A[] = {25, 36, 49; int B = 3; int *P; (code block 1) Bar s FP 9900 XXX XXX 9896 A[2] A[1] A[0] B 3 SP P P = &B; A[2] = Foo(A, P, *P); (code block 2) label instruction comment # compute &B # update P # allocate activation frame # preserve bookkeeping info # push inputs jal Foo # call Foo # restore bookkeeping info # read return value # store return value in A[2] # deallocate activation frame 7

### ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam Solutions 29 April 2015

Problem 1 (20 points) Optimization Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f and g are pure functions

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Q1: /30 Q2: /25 Q3: /45. Total: /100

ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

### ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Spring problems, 5 pages Exam Three 8 April Your Name (please print clearly)

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### 2. dead code elimination (declaration and initialization of z) 3. common subexpression elimination (temp1 = j + g + h)

Problem 1 (20 points) Compilation Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f is a pure function

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam Solutions 9 December 2015

Problem 1 (20 pos) Optimization Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume square, f, and g are

### MIPS Instruction Reference

Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

### Assembly Programming

Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

### ECE 2035 Programming HW/SW Systems Fall problems, 5 pages Exam Three 19 November 2014

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### MIPS Reference Guide

MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

### F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

### Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,

### Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

### Week 10: Assembly Programming

Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 \$d, \$s, \$t \$d = \$s + \$t addu 100001 \$d, \$s, \$t \$d = \$s + \$t addi 001000 \$t, \$s, i \$t = \$s +

### ECE 2035 Programming Hw/Sw Systems Spring problems, 8 pages Final Exam Solutions 1 May 2013

Problem 1 (3 parts, 30 points) Compilation, Concurrency & Interrupts Part A (20 points) Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version

### ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

### Computer Architecture. The Language of the Machine

Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

### Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

### ECE 2035 A Programming HW/SW Systems Spring problems, 5 pages Exam Three 13 April Your Name (please print clearly)

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand; do not leave your seat. Please work the exam in pencil and do not separate

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam Solutions 14 December 2016

Problem 1 (20 points) Optimization Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume cube, g, and h are

### ECE 2035 Programming HW/SW Systems Fall problems, 5 pages Exam Three 28 November 2012

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### The MIPS Instruction Set Architecture

The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

### MIPS Instruction Set

MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

### SPIM Instruction Set

SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

### CS 61c: Great Ideas in Computer Architecture

MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: \$s0-\$s7,\$t0-\$t9, \$0

### Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

### 101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

### ECE Exam I February 19 th, :00 pm 4:25pm

ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

### Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

### MIPS%Assembly% E155%

MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage \$0 0 the constant value 0 \$at 1 assembler temporary

### TSK3000A - Generic Instructions

TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

### EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

### MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

### ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

### CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

### 5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

### Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

### ECE 2035 Programming HW/SW Systems Fall problems, 4 pages Exam Three 14 November Your Name (please PRINT clearly) Signed.

Your Name (please PRINT clearly) Your Student Number (9 digit) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this

### Arithmetic for Computers

MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.

### MIPS Instruction Format

MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

### Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative

### ECE 2035 Programming HW/SW Systems Fall problems, 5 pages Exam Three 18 November 2015

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register \$2 then

### Programming the processor

CSC258 Week 9 Logistics This week: Lab 7 is the last Logisim DE2 lab. Next week: Lab 8 will be assembly. For assembly labs you can work individually or in pairs. No matter how you do it, the important

### ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 \$zero all bits are zero 16 \$s0 local variable 1 \$at assembler temporary 17 \$s1 local

### Q1: /14 Q2: /12 Q3: /8 Q4: /8. Total: /42

ECE 2035(B) Programming for Hardware/Software Systems Spring 2013 Exam Three April 10 th 2013 Name: Q1: /14 Q2: /12 Q3: /8 Q4: /8 Total: /42 1/10 For functional call related questions, let s assume the

### Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

### CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

### MIPS Assembly Language. Today s Lecture

MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

### Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

### Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1

Part II Instruction-Set Architecture Jan. 211 Computer Architecture, Instruction-Set Architecture Slide 1 MiniMIPS Instruction Formats op rs rt 31 25 2 15 1 5 R 6 bits 5 bits 5 bits 5 bits I J Opcode Source

### Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter

### Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### CSc 256 Final Fall 2016

CSc 256 Final Fall 2016 NAME: Problem 1 (25 points) Translate the C/C++ function func() into MIPS assembly language. The prototype is: void func(int arg0, int *arg1); arg0-arg1 are in \$a0- \$a1 respectively.

### Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers \$0 \$31 Multiply divide Coprocessor 1 (FPU) Registers

### Lec 10: Assembler. Announcements

Lec 10: Assembler Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University Announcements HW 2 is out Due Wed after Fall Break Robot-wide paths PA 1 is due next Wed Don t use incrementor 4 times

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq \$12, \$0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

### ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

### M2 Instruction Set Architecture

M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

### CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble \$12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

### Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

### Examples of branch instructions

Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

### CS61c MIDTERM EXAM: 3/17/99

CS61c MIDTERM EXAM: 3/17/99 D. A. Patterson Last name Student ID number First name Login: cs61c- Please circle the last two letters of your login name. a b c d e f g h i j k l m n o p q r s t u v w x y

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

### ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32

### EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW

1 2 EE 109 Unit 13 MIPS Instruction Set Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 4 Instruction Set Architecture (ISA) Defines the of the processor and memory system Instruction set

### Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

### Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

### MACHINE LANGUAGE. To work with the machine, we need a translator.

LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have

### A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

### MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register

### Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects

### Computer Architecture Experiment

Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

### Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

CS6C L9 MIPS Logical & Shift Ops, and Instruction Representation I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I 25-9-28

### MIPS Assembly Language

MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

### Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing

### Midterm. Sticker winners: if you got >= 50 / 67

CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.

### INSTRUCTION SET COMPARISONS

INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES

### Lecture 7: Procedures

Lecture 7: Procedures CSE 30: Computer Organization and Systems Programming Winter 2010 Rajesh Gupta / Ryan Kastner Dept. of Computer Science and Engineering University of California, San Diego Outline

### CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned

### Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework