CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

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1 CS COPTER ARCHITECTRE & ORGANIZATION SPRING DE : arch 6, HOEWORK III READ : i) Related portions of Chapter (except Sections. through.) ii) Related portions of Appendix A iii) Related portions of Appendix B iv) Related portions of Appendix D ASSIGNENT : There are four questions. Solve all homework and exam problems as shown in class and past exam solutions. ) The registers of an imaginary digital system are manipulated as shown in the state diagram below. The registers are bits wide. REGA REGB REGC REGA + REGD REGA + REGC REGB REGD >> 5 Show the content of the registers in HE for six (6) clock periods, by continuing the table below. Show how the shift operation generates its result, by working on its bits in a separate area. Clock period State REGA REGB REGC REGD Initial ??? NS NS NS NS Continue NY School of Engineering Page of 8 Handout No: 8 arch 5,

2 ) Repeat Problem above for the state diagram below. The registers are bits wide. [REGA] REGB ; REGC REGC - REGB REGB + REGB [REGA] ; REGA REGA + 6 REGA INP ; REGC INP REGC = Reset = 5 REGC = Reset = Assuming that Reset is, show the content of the registers in HE for six (6) clock periods, by continuing the table below. Clock period State Reset REGA REGB REGC [] Initial ?? E NS NS NS NS NS Continue In a few sentences, describe what this digital system does, how it operates. ) Consider the EY CP design with nine (9) integer instructions. We decide to expand the design by adding a IPS instruction in the IPS architecture : JR (Jump Register). odify the EY CP, except the control unit, to run the JR instruction. In order to solve this question, you will assume the CP is a multicycle CP. You will use the NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

3 EY CP handout, by xeroxing it and modifying the necessary pages of the xeroxed copy. If you do not want to copy and modify the handout, you can just show the changes to the datapath as done in past exam questions below. In this question you will modify the EY CP so that it can execute the JR instruction. In order to do that you will follow steps III(b) and IV in the Digital System Design Basics handout. That is, you need to modify the high-level state diagram (not in terms of buses) in parallel with the modification of the datapath. If you decide to add new states, start at state 6. ) Repeat problem above for the JAL instruction. In order to solve this question, you will assume the CP is a multicycle CP. You will use the EY CP handout, by xeroxing it and modifying the necessary pages of the xeroxed copy. If you do not want to copy and modify the handout, you can just show the changes to the datapath as done in past exam questions below. In this question you will modify the EY CP so that it can execute the JAL instruction. In order to do that you will follow steps III(b) and IV in the Digital System Design Basics handout. That is, you need to modify the high-level state diagram (not in terms of buses) in parallel with the modification of the datapath. If you decide to add new states, start at state 6. RELEVANT QESTIONS AND ANSWERS Q) The architectural description of a machine language instruction has at least three components : a syntax, an instruction format and what semantics (the architectural operation) the CP has to perform. An architectural operation is implemented by several microoperations. For example, the LW instruction of the EY computer in its I- format has the following syntax and semantics: LW Rt, Disp(Rs) Rt [Rs + Displ + ] We know that this architectural operation is performed by those microoperations in states,,, and. Computer architects at our company have six new instructions to add to the nine-instruction set executed by the EY CP of Handout. The architecture group assures you that the new instructions do not need a new instruction format. You, as a computer organization expert, do not want to modify the data unit for a new instruction also. They assure you about that too. They have given you the architectural operation list for these new instructions : I : + Rt I : [Rs + Displ + ] I : [Rs + Displ + ] Rt I : Rt Rs + Imm + I5 : [Rd + Rt] [Rs + Rt] I6 : Rs Rt You want to make sure that the architects assurances are correct. So, for every instruction above : NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

4 i) State the syntax and briefly what the instruction does, ii) If the architectural operation can be implemented by modifying the high-level state diagram, but without modifying the data unit, modify the high-level state diagram (not in terms of buses), starting at state 6, iii) If the architectural operation cannot be implemented without modifying the data unit, state briefly the reason. A) I) i) nconditional Branch by using Rt as an offset ==> BN Rt ii) This operation can be implemented by the original EY as follows : from State BN 6 + B to State I) i) Jump via memory Indirect. Location Rs + Displ + has the effective address ==> JPI Displ(Rs) iii) This cannot be implemented since the RBS is not connected to 6. I) i) Exchange the content of memory location Rs + Displ + and Rt ==> ECR Rt, Displ(Rs) iii) This cannot be implemented since the RBS that has [Rs + Displ + ] cannot be saved in the CP temporarily while Rt is written to the location : we need another temporary register besides ALout. I) i) The ADD Immediate instruction of EY from Chapter ==> ADDI Rt, Rs, Imm ii) This can be implemented as follows : from State ADDI 6 ALout A + DOImm + GPR[Rt] 7 ALout to State I5) i) Copy the content of memory location Rs + Rt to memory location Rd + Rt ==> OVT Rd, Rt, Rs iii) This cannot be implemented since we need at least one more organizational register besides ALout to keep the second memory address. I6) i) Exchange register Rt with register Rs ==> ECR Rt, Rs iii) This cannot be implemented : We need another register besides ALout to keep one of the architectural registers temporarily while we move the other. Also we need another input to to select Rs as a Write Register and extra lines are needed to move Rt and Rs either through the AL or around the AL to the temporary registers. Q) The EY CP is designed as shown in class. We modify its architecture! We add a new machine language instruction to the instruction set. Its description is as follows : Syntax : ADDR Rt, Rs, Offset Architectural operation : Rt <--- Rs + [ + ([DOImm + ]<<)] The format : The I format. Which addressing modes are used for the arguments of the ADDR instruction? NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

5 Show the modified high-level state diagram. Show the modified portion of the data unit. A) The addressing modes are as follows : Rt <--- Rs + [ + ([DOImm + ]<<)] Register Register -byte signed -relative We use the register addressing mode for the destination register argument since it is explicitly specified in the instruction. Similarly, the first source argument is a register and is explicitly specified in the instruction and so the register addressing mode is used. The other source argument is a memory location whose address is calculated by adding and the -byte signed offset that comes with the instruction. Therefore we use the -byte signed -relative addressing mode for it. The modified high-level state diagram (not in terms of buses) and the datapath are as follows : ADDR LW, SW From state A/L R-format control <-- [ALout] 6 ALout <-- A + To state 7 GPR[Rt] <-- ALout We see that the only new microoperation is in state 6 in which we add and ALout. The datapath modification is then as follows : ABS Zero To Same 5 ALSrcB NY School of Engineering Page 5 of 8 CS Handout No : 8 arch 5, BBS AL overflow OBS

6 Q) Consider the following modified EY high-level state diagram (not in terms of buses) : LW LW,? 6 LW, SW,?? 5 SW ALout <-- + B A/L R-format To state BEQ, J states 6 - : as before To state To state 7 GPR[Rt] <-- ALout To state The high-level state diagram is modified to accommodate a new instruction. i) Describe what the instruction does in a few sentences. ii) Describe its syntax, semantics, format, etc. iii) What is the CPI i of the new instruction? Explain. iv) odify the EY CP datapath. v) odify the EY CP low-level state diagram. A) i) The instruction adds a register and a memory location and stores the result on the register. ii) The syntax of the new instruction : ADDR Rt, Disp(Rs) The semantics of the new instruction : Rt <--- Rt + [Rs + Disp + ] The format is the I format : Three arguments are used by the instruction : The destination and the first source arguments are register arguments : Rt. We use the register addressing mode for them. The second source argument is a memory argument. We use the -byte signed displacement addressing mode for it. iii) The CPI i is six (6) since we trace states,,,, 6 and 7. iv) The modified EY CP datapath is as follows : To A ALSrcA NY School of Engineering Page 6 of 8 CS Handout No : 8 arch 5,

7 v) The modified EY CP low-level state diagram is as follows : Same except ALsrcA = LW, SW, ADDR Same except ALsrcA = Same except ALsrcA = A/L R-format Control LW, ADDR SW LW 5 ADDR To state 6 ALSrcA = ; ALSrcB = states 6 - : as before, except in states 6 & 8 : ALSrcA = To state ; ALop = To state 7 RegDst = ; emtoreg = ; RegWrite = To state Q) Consider the state diagram of a digital system shown below : AR IR [AR] ; + AR + (,, IR[-]) IR[5] = IR[5] = 7 [AR] If ACC == ACC ACC + IR[] = IR[] = 5 ACC AR 6 [AR] NY School of Engineering Page 7 of 8 CS Handout No : 8 arch 5,

8 Assume that all the registers of the digital system are 6 bits long. The memory has 6 bytes and 6 bits per location. By giving explanations, show the contents of registers and memory locations used by the above state diagram for six (6) clock periods. For that continue with the following table : Clock period State AR IR ACC [] [] Initial -----??? A 7 NS NS NS NS NS NS NS A) The table is continued below : Clock period State AR IR ACC [] [] Initial -----??? A 7 NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS NS 5 NS NS NS 7 NS NS NS 6 NS NS NS NS NS NS In state, AR is transferred () plus the rightmost bits of IR ( = ) catenated with two zeros ( = ). AR is transferred + = We do state after state because the leftmost bit of IR (IR[5]) is zero :. We do state after state because IR[] is also zero : In state, ACC is transferred ACC (A) plus (7). ACC is transferred. Q5) Consider the following mnemonic machine language subroutine : 5C LW R8, (R9) 5 SW R, (R9) 5 ADD R, R8, R 58 JR R NY School of Engineering Page 8 of 8 CS Handout No : 8 arch 5,

9 Continue filling in the following table until the ID cycle of the JR instruction is completed : cp State Source IR AL SrcB Reg Write A B R8 R9 R ALout [] Initial C? ??? F7? 8A NS NS?? NS NS NS? NS 5 LW R8, (R9)?? NS NS NS? NS Note that the values are shown right before the end of the clock period. Briefly describe what the subroutine does (in one sentence). A5) The table is as follows : cp state Source IR AL SrcB Reg Write A B R8 R9 R ALout [] Initial C -- --??? F7? 8A NS NS?? NS NS NS? NS 5 LW R8,(R9)?? NS NS NS 5 NS NS NS? NS NS NS 5 NS NS NS? NS NS NS NS 5 NS NS? NS NS NS? NS 6 NS NS? 8A NS NS? NS 7 5 SW R,(R9)? NS NS NS 5 NS 8 NS NS F7 NS NS NS 5 NS 9 5 NS NS F7 NS NS NS NS NS NS F7 NS NS NS 8B F7 58 ADD R,R8,R NS NS NS 58 NS 6 NS NS 8A NS NS NS 598 NS 7 NS NS 8A NS NS NS 8A NS NS NS 8A NS NS 8A 58 NS 5 5C JR R? NS NS NS 5C NS In clock period 5, the value of regsiter A is the value of R. As we know R contains the return address from the subroutine. The subroutine exchanges a memory location whose address is R9 + Displ + with register R. That is, it implements I of Past Exam Question above. NY School of Engineering Page 9 of 8 CS Handout No : 8 arch 5,

10 Q6) Assume that the EY CP high-level state diagram is modified to be able to run a new machine language instruction as follows :... States - 5, 7 - All other A/L R type A/L R type,? 6? 6 [ALout] GPR[Rd] 7 Assume that in state 6, an addition is performed for this new instruction. i) What is the new instruction? That is, determine its syntax, semantic, etc. If there is a new addressing mode that is not discussed in class, indicate so. ii) odify the EY CP datapath accordingly. How long does it take to run the new instruction? iii) odify the EY CP low-level state diagram accordingly. A6) i) On the high level state diagram, we see that we read a memory location and store the content on a register : It is a Load instruction : Load Word via Register Indirect (LWRI) Syntax : LWRI Rd, (Rs, Rt) Semantics : Rd [Rs + Rt] Format : It uses the R format since register Rd is specified. It has two arguments. The destination argument is a GPR register which is explicitly specified by the instructions. Therefore, the Register addressing mode is used. The source argument is a memory location content. The address of the location is the sum of Rs and Rt. Therefore, it is the Register Indirect Indexed addressing mode. This is a new addressing mode, not discussed in class. We make two memory accesses for the new instruction : One to fetch the instruction (state ) One to read a data element from the memory (state 6) ii) The new instruction does not need any change in the datapath, given the high-level state diagram. The new instruction takes five clock periods to run. That is, CPI LWRI is 5 since we trace states,, 6, 6 and 7 NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

11 iii) The modified EY low-level state diagram is as follows : Same..... States - 5, 7 - All other A/L R format 6 6 Same Same A/L R format, LWRI LWRI emread = IorD = 7 emtoreg = RegDst = RegWrite = Q7) Consider the following instruction that does not exist in the EY instruction set : COPR Rd, (Rs), Rt # If [Rs] < Rt then Rd else Rd i) odify the EY CP high-level state diagram and the datapath to be able to run the new instruction, as done in class. What is CPI COPR? How many memory accesses are made for this new instruction? ii) The new datapath allows new microoperations. List at least four () new microoperations. A7) i) The modified high-level state diagram and datapath of this high-speed implementation are shown below. 6 COPR [A] LW, SW Control A/L R-format ALout A A 7 ALout op B States - : Same IorD ALSrcA 8 GPR[Rd] ALout We perform an slt operation in state 7 for the COPR instruction. CPI COPR is 5 since we trace states,, 6, 7 and 8 NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

12 We make two memory accesses for the new instruction : - One to fetch the instruction (state ) - One to read a data element from the memory (state 6) ii) Two new microoperations are shown in states 6 and 7 above. Below is a partial list of remaining new microinstructions : a) IR [A] b) [A] B c) ALout + B d) ALout + e) ALout + DOImm + f) ALout + ((DOImm + )*) Continue this group with other op operations as the operation... g) + B h) + i) + DOImm + j) + ((DOImm + )*) Continue this group with other op operations as the operation... k) If = = B then ALout l) If = = then ALout m) If = = DOImm + then ALout n) If = = ((DOImm + )*) then ALout Continue this group by replacing ALout with the sources listed in c, d, e, f,... Q8) Assume that the EY CP high-level state diagram is modified to be able to run a new machine language instruction as shown below : States - : Same... LW, SW LW, SW,?? 6 [B] ALout 7 GPR[Rt] B + a) What is the new instruction? That is, determine its syntax, semantics, etc. If there is a new addressing mode that is not discussed in class, indicate so. b) i) odify the EY CP datapath accordingly. ii) How long does it take to run the new instruction? Explain. NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

13 A8) a) On the high level state diagram, we see that we add register Rs and a signed immediate element and store the result in memory pointed by register Rt and then we automatically update register Rt : It is an Add instruction that writes to the memory (ADDRI) : Add Register Immediate emory Syntax : ADDRI (Rt)++, Rs, Imm Semantics : [Rt] Rs + Imm + then Rt Rt + Format, etc. : It uses the I format since an immediate data element is used. It has six arguments. The destination argument of the first addition operation is a memory location. The address of the location is indicated by Rt. Therefore, it is the Register Indirect addressing mode. This is a new addressing mode, not discussed in class The sources of the first addition operation are a register and an immediate data element. We use the Register and -byte signed Immediate addressing modes, respectively. All the arguments of the second addition are implied and are using the Implied addressing mode. The destination argument is register Rt. One of the source arguments is also register Rt. The other source is a constant which is. We make two memory accesses for the new instruction : One to fetch the instruction (state ) One to write a data element to the memory (state 6) b) i) The new instruction requires the following changes in the datapath : ALout B ALout OBS A B ALout 7 WBS IorD emtoreg ALSrcA SelWBS ii) The new instruction takes five clock periods to run : CPI ADDRI is 5 since we trace states,, 6, 6 and 7 Q9) The EY CP is modified to run new instructions. When the new CP runs instructions, its control signals are observed for four clock periods. Only the following control signals are (one) in these four clock periods : clock period Control signals that are (one) 57 emread, IRWrite, ALSrcB, Write 58 ALSrcB ALSrcA, ALSrcB, ALop, Source, WriteCond Note that ALSrcB has two wires, named ALSrcB and ALSrcB, and so on... State which state and which microoperation(s) in that state happen(s) in which clock period. Your explanation should be in the following form : In clock period... ALSrcA is,... therefore, we have the following microoperation(s) and the following state... A9) The states are as follows : NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

14 clock period State and microoperations 57 emread =, IRWrite =, ALSrcB =, Write = exactly the as state of the low-level state diagram IR <--- [], < ALSrcB = exactly the as state of the the low-level state diagram ALout <--- + ([DOImm + ] << ) 59 All control signals are, that is ALSrcA = => ABS = ALSrcB = => BBS = B ALop = => Add a new state, state 6, of the low-level state diagram ALout <--- + B 6 ALSrcA = => ABS = A ALSrcB = => BBS = (DOImm + )<< ALop = => Sub Source = => BS = ALout WriteCond = => is written if the subtraction results in zero = a new state, state 7, of the low-level state diagram If (A== ((DOImm + )<<)) then <--- ALout Q) Assume that the EY CP high-level state diagram is modified to be able to run a new instruction we will call Ix as follows : States - 9 : Same... All other LW SW LW, SW, Ix ALout A + DOImm + LW, Ix [ALout] Ix & [ALout] > 6 7 [ALout] - Ix & [ALout] < a) odify the EY CP datapath accordingly. What is CPI Ix? Explain. NY School of Engineering Page of 8 CS Handout No : 8 arch 5,

15 b) Assume that the new instruction is run and Rs has 8 and DOImm is. Continue with the following table until the effect of the new instruction is visible on the architecture : Clock period State A ALout [?] Initial ----??? A Continue A) a) The new instruction requires a number of changes in the datapath as shown below. The ALout register has a new control signal so that it is not clocked every clock period. Its value computed in state is needed in state 7: A ALSrcA B DOImm + DOImm + * ALSrcB 5 RBS OBS Sel 7 B WSel 8 WBS ALoutWrite ALout This instruction takes the absolute value of the content of a memory location. Therefore, CPI Ix depends on the value of the content. i) If it is negative, the CPI Ix 6 since we trace states,,,, 6 and 7. ii) If it is positive, the CPI Ix since we trace states,, and. b) The table is completed as follows : Clock period State A ALout [?] Initial ----??? A NS? NS? NS? NS? NS NS 8? NS NS 8 8? NS 5 6 NS 8 NS A NS 6 7 NS 8 NS 6 NS 7 NS 8 NS? 6 Q) Consider the following instruction that does not exist in the EY instruction set : JP Disp(Rs) # [Rs + Disp + ] The Jump via emory (JP) instruction loads with an address read from the memory. a) odify the EY CP high-level state diagram, as done in class. What is CPI JP? Explain. b) odify the EY CP datapath accordingly. NY School of Engineering Page 5 of 8 CS Handout No : 8 arch 5,

16 A) a) The modified EY low-level state diagram is as follows : b) The datapath change is as follows : LW, JP JP 6 LW, SW, JP A/L Control R-format SW LW States - 9 : Same OBS ALout ([:8], Address)* 88 Source 6 BS CPI JP is 5 since we trace states,,, and 6. Q) Assume that the EY CP high-level state diagram is modified to be able to run a new instruction as follows : States - 9 : Same... All other LW LW, SW,? SW LW,? [ALout]? - 6 [ALout] 7 a) odify the EY CP datapath accordingly. What is CPI?? Explain. NY School of Engineering Page 6 of 8 CS Handout No : 8 arch 5,

17 b) Assume that the new instruction is run and Rs has A. Also, DOImm is. Continue with the following table until the effect of the new instruction is visible on the architecture : Clock period State A ALout [?] emory Accesses ade Initial ---- F??? AF Continue A) a) The new instruction requires a number of changes in the datapath as shown below. ALout has a new control signal so that it is not clocked every clock period. Its value computed in state is needed in states and 7 : A B DOImm + DOImm + * ALSrcA 5 ALoutWrite ALout RBS Sel 7 wbussel B 8 WBS ALSrcB This instruction decrements the content of a memory location : CPI? = 6 since we trace states,,,, 6 and 7. b) The table is completed as follows : Clock period State A ALout [A] emory Accesses ade Initial ---- F??? AF ---- NS?? NS NS Instruction Fetch F?? NS NS NS A? F NS NS A? A NS Data Read 5 6 NS A AF NS NS 6 7 NS A AE NS NS Data Write 7 NS A? NS AE Instruction Fetch Q) Consider the following instruction that does not exist in the EY instruction set : BP Rs, Disp(Rt) # If Rs > then Rt + Disp + NY School of Engineering Page 7 of 8 CS Handout No : 8 arch 5,

18 The Branch Positive (BP) instruction branches if the source register is positive. a) odify the EY CP high-level state diagram, as done in class. What is CPI BP? Explain. b) odify the EY CP datapath accordingly. A) a) The modified EY low-level state diagram is as follows : CPI BP is since we trace states, and States - 9 : Same All other BP 6 If A > then B + DOImm + b) The datapath change is as follows : Write A[] Zero WriteCond WriteCond A B ALSrcA NY School of Engineering Page 8 of 8 CS Handout No : 8 arch 5,

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 CS COPTER ARCHITECTRE & ORGANIZATION SPRING DE : TA HOEWORK IV READ : i) Related portions of Chapter (except Sections. through.) ii) Related portions of Appendix A iii) Related portions of Appendix iv)