The MIPS Processor Datapath

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1 The MIPS Processor Datapath

2 Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath design and Control Unit design using SystemC.

3 Logic Design Fundamentals Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses

4 Logic Design Fundamentals Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element State (sequential) elements

5 Logic Design Fundamentals Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements

6 Logic Design Fundamentals Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information

7 Combinational Elements AND-gate Adder A Y = A & B Y = A + B B + Y A B Y Multiplexer Y = S? I1 : I0 Arithmetic/Logic Unit Y = F(A, B) A I0 I1 M u x Y B ALU Y S F

8 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1

9 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q Clk D Q

10 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later

11 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Write Clk Q Write D Q

12 Clocking Methodology Combinational logic transforms data during clock cycles

13 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element

14 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element

15 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period

16 Building a Datapath Datapath

17 Building a Datapath Datapath Elements that process data and addresses in the CPU

18 Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, muxes, memories,

19 Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, muxes, memories, We will build a MIPS datapath incrementally

20 A Basic MIPS Implementation Memory-reference instructions Load Word (lw) and Store Word (sw) ALU instructions add, sub, AND, OR and slt Branch on equal (beq)

21 Instruction Execution Steps

22 Instruction Execution Steps Instruction Fetch

23 Instruction Execution Steps Instruction Fetch Instruction Decode/Register Fetch

24 Instruction Execution Steps Instruction Fetch Instruction Decode/Register Fetch Execute ALU Effective Address Calculation

25 Instruction Execution Steps Instruction Fetch Instruction Decode/Register Fetch Execute ALU Effective Address Calculation Memory Access

26 Instruction Execution Steps Instruction Fetch Instruction Decode/Register Fetch Execute ALU Effective Address Calculation Memory Access Write back (Update RF)

27 Instruction Fetch Actions

28 Instruction Fetch Actions Read Program Counter

29 Instruction Fetch Actions Read Program Counter Fetch instruction from Instruction memory pointed to by the PC

30 Instruction Fetch Actions Read Program Counter Fetch instruction from Instruction memory pointed to by the PC Increment PC

31 Instruction Fetch Elements

32 Instruction Fetch Elements

33 Instruction Fetch

34 ADD R1, R2, R3 ALU Instructions Operations

35 ALU Instructions Operations Read R2 and R3 from Register file Send 2 and 3 to RF RF reads contents of R2 and R3 ADD R1, R2, R3

36 ALU Instructions Operations Read R2 and R3 from Register file Send 2 and 3 to RF RF reads contents of R2 and R3 Add contents of R2 and R3 in the ALU ADD R1, R2, R3

37 ALU Instructions Operations Read R2 and R3 from Register file Send 2 and 3 to RF RF reads contents of R2 and R3 Add contents of R2 and R3 in the ALU Feed the sum output to the RF; Ask it to write into R1 ADD R1, R2, R3

38 ADD R1, R2, R3 ALU Operations Elements

39 ALU Operations Elements Addr Data REGISTER FILE Data Write ADD R1, R2, R3

40 ADD R1, R2, R3 ALU Operations Elements

41 ADD R1, R2, R3 ALU Operations Elements

42 ADD R1, R2, R3 ALU Operations Datapath

43 ALU Operations Datapath How will the design change for ADDI? ADDI R1, R2, -13

44 ADDI R1, R2, -13 ALU Operations Datapath

45 LW R1, -8(R2) Loads and Stores Actions

46 Loads and Stores Actions Calculate full address Sum of -8 (offset) and contents of R2 (base) Size of offset? Size of contents of R2? LW R1, -8(R2)

47 Loads and Stores Actions Calculate full address Sum of -8 (offset) and contents of R2 (base) Size of offset? Size of contents of R2? Send the address to Data memory LW R1, -8(R2)

48 Loads and Stores Actions Calculate full address Sum of -8 (offset) and contents of R2 (base) Size of offset? Size of contents of R2? Send the address to Data memory DM reads out the contents of Mem[R2+(-8)] LW R1, -8(R2)

49 Loads and Stores Actions Calculate full address Sum of -8 (offset) and contents of R2 (base) Size of offset? Size of contents of R2? Send the address to Data memory DM reads out the contents of Mem[R2+(-8)] Feed the value from memory to the RF; Ask it to write the value into R1 LW R1, -8(R2)

50 LW R1, -8(R2) Loads and Stores Elements

51 Memory and R-type Instructions

52 LW R1, -8(R2) Memory Instruction Load

53 LW R1, -8(R2) Memory Instruction Load

54 LW R1, -8(R2) Memory Instruction Load

55 LW R1, -8(R2) Memory Instruction Load

56 Memory Instruction Load ADD LW R1, -8(R2)

57 Memory Instruction Load ADD LW R1, -8(R2)

58 Memory Instruction Load ADD LW R1, -8(R2)

59 Memory Instruction Load Control Signals: RegWrite=1; ALUSrc=1; ALUoperation=ADD; MemRead=1;MemWrite=0; MemToReg=1;

60 SW R1, -8(R2) Memory Instruction Store

61 Memory Instruction Store ADD SW R1, -8(R2)

62 Memory Instruction Store Control Signals:

63 Memory Instruction Store Control Signals: RegWrite=0; ALUSrc=1; ALUoperation=ADD; MemRead=0;MemWrite=1; MemToReg=X;

64 ADD R1, R2, R3 R Type Instruction ADD

65 ADD R1, R2, R3 R Type Instruction ADD

66 Control Signals: R Type Instruction ADD

67 R Type Instruction ADD Control Signals: RegWrite=1; ALUSrc=0; ALUoperation=ADD; MemRead=X;MemWrite=X; MemToReg=0;

68 ADDI R1, R2, 13 I Type Instruction ADDI

69 ADDI R1, R2, 13 I Type Instruction ADDI

70 I Type Instruction ADDI Control Signals:

71 I Type Instruction ADDI Control Signals: RegWrite=1; ALUSrc=1; ALUoperation=ADD; MemRead=X;MemWrite=X; MemToReg=0;

72 BEQ R1, R2, -16 BEQ Actions

73 BEQ Actions Read R1 and R2 from Register file Send 1 and 2 to RF RF reads contents of R1 and R2 BEQ R1, R2, -16

74 BEQ Actions Read R1 and R2 from Register file Send 1 and 2 to RF RF reads contents of R1 and R2 Send to ALU; Ask it to Subtract BEQ R1, R2, -16

75 BEQ Actions Read R1 and R2 from Register file Send 1 and 2 to RF RF reads contents of R1 and R2 Send to ALU; Ask it to Subtract Read out Zero flag from ALU BEQ R1, R2, -16

76 BEQ Actions Read R1 and R2 from Register file Send 1 and 2 to RF RF reads contents of R1 and R2 Send to ALU; Ask it to Subtract Read out Zero flag from ALU If Z flag == 0; then PC = (PC + 4) 16 BEQ R1, R2, -16

77 BEQ Actions Read R1 and R2 from Register file Send 1 and 2 to RF RF reads contents of R1 and R2 Send to ALU; Ask it to Subtract Read out Zero flag from ALU If Z flag == 0; then PC = (PC + 4) 16 Else if Z flag == 1; then PC = PC + 4 BEQ R1, R2, -16

78 Branches Elements BEQ R1, R2, LABEL BEQ R1, R2, -16

79 Branches Elements BEQ R1, R2, LABEL BEQ R1, R2, -16

80 The MIPS Datapath

81 BEQ R1, R2, -16 The MIPS Datapath BEQ

82 BEQ R1, R2, -16 The MIPS Datapath BEQ

83 BEQ R1, R2, -16 The MIPS Datapath BEQ

84 BEQ R1, R2, -16 The MIPS Datapath BEQ

85 BEQ R1, R2, -16 The MIPS Datapath BEQ

86 BEQ R1, R2, -16 The MIPS Datapath BEQ

87 BEQ R1, R2, -16 The MIPS Datapath BEQ

88 The MIPS Datapath BEQ Control BEQ R1, R2, -16 Signals ::

89 The MIPS Datapath BEQ BEQ R1, R2, -16 Control Signals :: RegWrite=0; ALUSrc=0; ALUoperation=SUB; MemRead=X;MemWrite=X; MemToReg=X; PCSrc=Condition

90 MIPS Datapath and Control Lines

91 Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath design and Control Unit design using SystemC.

92 Backup

93 ALU Instructions ALU instructions (R type), Memory Transfer (effective address calculation), Branches (BEQ) R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits OP rd, rs, rt op: Opcode (class of instruction). Eg. ALU funct: Which subunit of the ALU to activate? I-type op rs rt immediate 6 bits 5 bits 5 bits 16 bits OP rt, rs, IMM

94 ALU Instructions ALU instructions (R type), Memory Transfer (effective address calculation), Branches (BEQ) Identified by Opcode fields and Funct fields

95 ALU Instructions ALU instructions (R type), Memory Transfer (effective address calculation), Branches (BEQ) R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits OP rd, rs, rt op: Opcode (class of instruction). Eg. ALU funct: Which subunit of the ALU to activate? I-type op rs rt immediate 6 bits 5 bits 5 bits 16 bits OP rt, rs, IMM

Processor (I) - datapath & control. Hwansoo Han

Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two