PIC16C63A/65B/73B/74B
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1 PI663A/65B/73B/74B 4.0 MEMORY ORGANIATION 4. Program Memory Organization The PI663A/65B/73B/74B has a 3bit program counter capable of addressing an 8K x 4 program memory space. All devices covered by this data sheet have 4K x 4 bits of program memory. The address range is h 0FFFh for all devices. Accessing a location above 0FFFh will cause a wraparound. The RESET vector is at h and the interrupt vector is at 04h. FIGURE 4: ALL,RETURN RETFIE,RETLW PI663A/65B/73B/74B PROGRAM MEMORY MAP AND STAK P<:0> Stac Level Stac Level Data Memory Organization The data memory is partitioned into multiple bans which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP and RP0 are the ban select bits. RP:RP0 (STATUS<6:5>) = Ban0 = 0 Ban = 0 Ban = Ban3 Each ban extends up to 7Fh (8 bytes). The lower locations of each ban are reserved for the SFRs. Above the SFRs are GPRs, implemented as static RAM. All implemented bans contain SFRs. Frequently used SFRs from one ban may be mirrored in another ban for code reduction and quicer access. Note: Maintain the IRP and RP bits clear in these devices. 4.. GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the File Select Register (FSR) (Section 4.5). RESET Vector h User Memory Space Interrupt Vector Onchip Program Memory (Page 0) Onchip Program Memory (Page ) 04h 05h 07FFh 08h 0FFFh 0h FFFh 0 Microchip Technology Inc. DS30605page 5
2 PI663A/65B/73B/74B FIGURE 4: REGISTER FILE MAP 4.. SPEIAL FUNTION REGISTERS File Address h 0h 0h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0h 0Dh 0Eh 0Fh 0h h h 3h 4h 5h 6h 7h 8h 9h Ah Bh h Dh Eh Fh 0h INDF () TMR0 PL STATUS FSR PORTA PORTB PORT PORTD () PORTE () PLATH INTON PIR PIR TMRL TMRH TON TMR TON SSPBUF SSPON PRL PRH PON RSTA TXREG RREG PRL PRH PON ADRES (3) ADON0 (3) INDF () OPTION_REG PL STATUS FSR TRISA TRISB TRIS TRISD () TRISE () PLATH INTON PIE PIE PON PR SSPADD SSPSTAT TXSTA SPBRG ADON (3) File Address 80h 8h 8h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8h 8Dh 8Eh 8Fh 90h 9h 9h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9h 9Dh 9Eh 9Fh A0h The Special Function Registers are registers used by the PU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The Special Function Registers can be classified into two sets (core and peripheral). Those registers associated with the core functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. General Purpose Register General Purpose Register 7Fh Ban 0 Ban FFh Unimplemented data memory locations, read as 0. Note : Not a physical register. : These registers are not implemented on the PI663A/73B, read as '0'. 3: These registers are not implemented on the PI663A/65B, read as '0'. DS30605page 6 0 Microchip Technology Inc.
3 PI663A/65B/73B/74B 4... STATUS Register The STATUS register, shown in Register 4, contains the arithmetic status of the ALU, the RESET status and the ban select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the, D or bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, LRF STATUS will clear the upper three bits and set the bit. This leaves the STATUS register as 0u uuu (where u = unchanged). It is recommended that only BF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the, or D bits in the STATUS register. For other instructions which do not affect status bits, see the "Instruction Set Summary." Note : These devices do not use bits IRP and RP (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products. : The and D bits operate as borrow and digit borrow bits, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 4: STATUS REGISTER (ADDRESS 03h, 83h) R/W0 R/W0 R/W0 R R R/Wx R/Wx R/Wx IRP () RP () RP0 TO PD D () bit 7 bit 0 bit 7 bit 65 bit 4 bit 3 bit bit bit 0 IRP () : Register Ban Select bit (used for indirect addressing) = Ban, 3 (h FFh) 0 = Ban 0, (h FFh) RP () :RP0: Register Ban Select bits (used for direct addressing) = Ban 3 (80h FFh) 0 = Ban (h 7Fh) 0 = Ban (80h FFh) = Ban 0 (h 7Fh) Each ban is 8 bytes TO: Timeout bit = After powerup, LRWDT instruction, or SLEEP instruction 0 = A WDT timeout occurred PD: Powerdown bit = After powerup or by the LRWDT instruction 0 = By execution of the SLEEP instruction : ero bit = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero D: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) = A carryout from the 4th low order bit of the result occurred 0 = No carryout from the 4th low order bit of the result () : arry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) = A carryout from the most significant bit of the result occurred 0 = No carryout from the most significant bit of the result occurred Note : Maintain the IRP and RP bits clear. : For borrow and digit borrow, the polarity is reversed. A subtraction is executed by adding the two s complement of the second operand. For rotate (RRF,RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 n = Value at POR = Bit is set 0 = Bit is cleared x = Bit is unnown 0 Microchip Technology Inc. DS30605page 9
4 PI663A/65B/73B/74B 4.0 INSTRUTION SET SUMMARY Each PI6XX instruction is a 4bit word divided into an OPODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The PI6XX instruction set summary in Table 4 lists byteoriented, bitoriented, and literal and control operations. Table 4 shows the opcode field descriptions. For byteoriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bitoriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, represents an eight or eleven bit constant or literal value. TABLE 4: Field OPODE FIELD DESRIPTIONS Description f Register file address (0x to 0x7F) W Woring register (accumulator) b Bit address within an 8bit file register Literal field, constant data or label x d Don t care location (= 0 or ) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = : store result in file register f. Default is d = label Label name TOS TopofStac P Program ounter PLATH Program ounter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer/ounter TO Timeout bit PD Powerdown bit dest Destination either the W register or the specified register file location [ ] Options ( ) ontents Assigned to < > Register bit field In the set of italics User defined term (font is courier) The instruction set is highly orthogonal and is grouped into three basic categories: Byteoriented operations Bitoriented operations Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution taes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is µs. Table 4 lists the instructions recognized by the MPASM TM assembler. Figure 4 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 4: To maintain upward compatibility with future PI6XX products, do not use the OPTION and TRIS instructions. GENERAL FORMAT FOR INSTRUTIONS Byteoriented file register operations OPODE d f (FILE #) d = 0 for destination W d = for destination f f = 7bit file register address Bitoriented file register operations OPODE b (BIT #) f (FILE #) b = 3bit bit address f = 7bit file register address Literal and control operations General OPODE = 8bit immediate value ALL and GOTO instructions only (literal) OPODE = bit immediate value (literal) 0 Microchip Technology Inc. DS30605page 99
5 PI663A/65B/73B/74B TABLE 4: Mnemonic, Operands PI6XX INSTRUTION SET Description ycles 4Bit Opcode Status MSb LSb Affected Notes BYTEORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF LRF LRW OMF DEF DEFS INF INFS IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f f Add W and f AND W with f lear f lear W omplement f Decrement f Decrement f, Sip if 0 Increment f Increment f, Sip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through arry Rotate Right f through arry Subtract W from f Swap nibbles in f Exclusive OR W with f BITORIENTED FILE REGISTER OPERATIONS BF BSF BTFS BTFSS f, b f, b f, b f, b Bit lear f Bit Set f Bit Test f, Sip if lear Bit Test f, Sip if Set LITERAL AND ONTROL OPERATIONS ADDLW ANDLW ALL LRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Add literal and W AND literal with W all subroutine lear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W () () () () bb 0bb 0bb bb x 0 0 xx 0xx 0x lfff lfff 0xx0 bfff bfff bfff bfff 0 0,D,,D,,D, TO,PD TO,PD,D, Note : When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, ), the value used will be that value present on the pins themselves. For example, if the data latch is for a pin configured as input and is driven low by an external device, the data will be written bac with a 0. : If this instruction is executed on the TMR0 register (and, where applicable, d = ), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program ounter (P) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.,,,,,,3,,,3,,,,,,,,, 3 3 Note: Additional information on the midrange instruction set is available in the PImicro TM MidRange MU Family Reference Manual (DS3303). DS30605page 0 Microchip Technology Inc.
6 PI663A/65B/73B/74B 4. Instruction Descriptions ADDLW Add Literal and W [label] ADDLW Operands: 0 55 (W) + (W), D, The contents of the W register are added to the eight bit literal and the result is placed in the W register. ANDWF AND W with f [label] ANDWF f,d Operands: 0 f 7 d [0,] (W).AND. (f) (destination) AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. ADDWF Add W and f [label] ADDWF f,d Operands: 0 f 7 d [0,] (W) + (f) (destination), D, Add the contents of the W register with register f. If d is 0, the result is stored in the W register. If d is, the result is stored bac in register f. BF Bit lear f [label] BF f,b Operands: 0 f 7 0 b 7 0 (f<b>) Bit 'b' in register 'f' is cleared. ANDLW AND Literal with W [label] ANDLW Operands: 0 55 (W).AND. () (W) The contents of W register are AND ed with the eight bit literal ''. The result is placed in the W register. BSF Bit Set f [label] BSF f,b Operands: 0 f 7 0 b 7 (f<b>) Bit 'b' in register 'f' is set. 0 Microchip Technology Inc. DS30605page 0
7 PI663A/65B/73B/74B BTFSS Bit Test f, Sip if Set [label] BTFSS f,b Operands: 0 f 7 0 b < 7 sip if (f<b>) = If bit b in register f is 0, the next instruction is executed. If bit b is, then the next instruction is discarded and a NOP is executed instead maing this a TY instruction. LRF lear f [label] LRF f Operands: 0 f 7 h (f) The contents of register f are cleared and the bit is set. BTFS Bit Test, Sip if lear [label] BTFS f,b Operands: 0 f 7 0 b 7 sip if (f<b>) = 0 If bit b in register f is, the next instruction is executed. If bit b, in register f, is 0, the next instruction is discarded, and a NOP is executed instead, maing this a TY instruction. LRW Operands: lear W [ label ] LRW h (W) W register is cleared. ero bit () is set. ALL all Subroutine [ label ] ALL Operands: (P)+ TOS, P<0:0>, (PLATH<4:3>) P<:> all Subroutine. First, return address (P+) is pushed onto the stac. The eleven bit immediate address is loaded into P bits <0:0>. The upper bits of the P are loaded from PLATH. ALL is a twocycle instruction. LRWDT Operands: lear Watchdog Timer [ label ] LRWDT h WDT 0 WDT prescaler, TO PD TO, PD LRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. DS30605page 0 0 Microchip Technology Inc.
8 PI663A/65B/73B/74B OMF omplement f [ label ] OMF f,d Operands: 0 f 7 d [0,] (f) (destination) The contents of register f are complemented. If d is 0, the result is stored in W. If d is, the result is stored bac in register f. GOTO Unconditional Branch [ label ] GOTO Operands: P<0:0> PLATH<4:3> P<:> GOTO is an unconditional branch. The eleven bit immediate value is loaded into P bits <0:0>. The upper bits of P are loaded from PLATH<4:3>. GOTO is a twocycle instruction. DEF Decrement f [label] DEF f,d Operands: 0 f 7 d [0,] (f) (destination) Decrement register f. If d is 0, the result is stored in the W register. If d is, the result is stored bac in register f. INF Increment f [ label ] INF f,d Operands: 0 f 7 d [0,] (f) + (destination) The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in register f. DEFS Decrement f, Sip if 0 Operands: 0 f 7 d [0,] [ label ] DEFS f,d (f) (destination); sip if result = 0 The contents of register f are decremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in register f. If the result is, the next instruction is executed. If the result is 0, then a NOP is executed instead maing it a TY instruction. INFS Increment f, Sip if 0 [ label ] INFS f,d Operands: 0 f 7 d [0,] (f) + (destination), sip if result = 0 The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in register f. If the result is, the next instruction is executed. If the result is 0, a NOP is executed instead maing it a TY instruction. 0 Microchip Technology Inc. DS30605page 03
9 PI663A/65B/73B/74B IORLW Inclusive OR Literal with W [ label ] IORLW Operands: 0 55 (W).OR. (W) The contents of the W register are OR ed with the eight bit literal ''. The result is placed in the W register. MOVLW Move Literal to W [ label ] MOVLW Operands: 0 55 (W) The eight bit literal '' is loaded into W register. The don t cares will assemble as 0 s. IORWF Inclusive OR W with f [ label ] IORWF f,d Operands: 0 f 7 d [0,] (W).OR. (f) (destination) Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is the result is placed bac in register 'f'. MOVWF Move W to f [ label ] MOVWF f Operands: 0 f 7 (W) (f) Move data from W register to register 'f'. MOVF Move f [ label ] MOVF f,d Operands: 0 f 7 d [0,] (f) (destination) The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d =, the destination is file register f itself. d = is useful to test a file register since status flag is affected. NOP No Operation [ label ] NOP Operands: No operation No operation. DS30605page 04 0 Microchip Technology Inc.
10 PI663A/65B/73B/74B RETFIE Return from Interrupt [ label ] RETFIE Operands: TOS P, GIE RLF Rotate Left f through arry [ label ] RLF f,d Operands: 0 f 7 d [0,] See description below The contents of register f are rotated one bit to the left through the arry Flag. If d is 0, the result is placed in the W register. If d is, the result is stored bac in register f. Register f RETLW Return with Literal in W [ label ] RETLW Operands: 0 55 (W); TOS P The W register is loaded with the eight bit literal. The program counter is loaded from the top of the stac (the return address). This is a twocycle instruction. RRF Rotate Right f through arry [ label ] RRF f,d Operands: 0 f 7 d [0,] See description below The contents of register f are rotated one bit to the right through the arry Flag. If d is 0, the result is placed in the W register. If d is, the result is placed bac in register f. Register f RETURN Return from Subroutine [ label ] RETURN Operands: TOS P Return from subroutine. The stac is POPed and the top of the stac (TOS) is loaded into the program counter. This is a twocycle instruction. SLEEP Operands: [ label ] SLEEP h WDT, 0 WDT prescaler, TO, 0 PD TO, PD The powerdown status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 3.8 for more details. 0 Microchip Technology Inc. DS30605page 05
11 PI663A/65B/73B/74B SUBLW Subtract W from Literal [ label ] SUBLW Operands: 0 55 (W) (W), D, The W register is subtracted ( s complement method) from the eight bit literal ''. The result is placed in the W register. XORLW Exclusive OR Literal with W [label] XORLW Operands: 0 55 (W).XOR. (W) The contents of the W register are XOR ed with the eight bit literal ''. The result is placed in the W register. SUBWF Subtract W from f [ label ] SUBWF f,d Operands: 0 f 7 d [0,], D, (f) (W) (destination) Subtract ( s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. XORWF Exclusive OR W with f [label] XORWF f,d Operands: 0 f 7 d [0,] (W).XOR. (f) (destination) Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. SWAPF Swap Nibbles in f [ label ] SWAPF f,d Operands: 0 f 7 d [0,] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is, the result is placed in register 'f'. DS30605page 06 0 Microchip Technology Inc.
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