Computer Engineering Capstone Design Summer A : Handheld Video Games

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1 Computer Engineering Capstone Design Summer A 99 0: Handheld Video Games J. S. McDonald Odd-Wednesday Talks May, 0

2 PIC-Pong By Rickard Gunée; uses a -MHz PICF and a TV(!) the game in action: the game: Slide

3 Original GameBoy Patent Slide

4 GameBoy Patent Drawings Slide

5 GameBoy Block Diagram Slide

6 GameBoy Schematic Slide

7 In a Nutshell Some Details Project Overview (999) Design and build a hand-held video game. The game must use a Microchip PIC CA microcontroller use a Micro Electronics SG graphic LCD module have an appropriate soundtrack and/or sound effects be battery-powered, compact, and sturdily constructed survive evaluation by a dozen th-graders!?!! Slide

8 Project History 99: Original Edition Handheld Video Games : no sound, makeshift buttons and cases Games: Street Fighter, Battleship, Breakout, PIC Pilot 999: Handheld Video Games II : one- or two-track sound, real NES buttons, smaller cases Games: Combat!, Bowling, Go Banana!, Tetris, Missile Command, Duel Tetris, PICman 0: Ultimate Handheld Video Games (as in, the last): custom printed-circuit boards, even smaller cases, in-circuit emulator for development Slide Games:???

9 FIGURE -: OSC PIC Overview Q Internal Harvard architecture (separate instruction and data memories) phase PC -bit instructions -bit data CLOCK/INSTRUCTION CYCLE Q Q Q OSC/CLKOUT (RC mode) Q Q Q Q Q Q Q Q Q Q Q Q PC PC+ PC+ Fetch INST (PC) Execute INST (PC-) Fetch INST (PC+) Execute INST (PC) Fetch INST (PC+) Execute INST (PC+) Single-cycle EXAMPLE -: instruction INSTRUCTION PIPELINE execution FLOW via instruction pre-fetch. MOVLW h Fetch Execute Tcy0 Tcy Tcy Tcy Tcy Tcy. MOVWF PORTB Fetch Execute. CALL SUB_ Fetch Execute. BSF PORTA, BIT (Forced NOP) Fetch Flush. address SUB_ Fetch SUB_ Execute SUB_ clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. -ns instruction cycle Reduced instruction set ( total)... Slide 99 Microchip Technology Inc. DS090E-page

10 CPU a PIC Instruction Set Section. CPU and ALU Table -: Mid-Range MCU Instruction Set Mnemonic, Operands Description Cycles BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d ANDWF f, d CLRF f CLRW - COMF f, d DECF f, d DECFS f, d INCF f, d INCFS f, d IORWF f, d f, d MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f - Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f f, d f, d f, d f, d f, d BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k - k k k - k - - k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W () () () () -Bit Instruction Word Status Bits MSb LSb Affected bb 0bb 0bb bb x 0kkk kkk 0 xx 0xx 0x lfff 0xxx lfff 0xx0 bfff bfff bfffbfff xxxx 0 0 C,DC, C C C,DC, C,DC, TO,PD TO,PD C,DC, Note : When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, ), the value used will be that value present on the pins themselves. For example, if the data latch is '' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. : If this instruction is executed on the TMR0 register (and, where applicable, d = ), the prescaler will be cleared if assigned to the Timer0 Module. : If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Slide 9 Notes,,,,,,,,,,,,,,,,,,

11 Device Program Memory Data Memory (RAM) PICC PICCA PICC K x K x K x PIC 9 x CA 9 x x Program Bus EPROM Program Memory Program Counter Level Stack (-bit) RAM Addr () Data Bus RAM File Registers 9 PORTA PORTB RA0/AN0 RA/AN RA/AN RA/AN/VREF RA/T0CKI RA/SS/AN Instruction reg Direct Addr Addr MUX Indirect Addr RB0/INT FSR reg RB:RB OSC/CLKIN OSC/CLK OUT Instruction Decode & Control Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset W atchdog Timer Brown-out Reset () ALU W reg STATUS reg MUX PORTC PORTD RC0/TOSO/TCKI RC/TOSI/CCP RC/CCP RC/SCK/SCL RC/SDI/SDA RC/SDO RC/TX/CK RC/RX/DT RD/PSP:RD0/PSP0 MCLR V DD, VSS Parallel Slave Port PORTE RE0/RD/AN Timer0 Timer Timer A/D RE/WR/AN RE/CS/AN Synchronous CCP CCP USART Serial Port Note : Higher order bits are from the STATUS register. : Brown-out Reset is not available on the PICC. K program and 9-byte data memories I/Os, including A/D DS090E-page Slide 0 99 Microchip Technology Inc.

12 PICC REGISTER FILE MAP PICCX PIC CA Registers FIGURE -: PICC/A//A REGISTER FILE MAP INDF () TMR0 PCL TATUS FSR PORTA PORTB PORTC CLATH NTCON PIR TMRL TMRH TCON TMR TCON SPBUF SPCON CPRL CPRH CPCON ADRES DCON0 General Purpose Register INDF () OPTION PCL ST ATUS FSR TRISA TRISB TRISC PCLATH INTCON PIE PCON PR SSPADD SSPSTAT ADCON General Purpose Register File Address 0h h h h h h h h h 9h Ah Bh Ch Dh Eh Fh 90h 9h 9h 9h 9h 9h 9h 9h 9h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h File Address h 0h 0h 0h 0h 0h 0h 0h 0h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0h h h h h h h h h 9h Ah Bh Ch Dh Eh Fh INDF () TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD () PORTE () PCLATH INTCON PIR PIR TMRL TMRH TCON TMR TCON SSPB UF SSPCON CCPRL CCPRH CCPCON RCSTA TXREG RCREG CCPRL CCPRH CCPCON ADRES ADCON0 INDF () OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD () TRISE () PCLATH INTCON PIE PIE PCON PR SSP ADD SSPST AT TXSTA SPBRG ADCON 0h A0h Gener al Purpose Register Gener al Purpose Register File Address 0h h h h h h h h h 9h Ah Bh Ch Dh Eh Fh 90h 9h 9h 9h 9h 9h 9h 9h 9h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Bank 0 Bank FFh plemented data memory locations, read as a physical register. Fh FFh Bank 0 Bank Unimplemented data memory locations, read as '0'. Note : Not a physical register. : These registers are not physically implemented on the PICC/A, read as '0'. Slide Technology Inc. DS090E-page

13 Development Environment PICDEM- demonstration board MPLAB IDE (Integrated Development Environment) assembler linker excellent simulator Free for download, with many useful application notes Chipmaster 0 device programmer U-V eraser Slide

14 PICDEM- Demonstration Board 99 Microchip Technology Inc. DS0B-page 9 Appendix A. Hardware Detail Figure A-: PICDEM- Schematic VDD VDD MCLR RA0 RA RA RA RA RA RB0 RB RB RB RB RB RB RB OSC VSS VSS 9 0 U PICC C NMCLR RA0 RA RA RA RA RA RB0 RB RB RB RB RB RB RB RD0 RD RD RD RD RD RD RD OS0 OS RC SCL SDA RC TX RX RB R K 0 C 0.0 LML0 U IN OUT COM W0M CR +9V Battery J DJA C 0 C9 0. VCC 0 9 U MAXA C 0. TX RX V+ TIN TIN ROUT ROUT C+ C- V- TOUT TOUT RIN RIN C+ C- GND C 0. C 0. C 0. 9 J + Notes: Unless otherwise specified, resistance values are in ohms, % /W. Capacitance values are in microfarads. 0. RE0 RE RE RD0 RD RD RD RD RD RD RD RC0 RC RC RC RC RC RC RC OSC R.K S C 0. R.K C 0PF OSC Provision Only RA0 RA RA RA RA RA R S R.K A0 A A SCL WP U SDA LC0B VDD VSS C0 0. X CR N9 +C 0 VDD MCLR RA0 RA RA RA RA RA RB0 RB RB RB RB RB RB RB VSS VSS 0 9 U PICC C NMCLR RA0 RA RA RA RA RA RB0 RB RB RB RB RB RB RB OSC OSC 0. OSC OSC RC0 RC RC RC RC RC RC RC 9 0 OSO OSI RC SCL SDA RC TX RX RE0 RE RE RE R 0K R 0 J 9 0 RA RA RA FOR LCD DSPLY R.K S C9 0. C 0. R 0 R 0 GRN POWER D J Y TBD C 0PF C 0PF Not Populated OUT TXCO RC OSO OSI RC SCL SDA RC TX RX (RC0) (RC) (RC) (RC) (RC) (RC) RD RD0 RD RD RD RD RD RD RD J 9 KEYBOARD 9 PIN HEADER RB0 RB RB RB RN RB RN RB RN RB RN RB RN RB0 RN RB RN RB RN RB RN RB RN RB RN RB RN RB D D D D D D D D9 J J OSC Provision Only, Not Populated Y TBD C 0pF C 0pF R0 0 R 0 R 0 R 0 R9 0 R 0 RA Y J Breadboard R9 0 R 0 R 0 RN Slide

15 MPLAB IDE Slide

16 Block Diagram: LCD Module Overview D-D0 WR RD CE C/D RESET FS VSS VDD VEE Toshiba T9C Controller Bias Circuit Kx bits SRAM x LCD -pixel graphics and/or array of -pixel characters (including user-defined) Slide

17 Graphic LCD Controller (Toshiba T9C) Slide

18 ISD ChipCorder Brags by the Company: Features and Benefits of ChipCorder Products Single-Chip Solution Optimal for lightweight, portable products. Simple Integration No software development required, quick time to market Exceptional Sound Quality Authentic, natural sounding voice and music reproduction Low Power Consumption Ideal for battery-powered applications. Battery-less Voice Storage Power failure protection Low Cost Meets consumer market demands ChipCorder Products Offer: Voice record and playback system on a single chip seconds to minutes record and playback durations Industry-leading sound quality Fully integrated system functions: AGC, mic preamp, speaker drivers, filters, oscillator, memory Low voltage operation Message management Flexible architecture Battery-less message storage Slide

19 ChipCorder Interfacing Interface to a Typical Microcontroller: VCC VCC VCC GND U VDD RESET IRQ PB OSC OSC PA PA PA PA PA PA PA PA0 PB PB0 PB PB PB VSS MHC0JA VCC GND 0 9 U A9 A A A A A A A A A0 CE PD EOM OVF P/R XCLK ISD VCCD VCCA AUX IN SP+ SP- ANA IN 0 ANA OUT MIC REF MIC AGC 9 VSSA VSSD GND R 0 R 0K C.uF J PHONEJACK P PHONEPLUG LS SPEAKER GND Slide Title TALKING THERMOMETER Size Document Number REV

20 ChipCorder Development Quadravox QV- development board and software support programming of.wav files Project window: Waveform editor: Slide 9

21 0: Printed-Circuit Fab Layout for Duel Tetris (using Linux freeware pcb): Fabrication cost at APC: $ for copies Slide 0

22 . Power supply cable. Processor module with cable 0: MPLAB-ICE. Device adapter to connect the processor module to the target system. Logic probe connector MPLAB-compatible In-Circuit Emulation system: Parallel Cable Emulator Pod Power Supply Cable Processor Module with Cable Logic Probe Connector Device Adapter Figure.: MPLAB-ICE Emulator System No more code, compile, simulate, burn, reset, crash, erase, The emulator pod connects to the PC through a parallel port using the code, compile, simulate, burn, reset, crash, erase,... cycle! provided cable. It contains the hardware necessary to perform the common Slideem ulator functions, such as trace, break, and emulate. The processor module inserts into a slot in the front of the emulator pod. It

Outlines. PIC Programming in C and Assembly. Krerk Piromsopa, Ph.D. Department of Computer Engineering Chulalongkorn University

Outlines. PIC Programming in C and Assembly. Krerk Piromsopa, Ph.D. Department of Computer Engineering Chulalongkorn University PIC ming in C and Assembly Outlines Microprocessor vs. MicroController PIC in depth PIC ming Assembly ming Krerk Piromsopa, Ph.D. Department of Computer Engineering Chulalongkorn University Embedded C