Short Course On Phase-Locked Loops and Their Applications Day 3, PM Lecture. Behavioral Simulation Exercises

Transcription

1 Short Course On Phase-Locked Loops and Their Applications Day 3, PM Lecture Behavioral Simulation Exercises Michael H Perrott August 13, 2008 Copyright 2008 by Michael H. Perrott All rights reserved.

2 A Modern Analog Custom IC A 2.5 Gb/s CDR for high speed links - Analog amplification and phase sensing - Digital filtering and calibration - RF clock generation (2.5 GHz) How do we design such chips? 2

3 Simplified View of a Top Down, Mixed-Signal Design Flow System Design Architecture High Level Investigation & Analysis Schematic Creation Circuit Design Analog Circuit Design Digital Creation Place & Route Extracted Layout Creation PVT Corners Monte Carlo Circuit Verification Analog Circuit Verification Digital Digital Test Vectors Timing Checks System Verification Circ. & Arch. System Level Test Vectors 3

4 The Many Simulation Tools Involved Popular Tools System Design Architecture Matlab/Simulink ADS Circuit Design Analog Circuit Design Digital SPICE Verilog/VHDL Circuit Verification Analog Circuit Verification Digital Verilog AMS AMS Designer System Verification Circ. & Arch.???????? 4

5 Goal: Create a Universal Simulator System Designer Analog Designer Digital Designer Managing Kernel SPICE Matlab Verilog VHDL The challenges of developing the Managing Kernel - Difficult to match up simulator signals at their boundaries without overly complicating the life of the user - Difficult to maintain fast simulation speed - Difficult to retrain designers on a new tool with a new flow 5

6 A Different Approach Look for commonality among simulators to allow universal simulation models to be used - C++ provides one such hook Allow designers to use their tool of choice while sharing universal simulation models SPICE Matlab Verilog VHDL C/C++ PLI Calls (Verilog AMS & AMS Designer) C/C++ Mex functions C/C++ PLI Calls Key idea: bootstrap into existing simulators 6

7 The VppSim Simulator Greatly Simplifies This Process Cadence Schematic Entry C++ primitive library Simulation parameter file Graphically driven generation of simulator blocks based on a C++ primitive library Automatic wrapper generation Verilog PLI Calls Verilog PLI Mex & Gen. Function AMS Designer Matlab NCVerilog Analog Designer System Designer Digital Designer 7

8 C++ Can Also Be Directly Simulated Cadence Schematic Entry C++ primitive library Simulation parameter file Automatic C++ system generation Automatic wrapper generation CppSim Advantage: - Very fast! Verilog PLI Calls Verilog PLI Mex & Gen. Function AMS Designer Matlab NCVerilog Analog Designer System Designer Digital Designer 8

9 CppSim Compiler Simulation File Time step value Number of sim steps Probing of signals C++ Simulation Program SPICE Netlist Topology of system - Generated by Cadence or Sue2 9

10 VppSim Compiler (for NCVerilog) Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object Simulation File Time step value Number of sim steps Probing of signals Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object Native Verilog Modules ASCII file descriptions Verilog Simulation Program Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object SPICE Netlist Topology of system - Generated by Cadence All CppSim modules supported (including vector signals) Same timing approach for module execution as CppSim 10

11 VppSim Modules for AMS Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object AMS Simulation Program Verilog Wrapper for Module Verilog PLI function calls Embedded C++ Class Object Not all CppSim modules are supported (i.e., no vector signals) Different timing approach for module execution 11

12 Example with Double Signals CppSim module module: leadlagfilter parameters: double fz, double fp, double gain inputs: double in outputs: double out static_variables: classes: Filter filt("1+1/(2*pi*fz)s", "C3*s + C3/(2*pi*fp)*s^2", "C3,fz,fp,Ts",1/gain,fz,fp,Ts); init: code: filt.inp(in); out = filt.out; ////// Auto-generated from CppSim module ////// module leadlagfilter(in, out); parameter fz = e+00; parameter fp = e+00; parameter gain = e+00; input in; output out; wreal in; real in_rv; wreal out; real out_rv; VppSim module assign out = out_rv; initial begin assign in_rv = in; end always begin #1 $leadlagfilter_cpp(in_rv,out_rv,fz,fp,gain); end endmodule 12

13 The Issue of Timing/Ordering (1) Best Execution Order Execution Order A B C A E B C D E Delay D (2) Impact of Alternate Ordering Arrangement Execution Order A B Delay C A E C B D E Delay D Ordering influences delays CppSim blocks are ordered automatically or by user 13

14 Cadence Interface Choose between CppSim, VppSim (for NCVerilog), and AMS with VppSim modules CppSim and VppSim run in above window or in Matlab 14

15 Windows Version of CppSim Will be used in class today Available for free download at Initial part of this session: fractional-n example Remaining part of this session: example of your choice 15

16 Windows Interface 16