Connecting MATLAB & Simulink with your SystemVerilog Workflow for Functional Verification

Transcription

1 Connecting MATLAB & Simulink with your SystemVerilog Workflow for Functional Verification Corey Mathis Industry Marketing Manager Communications, Electronics, and Semiconductors MathWorks 2014 MathWorks, Inc. 1

2 Who is MathWorks? 2

3 System Design & Simulation in Simulink Unique advantages Model continuous-time and discrete-time components together Express analog filters as Laplace transforms or RLC circuits Variable step ODE solvers Feedback control loops, VCOs, PLLs 3

4 ASIC/SoC-LEVEL TEST & VERIFICATION ASIC/SoC Design Flow Model-Based Design Integration RESEARCH REQUIREMENTS MODEL GENERATION SystemC Digital Models SystemVerilog ALGORITHM DESIGN Environment Models Analog Models Timing and Control Logic Algorithms ALGORITHM IMPLEMENTATION C/C++ HDL MCU DSP FPGA ASIC RF Models RF Analog Transistor ALGORITHM TEST & VERIFICATION ALGORITHM INTEGRATION ASIC/SoC-LEVEL INTEGRATION 4

5 Design Gap How to bridge MathWorks tools and EDA tools?? How do I reuse AMS models from Simulink in an EDA environment? How can I reuse my testbench for digital ASIC verfication? 5

6 Co-simulation with Simulink Verify the detailed level design: within the context of a full system simulation using the visualization and analysis capabilities of Simulink and MATLAB testing each module independently of other modules 6

7 Using Co-simulation for Model Elaboration Ideal behavioral model Cosimulation Refined model 7

8 Algorithm System Verilog DPI-C Component Generation Reuse of models in SystemVerilog Testbench Data Source Component Model Develop System components (IP and test benches) in Simulink and MATLAB Model, Simulate, and Verify Component Analysis Model Algorithmic System-level Testbench Environment Model Export Components as C code with SystemVerilog wrappers Integrate DPI-C components in Virtuoso and Incisive DPI-C DPI-C DPI-C DPI-C SystemVerilog Testbench Environment Verify Verification of the complete system design! Embedded Coder HDL Verifier 8

9 Using C Code Generation and the DPI-C Interface 1. Generate C code from your Simulink model 2. Automatically wrap the C code using the DPI-C interface 3. Import, build and simulate an equivalent behavioral SystemVerilog model in your IC design tool 2. SystemVerilog wrapper Simulink 1. C Code 3. Cadence 9

10 Benefits of C Code Generation and DPI-C Export Fast simulation using the native SystemVerilog API IC design tool independent Customizable approach supported by MathWorks Leverages mature C code generation technology Most suitable for testbench generation and IC verification Support discrete and continuous time signals Simulink Cadence 10

11 Some Details 11

12 Mixed-Signal ADC Model Sine Wave Signal Source First Order Sigma Delta Analog Low Pass Filter Digital Decimator Filter 12

13 Export of Mixed-Signal Models Continuous time signals Discrete time solver 13

14 From Variable to Fixed Time Step Solver Chose a fixed sample time that it is small enough to give correct results Tradeoff accuracy and simulation time Large time step Small time step 14

15 Clocks in SystemVerilog Determine the Scheduling of the Execution Simulink handles multi-rate systems automatically Simulink supports model generation for hierarchical subsystems or individual components Need to define multi-rate clocks to schedule the SystemVerilog execution when different rate components are generated Fast Rate Slow Rate Fast Clock Slow Clock 15

16 Model Analog Circuits with Simscape Model analog electronics with Simscape Generate a SystemVerilog component for simulation in the IC Design Tools 16

17 Algorithm Digital Workflow Data Source Analysis Algorithmic System-level Testbench Component Model Component Model Environment Model HDL Coder Used to generate synthesible RTL HDL for design models SystemVerilog DPI-C Reuse of golden testbench: Signal sources Support for Enviorment and channel models Measurement block and algorithms MATLAB Simulink Stateflow DPI-C RTL HDL (VHDL, Verilog) RTL HDL (VHDL, Verilog) SystemVerilog Testbench Environment DPI-C HDL Coder 17

18 Digital Workflow Example MathWorks can export HDL code for pure digital models Testbenches need to be exported to Cadence via DPI-C 18

19 Digital Workflow Example 1. Generate synthesizable Verilog or VHDL for design components 19

20 Digital Workflow Example 2. Generate C code with SystemVerilog wrappers for testbench components 20

21 Digital Workflow Example 3. Import HDL and SystemVerilog into Cadence for simulation/verification 21

22 Certified by STARC 22

23 SystemVerilog Workflow Summary MATLAB & Simulink provide a diverse environment for early stage design exploration Co-simulation provides a means of elaborating on initial behavioral models to match detailed level designs The DPI-C link for SystemVerilog provides a robust way of exporting behavioral models from MathWorks tools into Cadence for the purpose of functional verification 23

24 Q / A 24