Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN)
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1 Computer Organization CS Exam 2 Review Dr. William H. Robinson October 11, Topics Education is a progressive discovery of our own ignorance. Will Durant ( ) Review, review, review Ask questions if you have them RPN and IJVM instructions Digital logic level Microarchitecture level Today s 50-minute review is NOT comprehensive 1 2 Infix Notation The tradition of mathematics c = a + b Requires algebraic precedence structure Parentheses Multiplication/division Addition/subtraction Does not map well to HW Reverse Polish Notation (RPN) Method to write arithmetic expressions Avoids the use of brackets to define priorities for evaluation of operators Devised by Jan Lucasiewicz Polish philosopher and mathematician In his notation, the operators preceded their arguments The reverse places operators after arguments (postfix) For more info
2 Advantages of RPN Express formulas without parentheses Evaluate formulas on stack architectures Eliminates arbitrary precedence Structured Computer Organization Digital logic builds microarchitecture Microarchitecture implements the ISA ISA is in machine language Assembly language allows us to use ISA 5 6 IJVM Instruction Set (page 222) Java Bytecode (page 226) Subset of Java Virtual Machine (JVM) Only integer instructions Assume: i is varnum 1 j is varnum 2 k is varnum 3 7 8
3 Structured Computer Organization Boolean Algebra Defined Provides the operations and the rules for working with the binary set {0,1} Used in the study of electronic switches 0 represents off, low, or false 1 represents on, high, or true Boolean functions are represented using variables and operators 9 10 Boolean Product - AND Function Boolean Sum - OR Function Logic operation A B F Logic operation A B F Output is true when both inputs are true Equivalent to multiplication in base 2 F = A B Truth table for AND function A B F Output is true when either input is true or when both inputs are true Avoid confusion with the addition operation in arithmetic F = A + B Truth table for OR function A B F
4 Boolean Exclusive Sum - XOR Function Complementary Functions Logic operation A B F NOT Complements a single input Output is true when either input is true but not both Corresponds to addition in base 2 F = A B Truth table for XOR function A B F NAND Complement of AND NOR Complement of OR XNOR Complement of XOR Multiplexers/Demultiplexers Decoders/Encoders MUX 2 n data inputs, 1 data output, n control signals Binary code on select determines which input is routed to output DEMUX 1 data input, 2 n data outputs, n control signals Binary code on select routes a single input signal to one of 2 n outputs Decoder Takes an n-bit number as input Selects (sets to 1 ) exactly 1 of 2 n outputs Encoder Input is a group of parallel bits Output is the binary code assigned to asserted input 15 16
5 Comparators and Shifters Comparator Determine if two input words are equal Based upon XOR gate Shifter Arithmetic shift maintains the sign 1-bit arithmetic shift left multiplies by 2 1-bit arithmetic shift right divides by 2 Logical shift fills empty bits with 0 Shift left logical 8 from the Mic-1 Half adder Inputs A, B Outputs C out, Sum Full adder Inputs A, B, C in Outputs C out, Sum Ripple-carry adder Carry-select adder Adders Logic Unit with output enable ALU Bit Slice Output for all ALU functions Control Signals for ALU Functions 2:4 Decoder for enable signals Full Adder with output enable 19 20
6 Block Diagram of Microarchitecture (Mic-1) Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture) Control Section Part of CPU containing the H/W necessary to direct the datapath 21 Fetch-Decode-Execute 1. Fetch the next instruction from memory into the instruction register. 2. Change the program counter to point to the following instruction. 3. Determine the type of instruction just fetched. 4. If the instruction uses a word in memory, determine where it is. 5. Fetch the word, if needed, into a CPU register. 6. Execute the instruction. 7. Start over and begin executing the following instruction. 22 Datapath Registers Memory Address Register Memory Data Register Program Counter Memory Buffer Register Stack Pointer Local Variable pointer Constant Pool Pointer Top Of Stack OPC Holding register Hold either an address or a data value 23 Memory Operation Memory Address Register Memory Data Register Program Counter Memory Buffer Register Registers driven by control signals WRITE, READ, FETCH Two ways to access memory 32-bit port (word addressable) (MAR, MDR) 8-bit read-only port (byte addressable) (PC, MBR) Actual memory is byte oriented 24
7 Parts of IJVM Memory Datapath Timing Has a finite propagation time Signals travel along wires, through transistors, etc. CPP, LV, and SP registers are pointers to words PC contains a byte address Implicit clock subcycles Set up control signals to drive datapath Register loaded onto B bus ALU and shifter operate Result propagates along C bus to registers Timing Diagram for One Datapath Cycle Microinstruction Format Use two additional sets of signals 9 for address of next microinstruction 3 to determine how next microinstruction is selected (JAM) 27 Total of 36 control signals (bits) 28
8 Control Store (ROM) Block Diagram of Microarchitecture (Mic-1) Memory that holds the microprogram Contains 512 words, each a 36-bit microinstruction Each microinstruction specified its successor Not executed in order stored in control store Accessing the microprogram MicroProgram Counter similar to memory address register MicroInstruction Register similar to memory data register 29 Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture) Control Section Part of CPU containing the H/W necessary to direct the datapath 30 Summary Computer Organization is still a GREAT class Dr. Robinson is still a GREAT professor Questions focus on material since Exam 1 Don t forget concepts from Chapters 1 & 2 Main ideas Digital logic structures Microarchitecture level components IJVM 31
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