Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN)

Size: px
Start display at page:

Download "Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN)"

Transcription

1 Computer Organization CS Exam 2 Review Dr. William H. Robinson October 11, Topics Education is a progressive discovery of our own ignorance. Will Durant ( ) Review, review, review Ask questions if you have them RPN and IJVM instructions Digital logic level Microarchitecture level Today s 50-minute review is NOT comprehensive 1 2 Infix Notation The tradition of mathematics c = a + b Requires algebraic precedence structure Parentheses Multiplication/division Addition/subtraction Does not map well to HW Reverse Polish Notation (RPN) Method to write arithmetic expressions Avoids the use of brackets to define priorities for evaluation of operators Devised by Jan Lucasiewicz Polish philosopher and mathematician In his notation, the operators preceded their arguments The reverse places operators after arguments (postfix) For more info

2 Advantages of RPN Express formulas without parentheses Evaluate formulas on stack architectures Eliminates arbitrary precedence Structured Computer Organization Digital logic builds microarchitecture Microarchitecture implements the ISA ISA is in machine language Assembly language allows us to use ISA 5 6 IJVM Instruction Set (page 222) Java Bytecode (page 226) Subset of Java Virtual Machine (JVM) Only integer instructions Assume: i is varnum 1 j is varnum 2 k is varnum 3 7 8

3 Structured Computer Organization Boolean Algebra Defined Provides the operations and the rules for working with the binary set {0,1} Used in the study of electronic switches 0 represents off, low, or false 1 represents on, high, or true Boolean functions are represented using variables and operators 9 10 Boolean Product - AND Function Boolean Sum - OR Function Logic operation A B F Logic operation A B F Output is true when both inputs are true Equivalent to multiplication in base 2 F = A B Truth table for AND function A B F Output is true when either input is true or when both inputs are true Avoid confusion with the addition operation in arithmetic F = A + B Truth table for OR function A B F

4 Boolean Exclusive Sum - XOR Function Complementary Functions Logic operation A B F NOT Complements a single input Output is true when either input is true but not both Corresponds to addition in base 2 F = A B Truth table for XOR function A B F NAND Complement of AND NOR Complement of OR XNOR Complement of XOR Multiplexers/Demultiplexers Decoders/Encoders MUX 2 n data inputs, 1 data output, n control signals Binary code on select determines which input is routed to output DEMUX 1 data input, 2 n data outputs, n control signals Binary code on select routes a single input signal to one of 2 n outputs Decoder Takes an n-bit number as input Selects (sets to 1 ) exactly 1 of 2 n outputs Encoder Input is a group of parallel bits Output is the binary code assigned to asserted input 15 16

5 Comparators and Shifters Comparator Determine if two input words are equal Based upon XOR gate Shifter Arithmetic shift maintains the sign 1-bit arithmetic shift left multiplies by 2 1-bit arithmetic shift right divides by 2 Logical shift fills empty bits with 0 Shift left logical 8 from the Mic-1 Half adder Inputs A, B Outputs C out, Sum Full adder Inputs A, B, C in Outputs C out, Sum Ripple-carry adder Carry-select adder Adders Logic Unit with output enable ALU Bit Slice Output for all ALU functions Control Signals for ALU Functions 2:4 Decoder for enable signals Full Adder with output enable 19 20

6 Block Diagram of Microarchitecture (Mic-1) Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture) Control Section Part of CPU containing the H/W necessary to direct the datapath 21 Fetch-Decode-Execute 1. Fetch the next instruction from memory into the instruction register. 2. Change the program counter to point to the following instruction. 3. Determine the type of instruction just fetched. 4. If the instruction uses a word in memory, determine where it is. 5. Fetch the word, if needed, into a CPU register. 6. Execute the instruction. 7. Start over and begin executing the following instruction. 22 Datapath Registers Memory Address Register Memory Data Register Program Counter Memory Buffer Register Stack Pointer Local Variable pointer Constant Pool Pointer Top Of Stack OPC Holding register Hold either an address or a data value 23 Memory Operation Memory Address Register Memory Data Register Program Counter Memory Buffer Register Registers driven by control signals WRITE, READ, FETCH Two ways to access memory 32-bit port (word addressable) (MAR, MDR) 8-bit read-only port (byte addressable) (PC, MBR) Actual memory is byte oriented 24

7 Parts of IJVM Memory Datapath Timing Has a finite propagation time Signals travel along wires, through transistors, etc. CPP, LV, and SP registers are pointers to words PC contains a byte address Implicit clock subcycles Set up control signals to drive datapath Register loaded onto B bus ALU and shifter operate Result propagates along C bus to registers Timing Diagram for One Datapath Cycle Microinstruction Format Use two additional sets of signals 9 for address of next microinstruction 3 to determine how next microinstruction is selected (JAM) 27 Total of 36 control signals (bits) 28

8 Control Store (ROM) Block Diagram of Microarchitecture (Mic-1) Memory that holds the microprogram Contains 512 words, each a 36-bit microinstruction Each microinstruction specified its successor Not executed in order stored in control store Accessing the microprogram MicroProgram Counter similar to memory address register MicroInstruction Register similar to memory data register 29 Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture) Control Section Part of CPU containing the H/W necessary to direct the datapath 30 Summary Computer Organization is still a GREAT class Dr. Robinson is still a GREAT professor Questions focus on material since Exam 1 Don t forget concepts from Chapters 1 & 2 Main ideas Digital logic structures Microarchitecture level components IJVM 31

Topics. Block Diagram of Mic-1 Microarchitecture. Review Sheet. Microarchitecture IJVM ISA

Topics. Block Diagram of Mic-1 Microarchitecture. Review Sheet. Microarchitecture IJVM ISA Topics Review Sheet Microarchitecture IJVM ISA 1 Block Diagram of Mic-1 Microarchitecture Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture)

More information

1DT157 Digitalteknik och datorarkitekt. Digital technology and computer architecture, 5p

1DT157 Digitalteknik och datorarkitekt. Digital technology and computer architecture, 5p 1DT157 Digitalteknik och datorarkitekt Digital technology and computer architecture, 5p Homework #1 Tanenbaum Chapter 3 Problems 6,7,11,19,23 Submit electronically to the TAs: Binary Numbers Appendix A

More information

The Microarchitecture Level

The Microarchitecture Level The Microarchitecture Level Chapter 4 The Data Path (1) The data path of the example microarchitecture used in this chapter. The Data Path (2) Useful combinations of ALU signals and the function performed.

More information

Topics. Computer Organization CS Mic-1 Microinstructions. Control Store (ROM) Programming Teams

Topics. Computer Organization CS Mic-1 Microinstructions. Control Store (ROM) Programming Teams Computer Organization CS -0 Mic- Microinstructions Dr. William H. Robinson November, 004 http://eecs.vanderbilt.edu/courses/cs/ Topics There is no one giant step that does it. It's a lot of little steps.

More information

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit

Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit Lecture1: introduction Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit 1 1. History overview Computer systems have conventionally

More information

Computer Architecture Programming the Basic Computer

Computer Architecture Programming the Basic Computer 4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.

More information

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2 Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2 C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats

More information

Digital System Design Using Verilog. - Processing Unit Design

Digital System Design Using Verilog. - Processing Unit Design Digital System Design Using Verilog - Processing Unit Design 1.1 CPU BASICS A typical CPU has three major components: (1) Register set, (2) Arithmetic logic unit (ALU), and (3) Control unit (CU) The register

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean

More information

Topics. Structured Computer Organization. Assembly language. IJVM instruction set. Mic-1 simulator programming

Topics. Structured Computer Organization. Assembly language. IJVM instruction set. Mic-1 simulator programming Topics Assembly language IJVM instruction set Mic-1 simulator programming http://www.ontko.com/mic1/ Available in 2 nd floor PC lab S/W found in directory C:\mic1 1 Structured Computer Organization 2 Block

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

Chapter 4. Micro-architecture Level PART I

Chapter 4. Micro-architecture Level PART I Chapter 4 Micro-architecture Level PART I The Data Path Memory Operation Microinstructions Microinstruction Control: The Mic-1 An Example ISA: IJVM Microinstructions and Notation Implementation of IJVM

More information

Register Transfer and Micro-operations

Register Transfer and Micro-operations Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

Chapter 05: Basic Processing Units Control Unit Design. Lesson 15: Microinstructions

Chapter 05: Basic Processing Units Control Unit Design. Lesson 15: Microinstructions Chapter 05: Basic Processing Units Control Unit Design Lesson 15: Microinstructions 1 Objective Understand that an instruction implement by sequences of control signals generated by microinstructions in

More information

Von Neumann Architecture

Von Neumann Architecture Von Neumann Architecture Assist lecturer Donya A. Khalid Lecture 2 2/29/27 Computer Organization Introduction In 945, just after the World War, Jon Von Neumann proposed to build a more flexible computer.

More information

COSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1

COSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements PS8 Due today PS9 Due July 22 Sound Lab tonight bring machines and headphones! Binary Search Today Review of binary floating point notation

More information

Combinational Circuits

Combinational Circuits Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

More information

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in

More information

ECEN 468 Advanced Logic Design

ECEN 468 Advanced Logic Design ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26 Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean

More information

UNIT-II. Part-2: CENTRAL PROCESSING UNIT

UNIT-II. Part-2: CENTRAL PROCESSING UNIT Page1 UNIT-II Part-2: CENTRAL PROCESSING UNIT Stack Organization Instruction Formats Addressing Modes Data Transfer And Manipulation Program Control Reduced Instruction Set Computer (RISC) Introduction:

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 May 10, 2010 Final Exam Name: ID number: This is

More information

REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

More information

COMPUTER ARCHITECTURE AND PARALEL PROCESSING STUDY NOTES

COMPUTER ARCHITECTURE AND PARALEL PROCESSING STUDY NOTES COMPUTER ARCHITECTURE AND PARALEL PROCESSING STUDY NOTES UNIT 1 INTRODUCTION Central Processing unit (CPU): Alternately referred to as a processor, central processor, or microprocessor, the CPU is the

More information

4. MICROPROGRAMMED COMPUTERS

4. MICROPROGRAMMED COMPUTERS Structure of Computer Systems Laboratory No. 4 1 4. MICROPROGRAMMED COMPUTERS This laboratory work presents the principle of microprogrammed computers and an example of microprogrammed architecture, in

More information

Lecture #21 March 31, 2004 Introduction to Gates and Circuits

Lecture #21 March 31, 2004 Introduction to Gates and Circuits Lecture #21 March 31, 2004 Introduction to Gates and Circuits To this point we have looked at computers strictly from the perspective of assembly language programming. While it is possible to go a great

More information

CSE/EE 322: Computer Architecture II Spring The JAM machine Series

CSE/EE 322: Computer Architecture II Spring The JAM machine Series CSE/EE 322: Computer Architecture II Spring 2009 The JAM machine Series Peter M. Kogge CSE 322 jam-overview.1 Kogge, ND, 16/09 The Original JAM-8 Roots in JVM: Java Virtual Machine Target of most Java

More information

CS 2630 Computer Organization. Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa

CS 2630 Computer Organization. Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa CS 2630 Computer Organization Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa Where we are going Compiler Instruction set architecture (e.g., MIPS) translating source

More information

CPU Design John D. Carpinelli, All Rights Reserved 1

CPU Design John D. Carpinelli, All Rights Reserved 1 CPU Design 1997 John D. Carpinelli, All Rights Reserved 1 Outline Register organization ALU design Stacks Instruction formats and types Addressing modes 1997 John D. Carpinelli, All Rights Reserved 2 We

More information

Prefix/Infix/Postfix Notation

Prefix/Infix/Postfix Notation Prefix/Infix/Postfix Notation One commonly writes arithmetic expressions, such as 3 + 4 * (5-2) in infix notation which means that the operator is placed in between the two operands. In this example, the

More information

PART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers.

PART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers. Set No. 1 IV B.Tech I Semester Supplementary Examinations, March - 2017 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks:

More information

CHAPTER 8: Central Processing Unit (CPU)

CHAPTER 8: Central Processing Unit (CPU) CS 224: Computer Organization S.KHABET CHAPTER 8: Central Processing Unit (CPU) Outline Introduction General Register Organization Stack Organization Instruction Formats Addressing Modes 1 Major Components

More information

Computer Organisation CS303

Computer Organisation CS303 Computer Organisation CS303 Module Period Assignments 1 Day 1 to Day 6 1. Write a program to evaluate the arithmetic statement: X=(A-B + C * (D * E-F))/G + H*K a. Using a general register computer with

More information

COMPUTER ORGANIZATION AND ARCHITECTURE

COMPUTER ORGANIZATION AND ARCHITECTURE Page 1 1. Which register store the address of next instruction to be executed? A) PC B) AC C) SP D) NONE 2. How many bits are required to address the 128 words of memory? A) 7 B) 8 C) 9 D) NONE 3. is the

More information

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

More information

CS Computer Architecture

CS Computer Architecture CS 35101 Computer Architecture Section 600 Dr. Angela Guercio Fall 2010 An Example Implementation In principle, we could describe the control store in binary, 36 bits per word. We will use a simple symbolic

More information

Many ways to build logic out of MOSFETs

Many ways to build logic out of MOSFETs Many ways to build logic out of MOSFETs pass transistor logic (most similar to the first switch logic we saw) static CMOS logic (what we saw last time) dynamic CMOS logic Clock=0 precharges X through the

More information

Dec Hex Bin ORG ; ZERO. Introduction To Computing

Dec Hex Bin ORG ; ZERO. Introduction To Computing Dec Hex Bin 0 0 00000000 ORG ; ZERO Introduction To Computing OBJECTIVES this chapter enables the student to: Convert any number from base 2, base 10, or base 16 to any of the other two bases. Add and

More information

CHAPTER 4: Register Transfer Language and Microoperations

CHAPTER 4: Register Transfer Language and Microoperations CS 224: Computer Organization S.KHABET CHAPTER 4: Register Transfer Language and Microoperations Outline Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations

More information

REGISTER TRANSFER AND MICROOPERATIONS

REGISTER TRANSFER AND MICROOPERATIONS 1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

DIGITAL ELECTRONICS. P41l 3 HOURS

DIGITAL ELECTRONICS. P41l 3 HOURS UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

More information

PESIT Bangalore South Campus

PESIT Bangalore South Campus INTERNAL ASSESSMENT TEST III Date : 21/11/2017 Max Marks : 40 Subject & Code : Computer Organization (15CS34) Semester : III (A & B) Name of the faculty: Mrs. Sharmila Banu Time : 11.30 am 1.00 pm Answer

More information

Parallel logic circuits

Parallel logic circuits Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design

More information

Computer Architecture

Computer Architecture Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two

More information

1. Draw general diagram of computer showing different logical components (3)

1. Draw general diagram of computer showing different logical components (3) Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the

More information

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3. Boolean Algebra and Digital Logic Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

More information

Topics Power tends to corrupt; absolute power corrupts absolutely. Computer Organization CS Data Representation

Topics Power tends to corrupt; absolute power corrupts absolutely. Computer Organization CS Data Representation Computer Organization CS 231-01 Data Representation Dr. William H. Robinson November 12, 2004 Topics Power tends to corrupt; absolute power corrupts absolutely. Lord Acton British historian, late 19 th

More information

1. Fundamental Concepts

1. Fundamental Concepts 1. Fundamental Concepts 1.1 What is a computer? A computer is a data processing machine which is operated automatically under the control of a list of instructions (called a program) stored in its main

More information

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic

More information

Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators. JAVA Standard Edition

Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators. JAVA Standard Edition Basic operators, Arithmetic, Relational, Bitwise, Logical, Assignment, Conditional operators JAVA Standard Edition Java - Basic Operators Java provides a rich set of operators to manipulate variables.

More information

Reference Sheet for C112 Hardware

Reference Sheet for C112 Hardware Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0

More information

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015 Advanced Parallel Architecture Lesson 3 Annalisa Massini - 2014/2015 Von Neumann Architecture 2 Summary of the traditional computer architecture: Von Neumann architecture http://williamstallings.com/coa/coa7e.html

More information

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final

More information

Chapter 16. Control Unit Operation. Yonsei University

Chapter 16. Control Unit Operation. Yonsei University Chapter 16 Control Unit Operation Contents Micro-Operation Control of the Processor Hardwired Implementation 16-2 Micro-Operations Micro-Operations Micro refers to the fact that each step is very simple

More information

ASSEMBLY LANGUAGE MACHINE ORGANIZATION

ASSEMBLY LANGUAGE MACHINE ORGANIZATION ASSEMBLY LANGUAGE MACHINE ORGANIZATION CHAPTER 3 1 Sub-topics The topic will cover: Microprocessor architecture CPU processing methods Pipelining Superscalar RISC Multiprocessing Instruction Cycle Instruction

More information

Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems.

Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems. REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

William Stallings Computer Organization and Architecture

William Stallings Computer Organization and Architecture William Stallings Computer Organization and Architecture Chapter 16 Control Unit Operations Rev. 3.2 (2009-10) by Enrico Nardelli 16-1 Execution of the Instruction Cycle It has many elementary phases,

More information

REGISTER TRANSFER AND MICROOPERATIONS

REGISTER TRANSFER AND MICROOPERATIONS REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals

More information

2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]

2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7] Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two n-digit unsigned numbers.

More information

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

More information

History of Computing. Ahmed Sallam 11/28/2014 1

History of Computing. Ahmed Sallam 11/28/2014 1 History of Computing Ahmed Sallam 11/28/2014 1 Outline Blast from the past Layered Perspective of Computing Why Assembly? Data Representation Base 2, 8, 10, 16 Number systems Boolean operations and algebra

More information

Lecture 21: Combinational Circuits. Integrated Circuits. Integrated Circuits, cont. Integrated Circuits Combinational Circuits

Lecture 21: Combinational Circuits. Integrated Circuits. Integrated Circuits, cont. Integrated Circuits Combinational Circuits Lecture 21: Combinational Circuits Integrated Circuits Combinational Circuits Multiplexer Demultiplexer Decoder Adders ALU Integrated Circuits Circuits use modules that contain multiple gates packaged

More information

COMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA)

COMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA) COMP2121: Microprocessors and Interfacing Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2017 1 Contents Memory models Registers Data types Instructions

More information

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you

More information

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control,

Basic Processing Unit: Some Fundamental Concepts, Execution of a. Complete Instruction, Multiple Bus Organization, Hard-wired Control, UNIT - 7 Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple Bus Organization, Hard-wired Control, Microprogrammed Control Page 178 UNIT - 7 BASIC PROCESSING

More information

Course Syllabus [1/2]

Course Syllabus [1/2] Course Syllabus [1/2] Instructor 逄愛君, acpang@csie.ntu.edu.tw Office Number: 417, Office Hour: 15:00~17:00 (Thursday) Textbook Assembly Language for Intel-Based Computers, Kip R. Irvine, Pearson Education,

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

Assembly Language for Intel-Based Computers, 4 th Edition. Chapter 1: Basic Concepts. Chapter Overview. Welcome to Assembly Language

Assembly Language for Intel-Based Computers, 4 th Edition. Chapter 1: Basic Concepts. Chapter Overview. Welcome to Assembly Language Assembly Language for Intel-Based Computers, 4 th Edition Kip R. Irvine Chapter 1: Basic Concepts Slides prepared by Kip R. Irvine Revision date: 09/15/2002 Chapter corrections (Web) Printing a slide show

More information

Computer Logic II CCE 2010

Computer Logic II CCE 2010 Computer Logic II CCE 2010 Dr. Owen Casha Computer Logic II 1 The Processing Unit Computer Logic II 2 The Processing Unit In its simplest form, a computer has one unit that executes program instructions.

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

More information

Programmable machines

Programmable machines Page 1 of 9 Programmable machines indicates problems that have been selected for discussion in section, time permitting. Problem 1. Consider the following circuit: The heavy lines represent busses, which

More information

Controller Implementation--Part II

Controller Implementation--Part II Controller Implementation--Part II Alternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time-State: Divide and Conquer Jump counters Microprogramming (ROM)

More information

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9

More information

MICROPROGRAMMED CONTROL

MICROPROGRAMMED CONTROL MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed

More information

Basic Arithmetic (adding and subtracting)

Basic Arithmetic (adding and subtracting) Basic Arithmetic (adding and subtracting) Digital logic to show add/subtract Boolean algebra abstraction of physical, analog circuit behavior 1 0 CPU components ALU logic circuits logic gates transistors

More information

09 STACK APPLICATION DATA STRUCTURES AND ALGORITHMS REVERSE POLISH NOTATION

09 STACK APPLICATION DATA STRUCTURES AND ALGORITHMS REVERSE POLISH NOTATION DATA STRUCTURES AND ALGORITHMS 09 STACK APPLICATION REVERSE POLISH NOTATION IMRAN IHSAN ASSISTANT PROFESSOR, AIR UNIVERSITY, ISLAMABAD WWW.IMRANIHSAN.COM LECTURES ADAPTED FROM: DANIEL KANE, NEIL RHODES

More information

COA. Prepared By: Dhaval R. Patel Page 1. Q.1 Define MBR.

COA. Prepared By: Dhaval R. Patel Page 1. Q.1 Define MBR. Q.1 Define MBR. MBR( Memory buffer register) A Memory Buffer Register (MBR) is the register in a computers processor that stores the data being transferred to and from the devices It allowing the processor

More information

Chapter 20 - Microprogrammed Control (9 th edition)

Chapter 20 - Microprogrammed Control (9 th edition) Chapter 20 - Microprogrammed Control (9 th edition) Luis Tarrataca luis.tarrataca@gmail.com CEFET-RJ L. Tarrataca Chapter 20 - Microprogrammed Control 1 / 47 Table of Contents I 1 Motivation 2 Basic Concepts

More information

Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Review Topics. parameter passing, memory model)

Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Review Topics. parameter passing, memory model) Final Exam Review Original slides from Gregory Byrd, North Carolina State University Modified slides by C. Wilcox, S. Rajopadhye Colorado State University Review Topics! Number Representation & Arithmetic!

More information

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write

More information

Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012

Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012 Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012 1 Digital vs Analog Digital signals are binary; analog

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Data Paths and Microprogramming We have spent time looking at the MIPS instruction set architecture and building

More information

MARIE: An Introduction to a Simple Computer

MARIE: An Introduction to a Simple Computer MARIE: An Introduction to a Simple Computer 4.2 CPU Basics The computer s CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit.

More information

CS 24: INTRODUCTION TO. Spring 2015 Lecture 2 COMPUTING SYSTEMS

CS 24: INTRODUCTION TO. Spring 2015 Lecture 2 COMPUTING SYSTEMS CS 24: INTRODUCTION TO Spring 2015 Lecture 2 COMPUTING SYSTEMS LAST TIME! Began exploring the concepts behind a simple programmable computer! Construct the computer using Boolean values (a.k.a. bits )

More information

JAVA OPERATORS GENERAL

JAVA OPERATORS GENERAL JAVA OPERATORS GENERAL Java provides a rich set of operators to manipulate variables. We can divide all the Java operators into the following groups: Arithmetic Operators Relational Operators Bitwise Operators

More information

Computer Systems. Binary Representation. Binary Representation. Logical Computation: Boolean Algebra

Computer Systems. Binary Representation. Binary Representation. Logical Computation: Boolean Algebra Binary Representation Computer Systems Information is represented as a sequence of binary digits: Bits What the actual bits represent depends on the context: Seminar 3 Numerical value (integer, floating

More information

END-TERM EXAMINATION

END-TERM EXAMINATION (Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

More information

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015 Advanced Parallel Architecture Lesson 3 Annalisa Massini - Von Neumann Architecture 2 Two lessons Summary of the traditional computer architecture Von Neumann architecture http://williamstallings.com/coa/coa7e.html

More information

STRUCTURE OF DESKTOP COMPUTERS

STRUCTURE OF DESKTOP COMPUTERS Page no: 1 UNIT 1 STRUCTURE OF DESKTOP COMPUTERS The desktop computers are the computers which are usually found on a home or office desk. They consist of processing unit, storage unit, visual display

More information

CS 2461: Computer Architecture I

CS 2461: Computer Architecture I Computer Architecture is... CS 2461: Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: www.seas.gwu.edu/~bhagiweb/cs2461/ Instruction Set Architecture Organization

More information

Levels in Processor Design

Levels in Processor Design Levels in Processor Design Circuit design Keywords: transistors, wires etc.results in gates, flip-flops etc. Logical design Putting gates (AND, NAND, ) and flip-flops together to build basic blocks such

More information

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

More information

CS 261 Fall Mike Lam, Professor. Combinational Circuits

CS 261 Fall Mike Lam, Professor. Combinational Circuits CS 261 Fall 2017 Mike Lam, Professor Combinational Circuits The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric

More information

Operators. Java operators are classified into three categories:

Operators. Java operators are classified into three categories: Operators Operators are symbols that perform arithmetic and logical operations on operands and provide a meaningful result. Operands are data values (variables or constants) which are involved in operations.

More information

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics Chapter 4 Objectives Learn the components common to every modern computer system. Chapter 4 MARIE: An Introduction to a Simple Computer Be able to explain how each component contributes to program execution.

More information