CS 31: Intro to Systems Caching. Martin Gagne Swarthmore College March 23, 2017

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1 CS 1: Intro to Systems Caching Martin Gagne Swarthmore College March 2, 2017

2 Recall A cache is a smaller, faster memory, that holds a subset of a larger (slower) memory We take advantage of locality to keep data in cache as often as we can! When accessing memory, we check cache to see if it has the data we re looking for.

3 Why cache misses occur Compulsory (cold-start) miss: First time we use data, load it into cache. Capacity miss: Cache is too small to store all the data we re using. Conflict miss: To bring in new data to the cache, we evicted other data that we re still using.

4 A. In exactly one place. ( Direct-mapped ) Every location in memory is directly mapped to one place in the cache. Easy to find data. B. In a few places. ( Set associative ) A memory location can be mapped to (2, 4, 8) locations in the cache. Middle ground. C. In most places, but not all. D. Anywhere in the cache. ( Fully associative ) No restrictions on where memory can be placed in the cache. Fewer conflict misses, more searching.

5 Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Index: Which line (row) should we check? Where could data be? Line V D Tag Data (8 Bytes)

6 Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Index: Which line (row) should we check? Where could data be? 4 Line V D Tag Data (8 Bytes)

7 Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) In parallel, check: Tag: Does the cache hold the data we re looking for, or some other block? Valid bit: If entry is not valid, don t trust garbage in that line (row). Line V D Tag Data (8 Bytes) If tag doesn t match, or line is invalid, it s a miss!

8 Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Byte offset tells us which subset of block to retrieve. Line V D Tag Data (8 Bytes)

9 Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Byte offset tells us which subset of block to retrieve. Line V D Tag Data (8 Bytes)

10 Data Input: Memory Address Tag Index Byte offset Select Byte(s) V D Tag Data = 0: miss 1: hit

11 Direct-Mapped Example Let s say we access memory at address: Step 1: Partition address into tag, index, offset Line V D Tag Data (16 Bytes)

12 Direct-Mapped Example Let s say we access memory at address: Step 1: Partition address into tag, index, offset Line V D Tag Data (16 Bytes)

13 Direct-Mapped Example Let s say we access memory at address: Line V D Tag Data (16 Bytes) Step 2: Use index to find line (row) >

14 Direct-Mapped Example Let s say we access memory at address: Line V D Tag Data (16 Bytes) Step 2: Use index to find line (row) >

15 Direct-Mapped Example Let s say we access memory at address: Line V D Tag Data (16 Bytes) 0 1 Use tag to store high-order bits. Let s us determine which data is here! (many addresses map here) 2 Note: ANY address with 0011 () as the middle four index bits will map to this cache line. e.g So, which data is here? Data from address OR ?

16 Direct-Mapped Example Let s say we access memory at address: Line V D Tag Data (16 Bytes) 0 1 Step : Check the tag Is it (hit)? Something else (miss)? (Must also ensure valid)

17 Eviction: Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Find line: Tag doesn t match, bring in from memory. If dirty, write back first! Line V D Tag Data (8 Bytes)

18 Eviction: Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Send address to read main memory. Line V D Tag Data (8 Bytes) Main Memory

19 Eviction: Direct-Mapped Address division: Tag (19 bits) Index (10 bits) Byte offset ( bits) Send address to read main memory. Main Memory Line V D Tag Data (8 Bytes) Copy data from memory. Update tag.

20 Dirty Bit Indicates when a block in the cache may be inconsistent with corresponding block in RAM When evicted, the block is written back to memory if the dirty bit is 1 (write-back cache only)

21 Real CPUs Source: Intel 64 and IA-2 Architectures Optimization Reference Manual June 2016

22 Dirty Bit Indicates when a block in the cache may be inconsistent with corresponding block in RAM Set to zero when the block is read from RAM and brought to the cache (when there is a miss) A write will always set the dirty bit to 1 A read never modifies the dirty bit When evicted, the block is written back to memory if the dirty bit is 1 (write-back cache only)

23 Associativity Problem: suppose we re only using a small amount of data (e.g., 8 bytes, 4-byte block size) Bad luck: (both) blocks map to same cache line Constantly evicting one another Rest of cache is going unused! Associativity: allow a set blocks to be stored at the same index. Goal: reduce conflict misses.

24 The other extreme: fully associative + Any block can go in any cache line. + Reduces cache misses. - Have to check every line for matching address. - Need to store more bits of the address (longer tag). - Eviction decisions are harder.

25 Compromise: set associative Each line can hold N blocks. Addresses are mapped to a line (set), but can go in any of that line s N blocks.

26 Comparison Direct-mapped Tag tells you if you found the correct data. Offset specifies which byte within block. Middle bits (index) tell you which 1 line to check. N-way set associative Tag tells you if you found the correct data. Offset specifies which byte within block. Middle bits (set) tell you which N lines to check. (+) Low complexity, fast. (-) Conflict misses. (+) Fewer conflict misses. (-) More complex, slower, consumes more power.

27 Comparison: 1024 Lines (For the same cache size, in bytes.) Direct-mapped 1024 indices (10 bits) 2-way set associative 512 sets (9 bits) Tag slightly (1 bit) larger. Set # V D Tag Data (8 Bytes) V D Tag Data (8 Bytes)

28 2-Way Set Associative Tag (20 bits) Set (9 bits) Byte offset ( bits) Same capacity as previous example: 1024 rows with 1 entry vs. 512 rows with 2 entries Set # V D Tag Data (8 Bytes) V D Tag Data (8 Bytes)

29 2-Way Set Associative Tag (20 bits) Set (9 bits) Byte offset ( bits) Set # V D Tag Data (8 Bytes) V D Tag Data (8 Bytes) Check all locations in the set, in parallel.

30 2-Way Set Associative Tag (20 bits) Set (9 bits) Byte offset ( bits) Set # V D Tag Data (8 Bytes) V D Tag Data (8 Bytes) Multiplexer Select correct value.

31 4-Way Set Associative Cache Clearly, more complexity here!

32 Eviction Mechanism is the same Overwrite bits in cache line: update tag, valid, data Policy: choose which line in the set to evict Pick a random line in set Choose an invalid line first Choose the least recently used block Has exhibited the least locality, kick it out! Common combo in practice.

33 Least Recently Used (LRU) Intuition: if it hasn t been used in a while, we have no reason to believe it will be used soon. Need extra state to keep track of LRU info. Set # LRU V D Tag Data (8 Bytes) V D Tag Data (8 Bytes)

34 Least Recently Used (LRU) Intuition: if it hasn t been used in a while, we have no reason to believe it will be used soon. Need extra state to keep track of LRU info. For perfect LRU info: 2-way: 1 bit 4-way: 8 bits N-way: N * log 2 N bits Another reason why associativity often maxes out at 8 or 16. These are metadata bits, not useful program data storage. (Approximations make it not quite as bad.)

35 How would the cache change if we performed the following memory operations? (2-way set) Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) LRU of 0 means the left line in the set was least recently used. 1 means the right line was used least recently. Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

36 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) LRU of 0 means the left line in the set was least recently used. 1 means the right line was used least recently. Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

37 Stepping Through Read (Value: 5) nothing changes Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

38 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

39 Stepping Through Read (Value: 5) Read (Value: 17) cache miss (invalid), fetch block Write (Value: 7) Read (Value: 5) Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

40 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) cache miss, fetch block then write Read (Value: 5) Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

41 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) cache miss, fetch block then write Read (Value: 5) Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

42 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) hit, change of LRU Write (Value: 2) Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

43 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) cache miss, fetch block then write Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

44 Stepping Through Read (Value: 5) Read (Value: 17) Write (Value: 7) Read (Value: 5) Write (Value: 2) cache miss, fetch block then write Set # LRU V D Tag Data (4 Bytes) V D Tag Data (4 Bytes)

45 Cache Conscious Programming Knowing about caching and designing code around it can significantly affect performance (ex) 2D array accesses for(i=0; i < N; i++) { for(j=0; j< M; j++) { sum += arr[i][j]; }} for(j=0; j < M; j++) { for(i=0; i< N; i++) { sum += arr[i][j]; }} Algorithmically, both O(N * M). Is one faster than the other?

46 Cache Conscious Programming Knowing about caching and designing code around it can significantly affect performance (ex) 2D array accesses for(i=0; i < N; i++) { for(j=0; j< M; j++) { sum += arr[i][j]; for(j=0; j < M; j++) { for(i=0; i< N; i++) { sum += arr[i][j]; }} A. is faster. }} B. is faster. Algorithmically, both O(N * M). Is one faster than the other? C. Both would exhibit roughly equal performance.

47 Cache Conscious Programming The first nested loop is more efficient if the cache block size is larger than a single array bucket (for arrays of basic C types, it will be). for(i=0; i < N; i++) { for(j=0; j< M; j++) { sum += arr[i][j]; }} for(j=0; j < M; j++) { for(i=0; i< N; i++) { sum += arr[i][j]; }} (ex) 1 miss every 4 buckets vs. 1 miss every bucket...

48 Program Efficiency and Memory Be aware of how your program accesses data Sequentially, in strides of size X, randomly, How data is laid out in memory Will allow you to structure your code to run much more efficiently based on how it accesses its data Don t go nuts Optimize the most important parts, ignore the rest Premature optimization is the root of all evil. -Knuth

49 Amdahl s Law Idea: an optimization can improve total runtime at most by the fraction it contributes to total runtime If program takes 100 secs to run, and you optimize a portion of the code that accounts for 2% of the runtime, the best your optimization can do is improve the runtime by 2 secs. Amdahl s Law tells us to focus our optimization efforts on the code that matters: Speed-up what is accounting for the largest portion of runtime to get the largest benefit. And, don t waste time on the small stuff.

50 A quick recap of course so far Digital circuits Reality: Computers are big piles of transistors and capacitors Illusion: Computers are made of high-level components that we can understand Abstraction: Circuits made of logic gates High-level circuits (MUX, latches, adders) Components: (ALU, registers, etc.)

51 A quick recap of course so far Communicating with Hardware Reality: Machine code is nearly unreadable except to experts

52 A quick recap of course so far Communicating with Hardware Reality: Machine code is nearly unreadable except to experts Illusion: Computers talk near human language Abstraction: Assembly code makes machine code look more readable Compilers can turn high-level programming languages into assembly and machine code for us

53 A quick recap of course so far Memory Hierarchy Reality: Many types of memory with different costs and speed Illusion: We have very large (almost unlimited) amount of very fast memory Abstraction: Memory addresses all look the same (just let the hardware take care of caching)

54 A taste of things to come Processes Reality: Dozens (hundreds?) of programs are running on a computer with a limited number of cores Illusion: Each program is always running on its own core Abstraction: When programming, assume that your program is running on the CPU full time (just let the OS take care of switching)

55 A taste of things to come Memory addressing Reality: We only have one big chunk of RAM addressed from 0 to whatever (16 billions something something) Illusion: Each process has its own memory space, (e.g. their stack always starts at 0xFFFFFFFF) Abstraction: Access memory as if your program has its own (just let the OS take care of translating)

56 Up Next: Operating systems, Processes Virtual Memory

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