ELCT201: DIGITAL LOGIC DESIGN

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ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.

1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter 2017

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 4-VARIABLE MAP Notice the order of the minterms Remember that the cells in the top row are adjacent to the cells in the bottom row Remember that cells in the most left column are adjacent to the cells in the most right column Remember that the cells in the four corners are adjacent to each 3

4 NOTES ON A 4-VARIABLE MAP The number of adjacent squares that may be combined must always represent a number that is a power of two, such as 1, 2, 4, 8 and 16 As more adjacent squares are combined, we obtain a product term with fewer literals One square represents one minterm, giving a term with 4 literals Two adjacent squares represent a term with 3 literals Four adjacent squares represent a term with 2 literals Eight adjacent squares represent a term with 1 literal Sixteen adjacent squares encompass the entire map and produce a function that is always equal to logic 1 4

5 4-VARIABLE MAP: EXAMPLE I Simplify the Boolean expression: F A, B, C, D = Σ(0,1,2,4,5,7,8,9,10,12,13) 5

6 4-VARIABLE MAP: EXAMPLE I Simplify the Boolean expression: F A, B, C, D = Σ(0,1,2,4,5,7,8,9,10,12,13) F A, B, C, D = C + B D + A BD 6

7 4-VARIABLE MAP: EXAMPLE II Simplify the Boolean expression: F w, x, y, z = Σ(0,1,2,4,5,6,8,9,12,13,14) 7

8 4-VARIABLE MAP: EXAMPLE II Simplify the Boolean expression: F w, x, y, z = Σ(0,1,2,4,5,6,8,9,12,13,14) F w, x, y, z = y + w z + xz 8

9 CHOICE OF BLOCKS We can simplify a function by using larger blocks Do we really need all blocks? Can we leave some out to further simplify an expression? Any function needs to contain a special type of blocks These are called Essential Prime Implicants We need to define some new terms: Implicant Prime implicant Essential prime implicant 9

TERMINOLOGY Implicant (I) Any product term in the SOP form A block of 1s in a K-map Prime implicant (PI) Block of 1s that cannot be further increased Product term that cannot be further reduced

10 TERMINOLOGY Implicant (I) Any product term in the SOP form A block of 1s in a K-map Prime implicant (PI) Block of 1s that cannot be further increased Product term that cannot be further reduced Essential prime implicant (EPI) A prime implicant on a K-map which covers at least one 1 which is not covered by any other prime implicant is called an Essential Prime Implicant Is C an essential prime implicant? 10

11 THE SYSTEMATIC PROCEDURE FOR SIMPLIFYING BOOLEAN FUNCTIONS 1. Generate all Prime Implicants of the function 2. Include all Essential Prime Implicants 3. For the remaining minterms not included in the Essential Prime Implicants, select a set of other Prime Implicants to cover them, with minimal overlap in the set 4. The resulting simplified function is the logical OR of the product terms selected above 11

12 ILLUSTRATING THE TERMS: EXAMPLE I The Prime Implicants are: A D gray, AC rose, BC D pink, CD purple, ABD green, A BC (yellow). Of which only three are Essential: A D gray, AC rose and BC D pink. 12

13 ILLUSTRATING THE TERMS: EXAMPLE II The Prime Implicants are: BD gray, A BC yellow, AC D purple, ABC green, A CD rose. Of which only four are Essential: A BC yellow, AC D purple, ABC green and A CD rose. 13

14 PRODUCT OF SUMS SIMPLIFICATION USING K-MAPS Use the SOP simplification on the zeros of the function in the K-map to get F Find the complement of F, i.e. F = F Recall that the complement of a Boolean function can be obtained by (1) taking the dual and (2) complementing each literal Or by using DeMorgan s theorem 14

15 PRODUCT OF SUMS MINIMIZATION How to generate a POS from a K- map? Use duality of Boolean algebra (DeMorgan s law) Look at the 0s in map instead of the 1s Generate blocks around the 0s This gives the inverse of F Use duality to generate POS Example: F = (0,1,2,5,8,9,10) F = AB + CD + BD F = (A + B )(C + D )(B + D) 15

16 GATE IMPLEMENTATION 16

17 EXAMPLE ON POS MINIMIZATION Given the K-map below, produce the F from the zeros in the map and then obtain F from it F = AB +AC +A BCD F = (AB )(AC )(A BCD ) F = (A + B)(A + C)(A + B + C + D) 17

18 DON T CARE CONDITIONS There may be a combination of input values which: Will never occur, If they do occur, the output is of no concern The function value for such combinations is called a don t care They are usually denoted with an X Each X may be arbitrarily assigned the value 0 or 1 in an implementation Don t cares can be used to further simplify a function 18

19 MINIMIZATION USING DON T CARES Treat don t cares as if they are 1s to generate Prime Implicants Delete Prime Implicants that cover only don t care minterms Treat the covering of the remaining don t care minterms as optional in the selection process (i.e. they maybe, but need not be covered) 19

20 MINIMIZATION EXAMPLE F w, x, y, z = (1,3,7,11,15) and d w, x, y, z = (0,2,5) What are the possible solutions? 20 20

21 EXAMPLE INVOLVING X Simplify the function whose K-map is shown at the right F = A C D + AB + CD + A BC or F = A C D + AB + CD + A BD 21

22 ANOTHER EXAMPLE Simplify the function whose K-map is shown at the right F = A C + AB or F = A C + BD 22

23 NAND AND NOR IMPLEMENTATIONS Digital circuits are frequently constructed with NAND or NOR gates rather than AND & OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families A NAND gate has the smallest propagation time delay among the other gates, except for the inverter! 23

24 NAND AND NOR IMPLEMENTATIONS Each NAND or NOR gate requires only 4 transistors Each AND gate requires 6 transistors 24

25 LOGIC OPERATION WITH NAND GATE NOT, AND, and OR can be implemented with NAND! 25

26 CONVERSION TO NAND IMPLEMENTATION Minimized expressions are AND-OR combinations There are two illustrations for NAND gates Key observation: two bubbles eliminate each other Two bubbles equal a straight wire How to generate a sum of minterms using NAND? Use AND-invert for minterms Use invert-or for sum 26

27 CONVERSION TO NAND IMPLEMENTATION Sum of minterms Replace AND with AND-invert and OR with invert-or Still the same circuit! Replace AND-invert and invert-or with NAND F = (A B )(C D ) = AB + CD 27

28 NAND EXAMPLE IMPLEMENTATION Minimize and implement the function F(x, y, z) = (1,2,3,4,5,7), using only NAND gates 28

29 MULTILEVEL NAND CIRCUITS Multilevel circuits conversion rules: 1. Convert all AND gates to NAND with AND-invert symbols 2. Convert all OR gates to NAND with invert-or symbols 3. Check all bubbles in the diagram. For every bubble that is not compensated by another bubble, insert an inverter. Example: 29

30 MULTILEVEL NAND CIRCUITS: AN EXAMPLE F = (AB + A B)(C + D ) 30

31 LOGIC OPERATION WITH NOR GATE NOR can also replace NOT, AND & OR There are two representations of the NOR gate: 31

32 CONVERTING TO NOR IMPLEMENTATIONS Same rules as for NAND implementations F = (AB + A B)(C + D ) With NOR F = (AB + A B)(C + D ) 32

33 DESIGN PROBLEM Design a digital system whose output is defined as logically low if the 4-bit input binary number is a multiple of 3; otherwise, the output will be logically high. The output is defined if and only if the input binary number is greater than 2. 33

34 DESIGN PROBLEM Design a digital system whose output is defined as logically low if the 4-bit input binary number is a multiple of 3; otherwise, the output will be logically high. The output is defined if and only if the input binary number is greater than 2. 34

35 DESIGN PROBLEM 35

36 DESIGN PROBLEM SOP POS Y SOP = B D + A C + A BD + BC D + AB C + ACD Y POS = (A + B)(B + C + D )(A + C + D)(A + B + C + D)(A + B + C + D ) 36

37 DESIGN PROBLEM What if you are asked to implement these digital circuits using only NAND gates? Is that possible? 37

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter