Intel x86-64 and Y86-64 Instruction Set Architecture

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1 CSE 2421: Systems I Low-Level Programming and Computer Organization Intel x86-64 and Y86-64 Instruction Set Architecture Presentation J Read/Study: Bryant , 4.1 Gojko Babić Intel x86 Processors Totally dominate laptop/desktop/server market. Evolutionary design: backwards compatible up until 8086, introduced in 1978, added more features as time goes on. Have complex instruction set computer (CISC): many different instructions with many different formats, but, only small subset of instructions encountered with Linux/gcc application programs. Hard to match performance of reduced instruction set computers (RISC): but, Intel has done just that! in terms of speed, but less so for low power. Presentation J 2 1

2 Intel x86 Evaluation: Milestones Name Year Number of Transistors Clock (MHz) K 5-10 First 16-bit processor. Basis for IBM PC & DOS 1MB address space K First 32 bit processor, referred to as IA-32, Added flat addressing and capable of running Unix, Pentium M 2,800-3,800 First 64-bit processor, referred to as x86-64 Core i M 2,667-3,333 Presentation J 3 Intel Core i7 Organization Processor package Core 0 Regs Core 3 Regs L1 d-cache L1 i-cache L2 unified cache L1 d-cache L1 i-cache L2 unified cache L3 unified cache (shared by all cores) Main memory Presentation J 4 2

3 X86-64 Integer Registers %rax %eax %r8 %r8d %rbx %ebx %r9 %r9d %rcx %ecx %r10 %r10d %rdx %edx %r11 %r11d %rsi %esi %r12 %r12d %rdi %edi %r13 %r13d %rsp %esp %r14 %r14d %rbp %ebp %r15 %r15d Can reference low-order 4 bytes (also low-order 1 & 2 bytes) But we shall consider only instructions manipulating 64-bit data Presentation J 5 x86-64 supports register, immediate and memory addressing. The most general assembly form for memory address D(Rb,Ri,S) where: D Constant displacement using 1, 2, or 4 bytes, Rb base register: any of 16 integer registers, Ri index register: any of 16 integer registers, except %rsp S scale: 1, 2, 4, or 8 (why those numbers?) refers to the following way to calculate address: [Rb]+S*[Ri]+ D Instruction: addq %rdx, 204(%r15, %rbx,8) adds a content of register %rdx (register addressing) and a content of memory location with address calculated as [%r15]+[%rbx]*8+204, and stores result in the memory location of the second operand. g. babic x86-64 Addressing Modes Presentation J 6 3

4 Simpler x86-64 Memory Addressing Modes Mem[[R]] Register R specifies memory address: e.g. addq (%rcx),%rax adds a memory content with address in register %rcx and a content of register %rax, and stores result of addition in %rax Mem[[R]+D] Register R specifies start of memory region, while constant displacement D specifies offset e.g. addq %rdx, 8(%rbp) g. babic adds a content from register %rdx and a content of memory with address calculated as a sum of a content of register %rbp and constant 8 and stores result of addition in the memory location of the second operand. Presentation J 7 Moving data assembly instruction: movq Source, Dest Operand Types: Move Data Instruction Immediate: Constant integer data; can be source only. Example: $0x400, $-533 Like C constant, but prefixed with $ Encoded with 1, 2, or 4 bytes Register: One of 16 integer registers Example: %rax, %r13 But do not use %rsp since reserved for special use Memory: 8 consecutive bytes of memory address Simplest example: (%rax) Various other memory address modes Presentation J 8 4

5 movq Operand Combination Source Dest Example C Analog Imm Reg Mem movq $0x4,%rax temp = 0x4; movq $-147,(%rax) *p = -147; movq Reg Reg Mem movq %rax,%rdx movq %rax,(%rdx) temp2 = temp1; *p = temp; Mem Reg movq (%rax),%rdx Cannot do memory-memory transfer with a single instruction Similar operand combinations for 2 operand instructions Try addq instruction instead of movq instruction above. Note that x-86 has 2-address instructions temp = *p; Presentation J 9 Memory Address Computation Examples Carnegie Mellon %rdx %rcx 0xf000 0x0100 Expression Address Computation Address 0x8(%rdx) (%rdx,%rcx) (%rdx,%rcx,4) 0x80(,%rdx,2) 0xf x8 0xf x100 0xf *0x100 2*0xf x80 0xf008 0xf100 0xf400 0x1e080 Presentation J 10 5

6 x86-64 Instruction Format X86-64 instruction (length from one to 17 bytes) consist of: optional instruction prefixes (in any order), 1-3 opcode bytes determines the action of the instruction, an addressing-form specifier (if required) consisting of: the ModR/M byte - addressing modes register/memory, sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), an immediate data field (if required). 11 Examples of Arithmetic Instructions Carnegie Mellon Two Operand Instructions: Format Computation addq Src,Dest Dest = Dest + Src subq Src,Dest Dest = Dest Src imulq Src,Dest Dest = Dest * Src salq Src,Dest Dest = Dest << Src Also called shlq sarq Src,Dest Dest = Dest >> Src Arithmetic shrq Src,Dest Dest = Dest >> Src Logical xorq Src,Dest Dest = Dest ^ Src andq Src,Dest Dest = Dest & Src orq Src,Dest Dest = Dest Src No distinction between signed and unsigned int (why?) Presentation J 12 6

7 Examples of Arithmetic Instructions (cont.) Carnegie Mellon One Operand Instructions incq Dest Dest = Dest + 1 decq Dest Dest = Dest 1 negq Dest Dest = Dest notq Dest Dest = ~Dest See book for more instructions Presentation J 13 Introduction to Y86-64 Y86-64 instruction set architecture is hypothetical one: Similar instructions x86-64, but much fewer instructions and addressing modes and encodings much simpler somewhere between CISC and RISC, relatively easy to learn assembly language programming. Processor (CPU) Main Memory 0 PC Register file Condition Codes Addresses Data Instructions Object Code & Program Data %rsp Stack Presentation J??? 7

8 Y86-64 Programmer Visible State RF: Program registers 0 %rax 1 %rcx 2 %rdx 3 %rbx 4 %rsp 5 %rbp 6 %rsi 7 %rdi %r8 %r9 %r10 %r11 %r12 %r13 %r14 CC: Condition codes ZF SF OF Main Memory: byte addressable array PC Presentation J 15 Y86-64 Programmer Visible State (cont.) bit integer registers: except missing %r15, same as in x Condition codes: single-bit flags set by arithmetic or logical instructions, ZF: zero flag, SF sign flag, OF: overflow flag. X86-64 has in addition CF: carry flag. 64-bit Program counter: indicates address of instruction in execution. Main Memory (as x86-64): byte-addressable storage array, words stored in little-endian byte order. Presentation J 16 8

9 Y86-64 Instruction Formats Byte halt 0 0 nop 1 0 rrmov ra, rb 2 0 ra rb irmovq V, rb 3 0 0xF rb V rmmovq ra, D(rB) 4 0 ra rb D mrmovq D(rB), ra 5 0 ra rb D OPq ra, rb 6 fn ra rb jxx Dest 7 fn Destination cmovxx ra, rb 2 fn ra rb call Dest 8 0 Destination ret 9 0 pushq ra A 0 ra 0xF popq ra B 0 ra 0xF 17 Y86-64 Arithmetic and Logical Instructions Add addq ra, rb 6 0 ra rb [ra] + [rb] rb; [PC]+2 PC Subtract subq ra, rb And andq ra, rb 6 1 ra rb 6 2 ra rb [rb] [ra] rb; [PC]+2 PC [ra] & [rb] rb; [PC]+2 PC Exclusive-Or xorq ra, rb 6 3 ra rb [ra] ^ [rb] rb; [PC]+2 PC As side effect, each of these instructions sets: ZF flag to 1 if the result is zero, to 0 otherwise, SF flag to the value of the most significant bit of the result, OF flag to 1 if there is 2 s complement overflow, 0 otherwise. Only those Y86-64 instructions can set the flags. Presentation J 18 9

10 Arithmetic & Logical Instruction Examples Y86-64 Instruction Encoding addq %rbx, %rdx subq %rsp, %rbx andq %rbp, %rcx xorq %rsi, %rdi addq $0xabcd, %rdx subq %rsp, %rbx x86-64 Instruction # 0xabcd+[%rdx] %rdx # [%rbx]-[%rsp] %rbx andq -12(%rbp),%rcx # Mem[[%rbp]-12]&[%rcx] %rcx addq %rsi,0x41(%rsp) # [%rsi]+mem[[%rsp]+0x41] Mem[[%rsp]+0x41] These x86-64 instructions as the first operand can have an immediate, a register or memory, as the second a register or memory, and as the destination for its result a register or memory, and data can be 64, 32-bits, 16-bits or byte. Presentation J 19 Y86-64 Reg-to-Reg Move Instructions Move Unconditionally rrmovq ra, rb 2 0 ra rb Move When Less or Equal cmovle ra, rb 2 1 ra rb rrmovl instruction copies value from source register ra to destination register rb, i.e. [ra] rb Move When Less cmovl ra, rb Move When Equal cmove ra, rb Move When Not Equal cmovne ra, rb 2 2 ra rb 2 3 ra rb 2 4 ra rb All other reg-to-reg move instructions conditionally copy value from source register ra to destination register rb, based on values of condition codes. Move When Greater or Equal cmovge ra, rb 2 5 ra rb Move When Greater cmovg ra, rb 2 6 ra rb All these instructions also increment PC by 2, i.e. [PC] + 2 PC Presentation J 20 10

11 Y86-64 Move Conditions cmovle instruction (move when Less or Equal) move condition: (SF^OF) ZF cmovl instruction (move when Less) move condition: SF^OF cmove instruction (move when Equal) move condition: ZF cmovne instruction (move when Not Equal) move condition: ~ZF cmovge instruction (move when Greater or Equal) move condition: ~(SF^OF) cmovg instruction (move when Greater) move condition: ~(SF^OF) & ~ZF X86-64 includes these instructions and additional conditional move instruction involving CF. g. babic Presentation J 21 Y86-64 Immediate & Memory Move Instructions Move Immediate to Register irmovq V, rb 3 0 0xF rb V Move Register to Memory rmmovq ra, D(rB) 4 0 ra rb D Move Memory to Register mrmovq D(rB), ra 5 0 ra rb D V rb [ra] Memory[[rB]+D] Memory[[rB]+D] ra Memory address calculation for move instructions: memory address = [rb] + D Note: register id 15 (0xF) indicates no register. All these instructions increment PC by 10, i.e. [PC] + 10 PC Presentation J 22 11

12 Move Instruction Examples Y86-64 Instruction Encoding irmovq 0xabcd, %rdx 30 F2 cd ab rrmovq %rsp, %rbx mrmovq -12(%rbp),%rcx f4 ff ff ff ff ff ff ff rmmovq %rsi,0x41c(%rsp) c Equivalent x86-64instruction movq $0xabcd, %rdx movq %rsp, %rbx movq -12(%rbp),%rcx movq %rsi,0x41c(%rsp) X86-64 has more instructions of this type, including instructions moving bytes,16-bit and 32-bit data (in addition to 64-bit data), with sign-extend and zero-extend and with many memory addressing modes. Presentation J 23 Jump Unconditionally jmp Destination 7 0 Destiantion Jump When Less or Equal jle Destination 7 1 Destination Jump When Less jl Destination 7 2 Jump When Equal je Destination 7 3 Destination Destination Jump When Not Equal jne Destination 7 4 Destination Jump When Greater or Equal jge Destination 7 5 Destination Jump When Greater jg Destination 7 6 Y86-64 Jump Instructions Desinationt jmp instruction copies value from its Destination field to PC, i.e. [Destiantion] PC Each other jump instruction copies a value from its Destination field to PC if jump condition is satisfied, otherwise PC value is incremented by 9 (the length of jump instruction) These Y86-64 jump instructions are the same as in x86-64, but they are a subset of x86-64 jump instructions. Presentation J 24 12

13 Y86-64 Jump Conditions jle instruction (jump when Less or Equal) jump condition: (SF^OF) ZF jl instruction (jump when Less) jump condition: SF^OF je instruction (jump when Equal) jump condition: ZF jne instruction (jump when Not Equal) jump condition: ~ZF jge instruction (jump when Greater or Equal) jump condition: ~(SF^OF) jg instruction (jump when Greater) jump condition: ~(SF^OF) & ~ZF X86-64 includes these instructions and additional conditional jmp instructions involving CF. Presentation J 25 Y86-64 Stack Instructions Stack is a region of memory managed with stack discipline and holding program data used for supporting function calls. Stack top is addressed (pointed) by the content %rsp. Stack grows toward lower addresses: top element is at lowest address in the stack, when pushing, must first decrement stack pointer, after popping, increment stack pointer. pushq ra A 0 ra 0xF popq ra B 0 ra0xf Decrement %rsp by 8 Store word from ra to memory at (%rsp) Read word from memory at (%rsp) Save in ra Increment %rsp by 8 [PC] + 2 PC [PC] + 2 PC In addition to these, x86-64stack instructions can also have as an operand memory or immediate (push only)

14 Stack Carnegie Mellon Stack Bottom Increasing Addresses Stack Pointer: %rsp Stack Grows Down Stack Top Presentation J 27 Stack: Push pushq Src: Fetch operand at Src Decrement %rsp by 8 Write operand at address given by %rsp Stack Bottom Increasing Addresses Stack Pointer: %rsp 8 Stack Grows Down Stack Top Stack Top Presentation J 28 14

15 Stack: Pop popq Dst: Fetch operand at address given by %rsp Write operand at address Dst Increment %rsp by 8 Stack Bottom Increasing Addresses Stack Pointer: %rsp +8 Stack Grows Down Note: popq %rsp is a special case! Stack Top Presentation J 29 Y86-64 & x86-64 Stack Operation Example Initially %rax 0x123 %rdx??? %rsp 0x108 pushq %rax %rax %rdx %rsp 0x123??? 0x100 popq %rdx %rax %rdx %rsp 0x123 0x123 0x108 Stack bottom Stack bottom Stack bottom Increasing address 0x108 Stack top 0x108 0x100 0x123 Stack top subq $8, %rsp rmmovq %rax, (%rsp) 0x108 0x123 Stack top mrmovq (%rsp), %rdx addq $8, %rsp Presentation J 30 15

16 Y86-64 Function Call and Return Instructions call Destination 8 0 Destination This instruction: pushes value PC+9 (the address of the next instruction, i.e. returning address) onto stack; note this decrements a value of %rsp by 8, and [Destination] PC ret 9 0 This instruction: pops value from stack and loads it into PC; note this increments a value of %rsp by 8 X86-64 has similar call and ret instructions. Presentation J 31 Y86-64 & x86-64 Function Call Example 0x e: call 0x b90 0x : instruction after call Before call 0x b90 After call b90 0x110 0x110 0x108 0x108 0x x x0F8 0x %rsp 0x100 %rsp 0x0F8 PC 0x e PC 0x b90 Presentation J 32 16

17 Y86-64 & x86-64 Return from Function Example 0x : 90 ret Before ret After ret 0x110 0x110 0x108 0x108 0x x x0F8 0x x0F8 0x %rsp 0x0F8 %rsp 0x100 PC 0x PC 0x Presentation J 33 Y86-64 Miscellaneous Instructions nop 1 0 do nothing, except [PC] +1 PC why is it needed? halt 0 0 stop executing instructions, it will be used to stop the simulator, encoding ensures that program hitting memory initialized to zero will halt. X86-64 has comparable instruction, but can t execute it in user mode, more about CPU modes and interrupts/exceptions later. Presentation J 34 17

18 X86-64 leaq Instruction leaq (load effective address) instruction does not reference memory at all, but is actually a variant of the movq instruction, used to generate pointers for later memory references, can also be used to compactly describe common arithmetic operations, the destination operand must be a register. Assume: %rax = x and %rcx= y Instruction Result, i.e. %edx content leaq 6(%rax), %rdx 6 + x leaq (%rax, %rcx), %rdx x + y leaq (%rax, %rcx, 4), %rdx x + 4y leaq 7(%rax, %rax,8), %rdx 7 + 9x leaq 0xA(,%rcx,4),%rdx y leaq 9(%rax,%rcx,2), %rdx 9 + x + 2y 35 X86-64 Setting of Condition Codes Almost all instructions, including moves (but not leaq) set the condition codes. CF set to 1 if most recent instruction generated carry out, ZF set to 1 if most recent instruction yielded zero, SF set to 1 if most recent instruction yielded negative result, OF set to 1 if most recent instruction yielded 2's complement overflow. For logical instructions (e.g. xor), CF & OF are always set to 0. For shift instructions, CF is set to the last bit shifted out (of either end of the word) and OF is set always to 0. cmp instruction calculates S1-S2 and sets all condition codes accordingly; it doesn't modify any of registers. test instruction calculates S1&S2 and sets only ZF and SF codes accordingly. It doesn't modify any of registers

19 X86-64 Compare Instruction cmpq (compare) instruction is used for explicit setting of condition codes. Example: cmpq src2, src1 like computing (a b) without setting destination, where [src2] b [src1] a and condition code flags: ZF set to 1 if (a == b), otherwise to 0, SF set to 1 if (a b) < 0 (as signed), otherwise to 0, OF set to 1 if two s-complement (signed) overflow, i.e. if (a >0 && b <0 && (a b) <0) (a <0 && b >0 && (a b) >0), otherwise to 0, CF set to 1, if (carry out from most significant bit == 1), otherwise to 0. Presentation J 37 X86-64 Test Instruction testq instruction is used for explicit setting of condition codes. Example: testq src2, src1 like computing a & b without setting destination, where [src2] b [src1] a and condition code flags: ZF set to 1 if ((a & b) == 0), otherwise to 0, SF set to 1 if ((a & b) < 0), otherwise to 0, OF set 0 (unused), CF set 0 (unused). Presentation J 38 19

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