The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:

Size: px
Start display at page:

Download "The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:"

Transcription

1 Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and Demultiplexer ii. To understand the behavior of Multiplexer and Demultiplexer iii. To synthesize and simulate Multiplexer and Demultiplexer Theory: A multiplexer is a combinational circuit which has 2 N :1 input output ports with N and control ports. The control port is used to select one of the 2 N input and connect it to the output. A multiplexer is also called a switcher as it switches one of several input lines through to a single common output line. The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below: Y = I 0. S + I 1. S The VHDL code for synthesizing the 2x1 multiplexer is given below in all the three style of modelling. VHDL CODING library IEEE; use IEEE.STD_LOGIC_1164.ALL;

2 entity MUX2x1 is Port ( I : in STD_LOGIC_VECTOR (1 downto 0 s : in STD_LOGIC; y : out STD_LOGIC end MUX2x1; architecture Behavioral of MUX2x1 is Y <= (I(0) and (not s)) or (I(1) and s end Behavioral; Behavioural Modelling of 2x1 multiplexer in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux2x1_behave is Port ( i : in STD_LOGIC_VECTOR (1 downto 0 s : in STD_LOGIC; y : out STD_LOGIC end mux2x1_behave; architecture Behavioral of mux2x1_behave is mux2x1: process (i,s) if ( s='0') then

3 Y <= i(0 elsif( s='1') then Y <= i(1 else y <= 'Z'; end if; end process; end Behavioral; Designing a 4x1 multiplexer using 2x1 multiplexers in structural modelling A 4x1 multiplexer can be implemented in structural modelling using VHDL by using three 2x1 multiplexers. The block diagram and the VHDL code is shown below. VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX4x1 is Port ( i : in STD_LOGIC_VECTOR (3 downto 0 s : in STD_LOGIC_VECTOR (1 downto 0 y : out STD_LOGIC

4 end MUX4x1; architecture Behavioral of MUX4x1 is signal w1,w2: std_logic; X1: entity work.mux2x1 port map X2: entity work.mux2x1 port map X3: entity work.mux2x1 port map end Behavioral; (I(0)=>I(0), I(1)=>I(1),s=>s(0), y=>w1 (I(0)=>I(2), I(1)=>I(3),s=>s(0), y=>w2 (I(0)=> w1, I(1)=>w2,s=>s(1), y=> Y Test Bench for MUX 4x1: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux_4x1_tb IS

5 END mux_4x1_tb; ARCHITECTURE behavior OF mux_4x1_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MUX4x1 PORT( i : IN std_logic_vector(3 downto 0 s : IN std_logic_vector(1 downto 0 y : OUT std_logic END COMPONENT; --Inputs signali : std_logic_vector(3 downto 0) := (others => '0' signal s : std_logic_vector(1 downto 0) := (others => '0' --Outputs signal y : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: MUX4x1 PORT MAP ( i =>i, s => s, y => y -- Stimulus process stim_proc: process

6 -- hold reset state for 100 ns. wait for 1000 ns; -- insert stimulus here i<= "0001"; s<= "00"; wait for 1000 ns; i<= "0001"; s<= "00"; wait for 1000 ns; i<= "0010"; s<= "01"; wait for 1000 ns; i<= "0100"; s<= "10"; wait for 1000 ns; i<= "1000"; s<= "11"; wait for 100 ns; wait; end process; END; Special Type of Mux: Now we move a step further in defining a multi-bit output multiplexer. Here we illustrate a mux2x1_4bit that accepts two four bit input number on its two input ports A and B. The sel input is used to select one of the two four bit input and passes it on the four bit output shared bus.

7 The general bloc for a MUX2x1_4bit is shown below followed by the VHDL concurrent style of modelling. VHDL CODE: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux2_1_nbit_wide IS Generic ( N: integer :=4 PORT(in_a : IN STD_LOGIC_VECTOR(N DOWNTO 0 --input a in_b : IN STD_LOGIC_VECTOR(N DOWNTO 0 --input b sel : IN STD_LOGIC; --select input output : OUT STD_LOGIC_VECTOR(N DOWNTO 0) --data output END mux2_1_nbit_wide; ARCHITECTURE dataflow OF mux2_1_nbit_wide IS BEGIN WITH sel SELECT output<= in_a WHEN 0, in_b WHEN 1, (OTHERS => X ) WHEN OTHERS; END dataflow; OTHERS again Here we see OTHERS used to match cases where sel is not 1 or 0 in the WHEN OTHERS clause. i.e.: (OTHERS => X ) WHEN OTHERS; OTHERS is also used to provide a shorthand method of saying, make all the bits of the target signal X for however many bits are in target signal. (OTHERS => X ) WHEN OTHERS;

8 De-multiplexer: A de-multiplexer is a combinational circuit that behavior opposite to a multiplexer. It has a single input, S control inputs and 2S as output lines. Only one of the output will be activated by the control / selection lines and the input I will be transferred on the selected output line. Figure below shows the block diagram of the demultiplexer Output equations: Y0 = I.S1.S0 Y1 = I.S1.S0 Y2 = I.S1.S0 Y3 = I.S1.S0 VHDL Code: entitydemux is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0 Y : out STD_LOGIC_VECTOR (3 downto 0) enddemux; architecture Behavioral of DeMux is Y(0) <= I and (not S(1) ) and (not s(0) Y(1) <= I and (not S(1) ) and (s(0) Y(2) <= I and (S(1) ) and (not s(0) Y(3) <= I and (S(1) ) and (s(0) end Behavioral; TEST BENCH

9 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY DeMux_tb IS END DeMux_tb; ARCHITECTURE behavior OF DeMux_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT DeMux PORT( I : IN std_logic; S : IN std_logic_vector(1 downto 0 Y : OUT std_logic_vector(3 downto 0) END COMPONENT; --Inputs signal I : std_logic := '0'; signal S : std_logic_vector(1 downto 0) := (others => '0' --Outputs signal Y : std_logic_vector(3 downto 0 BEGIN -- Instantiate the Unit Under Test (UUT) uut: DeMux PORT MAP ( I => I, S => S, Y => Y -- Stimulus process stim_proc: process -- insert stimulus here wait for 100 ns; I <= '0'; S<= "00";

10 wait for 100 ns; I <= '1'; S<= "01"; wait for 100 ns; I <= '0'; S<= "10"; wait for 100 ns; I <= '1'; S<= "11"; wait; end process; END; Behavioural Modelling of De-Mux VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; entitydemux is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0 Y : out STD_LOGIC_VECTOR (3 downto 0) enddemux; architecture Behavioral of DeMux is

11 process(s,i) if (S="00") then Y <= "000"&I; elsif(s="01") then Y <= "00"&I&'0'; elsif (S="10") then Y <= '0'&I&"00"; else Y<= I&"000"; end if; end process; end Behavioral; SIMMULATION using ISIM

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents

VHDL Testbench. Test Bench Syntax. VHDL Testbench Tutorial 1. Contents VHDL Testbench Tutorial 1 Contents 1 VHDL Testbench 2 Test Bench Syntax 3 Testbench Example: VHDL Code for Up Down Binary Counter 4 VHDL Testbench code for up down binary counter 5 Testbench Waveform for

More information

Multi-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized

Multi-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard

More information

Introduction to VHDL #3

Introduction to VHDL #3 ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in

More information

Very High Speed Integrated Circuit Har dware Description Language

Very High Speed Integrated Circuit Har dware Description Language Very High Speed Integrated Circuit Har dware Description Language Industry standard language to describe hardware Originated from work in 70 s & 80 s by the U.S. Departm ent of Defence Root : ADA Language

More information

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.

More information

Hardware Description Language VHDL (1) Introduction

Hardware Description Language VHDL (1) Introduction Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for

More information

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language) Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable

More information

Basic Language Concepts

Basic Language Concepts Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,

More information

Solutions - Homework 2 (Due date: October 9:30 am) Presentation and clarity are very important!

Solutions - Homework 2 (Due date: October 9:30 am) Presentation and clarity are very important! ECE-8L: Computer Logic Design Fall Solutions - Homework (Due date: October rd @ 9: am) Presentation and clarit are ver important! PROBLEM ( PTS) Complete the following table. Use the fewest number of bits

More information

Test Benches - Module 8

Test Benches - Module 8 Test Benches Module 8 Jim Duckworth, WPI 1 Overview We have concentrated on VHDL for synthesis Can also use VHDL as a test language Very important to conduct comprehensive verification on your design To

More information

Chapter 8 VHDL Code Examples

Chapter 8 VHDL Code Examples APPENDIX I Chapter 8 VHDL Code Examples I.1 Introduction Two example VHDL code designs are presented in Chapter 8, the first for controlling the AD7524 digital-to-analogue converter and the second for

More information

Constructing VHDL Models with CSA

Constructing VHDL Models with CSA Constructing VHDL Models with CSA List all components (e.g., gate) inclusive propagation delays. Identify input/output signals as input/output ports. All remaining signals are internal signals. Identify

More information

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline Chapter 1 Introduction to VHDL VHDL VHDL - Flaxer Eli Ch 1-1 Course Objectives Affected Write functionally correct and well-documented VHDL code, intended for either simulation or synthesis, of any combinational

More information

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University

ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. George Mason University ECE 545 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 5.1, VHDL Process Chapter 8, Sequential

More information

In our case Dr. Johnson is setting the best practices

In our case Dr. Johnson is setting the best practices VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry

More information

ECE 545 Lecture 4. Simple Testbenches. George Mason University

ECE 545 Lecture 4. Simple Testbenches. George Mason University ECE 545 Lecture 4 Simple Testbenches George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 2.2.4, Testbenches 2 Testbenches ECE 448 FPGA and ASIC Design with VHDL 3 Testbench

More information

Chapter 6 Combinational-Circuit Building Blocks

Chapter 6 Combinational-Circuit Building Blocks Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer

More information

EENG 2910 Project III: Digital System Design. Due: 04/30/2014. Team Members: University of North Texas Department of Electrical Engineering

EENG 2910 Project III: Digital System Design. Due: 04/30/2014. Team Members: University of North Texas Department of Electrical Engineering EENG 2910 Project III: Digital System Design Due: 04/30/2014 Team Members: University of North Texas Department of Electrical Engineering Table of Content i Contents Abstract...3 Introduction...3 Report...4

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1 DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,

More information

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks. Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,

More information

Introduction to VHDL #1

Introduction to VHDL #1 ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state

More information

5. VHDL - Introduction - 5. VHDL - Design flow - 5. VHDL - Entities and Architectures (1) - 5. VHDL - Entities and Architectures (2) -

5. VHDL - Introduction - 5. VHDL - Design flow - 5. VHDL - Entities and Architectures (1) - 5. VHDL - Entities and Architectures (2) - Sistemas Digitais I LESI - 2º ano Lesson 5 - VHDL Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Introduction - VHDL was developed, in the mid-1980s, by DoD and IEEE. VHDL stands

More information

ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles

ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended

More information

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3 DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. BEHAVIORAL DESCRIPTION (OR SEQUENTIAL) In this design style,

More information

Concurrent Signal Assignment Statements (CSAs)

Concurrent Signal Assignment Statements (CSAs) Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value

More information

[VARIABLE declaration] BEGIN. sequential statements

[VARIABLE declaration] BEGIN. sequential statements PROCESS statement (contains sequential statements) Simple signal assignment statement

More information

Introduction to VHDL

Introduction to VHDL Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA

More information

VHDL in 1h. Martin Schöberl

VHDL in 1h. Martin Schöberl VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset

More information

ECE 459/559 Secure & Trustworthy Computer Hardware Design

ECE 459/559 Secure & Trustworthy Computer Hardware Design ECE 459/559 Secure & Trustworthy Computer Hardware Design VHDL Overview Garrett S. Rose Spring 2016 Recap Public Key Encryption (PKE) RSA (Rivest, Shamir and Adelman) Encryption Advanced Encryption Standard

More information

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial

More information

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine:

More information

Control and Datapath 8

Control and Datapath 8 Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system

More information

VHDL. Chapter 7. Behavioral Modeling. Outline. Behavioral Modeling. Process Statement

VHDL. Chapter 7. Behavioral Modeling. Outline. Behavioral Modeling. Process Statement Chapter 7 VHDL VHDL - Flaxer Eli Ch 7-1 Process Statement Outline Signal Assignment Statement Variable Assignment Statement Wait Statement If-Then-Else Statement Case Statement Null Statement Loop Statement

More information

Inthis lecture we will cover the following material:

Inthis lecture we will cover the following material: Lecture #8 Inthis lecture we will cover the following material: The standard package, The std_logic_1164 Concordia Objects & data Types (Signals, Variables, Constants, Literals, Character) Types and Subtypes

More information

Lattice VHDL Training

Lattice VHDL Training Lattice Part I February 2000 1 VHDL Basic Modeling Structure February 2000 2 VHDL Design Description VHDL language describes a digital system as a set of modular blocks. Each modular block is described

More information

Getting Started with VHDL

Getting Started with VHDL Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component Entities can be primitive objects or complex objects Architectures are associated

More information

VHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit

VHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design

More information

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language

More information

Lecture 3. VHDL Design Units and Methods. Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory

Lecture 3. VHDL Design Units and Methods. Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory Lecture 3 Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF4220 - Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec317bd

More information

VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2

VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2 VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware

More information

Computer-Aided Digital System Design VHDL

Computer-Aided Digital System Design VHDL بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles

More information

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3 DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. Arithmetic expressions inside asynchronous processes.

More information

IE1204 Digital Design L7: Combinational circuits, Introduction to VHDL

IE1204 Digital Design L7: Combinational circuits, Introduction to VHDL IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer

More information

CCE 3202 Advanced Digital System Design

CCE 3202 Advanced Digital System Design CCE 3202 Advanced Digital System Design Lab Exercise #2 Introduction You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDLbased designs. This lab will outline the steps necessary

More information

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 8

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 8 DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 8 PARAMETRIC CODING Techniques: generic input size, for-generate, if-generate, conv_integer. Custom-defined arrays, functions, and packages. Examples: vector

More information

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level

More information

VHDL Notes for Week 4. VHDL Programming in CprE 381. Entity and Component 9/22/2014. Generic Constant. Test bench

VHDL Notes for Week 4. VHDL Programming in CprE 381. Entity and Component 9/22/2014. Generic Constant. Test bench VHDL Notes for Week 4 VHDL Programming in CprE 381 Generic Constant Entity and component Test bench Zhao Zhang CprE 381, Fall 2013 Iowa State University Last update: 12/02/2013 Generic Constant Generic

More information

Quartus Counter Example. Last updated 9/6/18

Quartus Counter Example. Last updated 9/6/18 Quartus Counter Example Last updated 9/6/18 Create a logic design from start to a DE10 implementation This example uses best design practices This example is not about creating HDL The HDL code will be

More information

Synthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden

Synthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March

More information

ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University

ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description

More information

UNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :

UNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library : UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral

More information

FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic

FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic FPGA BASED SYSTEM DESIGN Dr. Tayab Din Memon tayabuddin.memon@faculty.muet.edu.pk Lecture 9 & 10 : Combinational and Sequential Logic Combinational vs Sequential Logic Combinational logic output depends

More information

Lecture 3. VHDL Design Units and Methods. Notes. Notes. Notes

Lecture 3. VHDL Design Units and Methods. Notes. Notes. Notes Lecture Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF4220 - Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec17bd.2

More information

EEL 4712 Name: SOLUTION Midterm 1 Spring 2016 VERSION 1 UFID:

EEL 4712 Name: SOLUTION Midterm 1 Spring 2016 VERSION 1 UFID: EEL 4712 Name: SOLUTION Midterm 1 Spring 2016 VERSION 1 UFID: Sign here to give permission to return your test in class, where other students might see your score: IMPORTANT: Please be neat and write (or

More information

EEL 4712 Digital Design Test 1 Spring Semester 2008

EEL 4712 Digital Design Test 1 Spring Semester 2008 IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Also, as always, the best answer gets the most points. COVER SHEET: Problem:

More information

Lecture 4: Modeling in VHDL (Continued ) EE 3610 Digital Systems

Lecture 4: Modeling in VHDL (Continued ) EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 4: Modeling in VHDL (Continued ) Sequential Statements Use Process process (sensitivity list) variable/constant declarations Sequential Statements end process; 2 Sequential

More information

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level

More information

Sequential Logic - Module 5

Sequential Logic - Module 5 Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the

More information

Introduction to VHDL #2

Introduction to VHDL #2 ECE 322 Digital Design with VHDL Introduction to VHDL #2 Lecture 4 Signal Assignment Statements Forms of signal assignment statements: Simple Concurrent Assignment Selected Assignment Conditional Assignment

More information

14:332:331. Computer Architecture and Assembly Language Spring Week 6

14:332:331. Computer Architecture and Assembly Language Spring Week 6 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 6 [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] Week 6.1 Spring 2005 Review: Entity-Architecture

More information

VHDL And Synthesis Review

VHDL And Synthesis Review VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only

More information

DESCRIPTION OF DIGITAL CIRCUITS USING VHDL

DESCRIPTION OF DIGITAL CIRCUITS USING VHDL DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,

More information

ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University

ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:

More information

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes)

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes) Last (family) name: Answer Key First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Midterm

More information

Lecture 12 VHDL Synthesis

Lecture 12 VHDL Synthesis CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?

More information

Contents. Appendix D VHDL Summary Page 1 of 23

Contents. Appendix D VHDL Summary Page 1 of 23 Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data

More information

CprE 583 Reconfigurable Computing

CprE 583 Reconfigurable Computing Recap 4:1 Multiplexer CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #18 VHDL for Synthesis I LIBRARY ieee

More information

Tutorial 4 HDL. Outline VHDL PROCESS. Modeling Combinational Logic. Structural Description Instantiation and Interconnection Hierarchy

Tutorial 4 HDL. Outline VHDL PROCESS. Modeling Combinational Logic. Structural Description Instantiation and Interconnection Hierarchy CS3: Hardware Lab Tutorial 4 HDL Outline VHDL basic language concepts basic design methodology Examples A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati i i i3 i4 Modeling Combinational

More information

VHDL Simulation. Testbench Design

VHDL Simulation. Testbench Design VHDL Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUT s Stimulus of UUT inputs algorithmic

More information

PACKAGE. Package syntax: PACKAGE identifier IS...item declaration... END PACKAGE [identifier]

PACKAGE. Package syntax: PACKAGE identifier IS...item declaration... END PACKAGE [identifier] Modular Design PACKAGE Package is a collection of : - Type declaration - Component declaration - Constants declaration - Subprograms (functions or procedures) Package is a separate VHDL code consisting

More information

EITF35: Introduction to Structured VLSI Design

EITF35: Introduction to Structured VLSI Design EITF35: Introduction to Structured VLSI Design Part 1.2.2: VHDL-1 Liang Liu liang.liu@eit.lth.se 1 Outline VHDL Background Basic VHDL Component An example FSM Design with VHDL Simulation & TestBench 2

More information

COVER SHEET: Total: Regrade Info: Problem#: Points. 7 (14 points) 6 (7 points) 9 (6 points) 10 (21 points) 11 (4 points)

COVER SHEET: Total: Regrade Info: Problem#: Points. 7 (14 points) 6 (7 points) 9 (6 points) 10 (21 points) 11 (4 points) EEL 4712 Midterm 3 Spring 2013 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read

More information

Digitaalsüsteemide disain

Digitaalsüsteemide disain IAY 0600 Digitaalsüsteemide disain VHDL discussion Verification: Testbenches Design verification We want to verify that our design is correct before the target PLD is programmed. The process performed

More information

EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems EE434 ASIC & Digital Systems VHDL Sequential Processing Spring 2016 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Sequential Statements Sequential statements are executed sequentially. Format ARCHITECTURE architecture_name

More information

CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\

CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,

More information

EEL 4783: Hardware/Software Co-design with FPGAs

EEL 4783: Hardware/Software Co-design with FPGAs EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description

More information

LECTURE 4: The VHDL N-bit Adder

LECTURE 4: The VHDL N-bit Adder EECS 317 Computer Design LECTURE 4: The VHDL N-bit Adder Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University Review: N-Bit Ripple-Carry Adder Hierarchical design: 2-bit adder

More information

ECE U530 Digital Hardware Synthesis. Course Accounts and Tools

ECE U530 Digital Hardware Synthesis. Course Accounts and Tools ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden

More information

Summary of FPGA & VHDL

Summary of FPGA & VHDL FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:

More information

Declarations of Components and Entities are similar Components are virtual design entities entity OR_3 is

Declarations of Components and Entities are similar Components are virtual design entities entity OR_3 is Reserved Words component OR_3 port (A,B,C: in bit; Z: out bit); end component ; Reserved Words Declarations of Components and Entities are similar Components are virtual design entities entity OR_3 is

More information

CSC / EE Digital Systems Design. Summer Sample Project Proposal 01

CSC / EE Digital Systems Design. Summer Sample Project Proposal 01 THE CATHOLIC UNIVERSITY OF AMERICA SCHOOL OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE CSC / EE 519-01 Digital Systems Design Summer 2013 Sample Project Proposal 01 Thursday

More information

EEL 4712 Digital Design Test 1 Spring Semester 2007

EEL 4712 Digital Design Test 1 Spring Semester 2007 IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. COVER SHEET: Problem: Points: 1 (15 pts) 2 (20 pts) Total 3 (15 pts) 4 (18 pts)

More information

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA Session One Outline Introducing VHDL

More information

Experiment 8 Introduction to VHDL

Experiment 8 Introduction to VHDL Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign

More information

VHDL for FPGA Design. by : Mohamed Samy

VHDL for FPGA Design. by : Mohamed Samy VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements

More information

ECE 545 Lecture 9. Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. George Mason University

ECE 545 Lecture 9. Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. George Mason University ECE 545 Lecture 9 Modeling of Circuits with a Regular Structure Aliases, Attributes, Packages George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapters 14.5 For Generate

More information

Lab 3: Standard Combinational Components

Lab 3: Standard Combinational Components Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level

More information

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014

CSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014 CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not

More information

EE261: Intro to Digital Design

EE261: Intro to Digital Design 2014 EE261: Intro to Digital Design Project 3: Four Bit Full Adder Abstract: This report serves to teach us, the students, about modeling logic and gives a chance to apply concepts from the course to a

More information

COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)

COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points) EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read

More information

The process. Sensitivity lists

The process. Sensitivity lists The process process itself is a concurrent statement but the code inside the process is executed sequentially Process label (optional) Process declarative region Process body entity Test is, : in bit;

More information

TKT-1212 Digitaalijärjestelmien toteutus. Lecture 7: VHDL Testbenches Ari Kulmala, Erno Salminen 2008

TKT-1212 Digitaalijärjestelmien toteutus. Lecture 7: VHDL Testbenches Ari Kulmala, Erno Salminen 2008 TKT-1212 Digitaalijärjestelmien toteutus Lecture 7: VHDL Testbenches Ari Kulmala, Erno Salminen 2008 Contents Purpose of test benches Structure of simple test bench Side note about delay modeling in VHDL

More information

ENGIN 241 Digital Systems with Lab

ENGIN 241 Digital Systems with Lab ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided

More information

VHDL for Synthesis. Course Description. Course Duration. Goals

VHDL for Synthesis. Course Description. Course Duration. Goals VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes

More information

Department of Electronics & Communication Engineering Lab Manual E-CAD Lab

Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION

More information

Inferring Storage Elements

Inferring Storage Elements Inferring Storage Elements In our designs, we usually use flip-flops as our storage elements. Sometimes we use latches, but not often. Latches are smaller in size, but create special, often difficult situations

More information