Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS

Size: px

Start display at page:

Download "Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS"

Allyson Chase
6 years ago
Views:

1 Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer. To use multiplexer for the implementation of logic functions. To understand the benefits of using multiplexer for logic realizations Required Components and Equipment: A. data selector/multiplexer Digital Electronics Trainer Bread Board Connecting Wires Multiplexer: A multiplexer (MUX) is a device that allows digital information from several sources to be routed onto a single line for a transmission over that line to common destination. The basic multiplexer has several input data lines and a single output line. It also has "data select inputs" which permit digital data on any one of the inputs to be switched to the output line. Multiplexer are also called Data selectors. The figure below shows a 2 X 1 Multiplexer and a 4 X 1 Multiplexer. Depending on whether S is zero or one, a 2 X 1 Multiplexer chooses A as the output or B as the output respectively. Similarly, depending on the combined value on S1 and S0, the 4 X 1 multiplexer chooses which among the inputs A, B, C, and D is chosen to be passed to the output.

2 2 X 1 Multiplexer 4 X 1 Multiplexer 74LS151 is an 8 line-to-1 line multiplexer. It has the schematic representation as shown below. Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe =1, the chip is disabled and output y = 0. If strobe = 0 then the chip is enabled and functions as a multiplexer. The multiplex function of in terms of select lines is shown in the table below. Functioning of a multiplexer is illustrated in Fig. 9.1 using its block diagram and a graphic representation of the conceptual interpretation of what the outputs of a multiplexer, in effect, correspond to. The multiplexer shown in Fig. 9.1 would be called an 8 to 1 multiplexer as it, in effect, connects its single output pin ( Y ) with one of the eight input pins (Do D7). Which input pin gets connected with the output pin is decided by the logic values combination on the select pins (So, S1, S2). Multiplexers are so designed that if the binary number formed by the combination of values at the select pins is e.g., n, then the input pin Dn gets connected to the output pin, making (Y=Dn) 9.1 Block Diagram of a Multiplexer with explanation of its Functioning

3 74LS151 is an 8 line-to-1 line multiplexer. It has the schematic representation as shown below. Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe =1, the chip is disabled and output y = 0. If strobe = 0 then the chip is enabled and functions as a multiplexer. The multiplex function of in terms of select lines is shown in the table below. PROCEDURE: Make all the connections for 74LS151 Verify its operation as a multiplexer by applying all input combinations. Record the results in table. Mention the output in terms of input line, not the level. Truth Table Inputs Outputs S2 S1 S0 Z Z

4 COMBINATIONAL LOGIC DESIGN WITH MULTIPLEXERS: The function of multiplexer as explained using Fig. 9.1 provides a simple alternative method of implementing any logic function using a multiplexer with as many data pins as the number of rows in the truth table of the function to be implemented. As illustrated in Fig. 9.2; Strobe Select Lines Output S S2 S1 S0 Y 1 X X X D D D D D D D D7 All we need to do is to connect all the entries of the output column of the logic function s truth table to all the data pins of the multiplexer in the same order as the truth-table. Then, since the input variables represent the row number (in binary number system counting from zero from the top row), connecting these variables at the select pins of the multiplexer would always select the data pin connected to the output of the same row of the truth table, in which that input combination lie; hence completely implementing the logic function. Multiplexers, however provide an even smarter alternative using which a truth-table with 2n+1 rows, (i.e., an n+1 variables function) can implemented using a multiplexer with n data pins (i.e., an n-bit multiplexer). The only extra requirement in this case is the inverted value of some input variables. Any function can then be implemented as illustrated in Fig9.3. The same function of Fig. 9.2 has been implemented by using only two input variables A & B as select inputs while the third C, 0 and 1 as data inputs. Fig. 9.2: Implementation of a Boolean Logic Fig. 9.3: Smart Implementation of a Boolean Logic Function using Multiplexer Fig. 9.4

5 This becomes possible because, as illustrated in the truth table of the Figure 9.3, because any truth table can be simplified so as to contain lesser number of rows by becoming a lesser input columns truth-table, if the output column is expressed in terms of some input variable(s). Thus, e.g., an 8 row truth table, half of whose output vales being the same as the corresponding values of one input variable, say B and the other half values being the same as another input variable, say C, can be simplified into a truth table with only two rows with output entries B and C corresponding to the 0 and 1 value of the third input variable A. Student Exercise: A. Design a 4x1 multiplexer using logic gates. Write down the logic equation of the output. Draw the logic diagram using select lines S and data lines A-D. Implement the circuit on digital trainer. Fill in the results in table. Truth Table Logic Equation S1 S0 Output Logic Diagram: B. Use the truth table of a full-adder to implement the sum and carry outputs with 8 X 1 multiplexers. How many 8 X 1 multiplexer ICs (74LS151) are required for this realization? Compare the count with that of the standard AND-OR-XOR realization. C. Implement 8 X 1 MUX in Verilog.

EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS

EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,