Computer System. Hiroaki Kobayashi 7/25/2011. Agenda. Von Neumann Model Stored-program instructions and data are stored on memory

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1 Computer System Hiroaki Kobayashi 7/25/2011 7/25/2011 Computer Engineering 1 Agenda Basic model of modern computer systems Von Neumann Model Stored-program instructions and data are stored on memory Fundamental Functions of Computer Systems Data Memory Data Processing How to control/use a computer: user s perspective Machine instructions to specify operations on computer How a computer controlled: system s perspective Instruction fetch, decode, execution, result store 7/25/2011 Computer Engineering 2

2 EDVAC in 1949 Basic Model of Modern Computers Von Neumann Computer Model Basic model of modern computers, designed and proposed by John von Neumann in 1945 First implementation in 1949; EDVAC ( Characteristics of Von-Neumann-type Computers Stored program Program and data are stored in memory Instruction read from memory, decode, data read from memory, processing (calculation), and result store to memory Linear memory space Memory cells (unit for data storage) are placed as an 1D array Each cell has its own address to specify a cell for data read and write Simple instructions to control a computer are provided such as Addition, subtraction, shift, logical AND/OR, Data move for read/write to/from memory Execution sequence control Sequentially-controlled computer that processes an instruction one by one Program (machine instructions) is processed sequentially stored on memory Special counter named program counter specifies the address of the current executing instruction. 7/25/2011 Computer Engineering 3 Change value of program counter if you want to change the sequence of execution. Basic Structure of Von-Neumann Computer Computer System Processor Control Unit Arithmetic Unit Memory Input Unit Output Unit 7/25/2011 Computer Engineering 4

3 Structure of Memory Logical Structure (visible from programmers) 1 dimensional array of memory cells Each cell stores a unit of data and has its own address to specify for data read/ write in memory Physical Structure (actual implementation) Memory devices are placed in a 2-dimensional and accessed through a combination of row and column address address data control Logical structure data cell row address Physical structure (implementation) 7/25/2011 Computer Engineering 5 column address Memory cell (1bit) Physical Memory Structure SRAM:Static Random Access Memory 1-bit memory cell column-address decoder 8-bit data Row-address decoder Data (input/output) CE: Chip Enable Input Input/output control 1-bit memory structure (plane) (control signal, WE=1 for write) Kbit 8-bit! K cells) SRAM structure 7/25/2011 Computer Engineering 6

4 Another Implementation of Memory DRAM:Dynamic Random Access Memory represent 1-bit store whether a capacitor is charged or not. Need only one transistor and one capacitor for 1-bit memory! Less hardware compared with SRAM (1/4) " More memory capacity on the same area" " # Need periodical refreshment of the memory content $ So named dynamic memory $ Longer access time for read/write of DRAM (output of address decoder) 1-bit cell of DRAM (for data read/write) 7/25/2011 Computer Engineering 7 SRAM vs. DRAM SRAM:Static Random Access Memory Use D-FF(equivalent to 4 Transistors) for 1-bit storage Stable(static) memory Fast memory access Access time: 0.5ns-5ns High (hardware) cost/1bit DRAM:Dynamic Random Access Memory Use one transistor and one capacitor for 1-bit storage More memory capacity at lower cost Unstable and need refreshment of contents Dynamic operation Refresh mechanism enlarges memory access time Access time: 50 70ns For speed-oriented memory %on-chip(processor) memory such as register and cache For capacity oriented memory %off-chip(processor) memory such as main memory (SIMM/DIMM) 7/25/2011 Computer Engineering 8

5 Basic Configuration and Operation of Computer(1/2) Memory Operation Data read from memory Specify an address to read data and bring the data to a register to have data in processor A register is an internal memory in processor Move data from memory specified to the register Data write to memory prepare data (calculation result) in a register Specify an address to write data Move data from the register to memory specified. D-FF Processor Combinational circuit Sequential circuit D-FF/capacitor &Tr 7/25/2011 Computer Engineering 9 Basic Configuration and Operation of Computer (1/2) Program Control and Calculation Basic behavior for data processing Move data from memory to processor, Perform an operation on data Store the operation result to memory Processor Example: perform an addition of two values y = a + b Data y,a,b are placed in memory Addition is performed in a processor by using an adder (combinational circuit) Processing of y=a+b is realized as a sequence of basic instructions & Execute the following four instructions sequentially Instructions 1 and 2 for data movement from memory locations a and b to internal registers Instruction 3 to perform addition of data stored in the registers, and store the result in (another) register Instruction 4 for data movement from register to memory location for y Program counter Address 7/25/2011 Computer Engineering a b y Contents Instruction1 Instruction2 Instruction3 Instruction4 Data of a Data of b Data of y

6 Sequential Processing: Basic Execution Control for Computer Computer sequentially processes instructions in order of memory locations Sequential processing Current memory location of an instruction processed by computer is hold by a register, named program counter (PC) Sequential processing is carried out by incrementing the content of PC & Basic operations specified by instructions are: data movement to/from memory, arithmetic operations In addition, special instructions (named JUMP and BRANCH) for execution control are prepared to change the order of instruction execution. Conditional branch: if then else statement loop (iteration): while, for statements Action: change the content of PC to the destination address specified by JUMP or BRANCH instruction 7/25/2011 Computer Engineering 11 How a Computer Program is Translated into Machine Instructions: Three Basic Execution Flow Available on Computers Execution order Process 1 Process 2 Process 3 Descriptions at programming level If condition While condition then process 1 do process 1 else process 2 process 2 Proc1 Satisfied Cond Not satisfied Cond Not satisfied Proc2 Proc1 Proc2 Satisfied Proc1 Proc2 Proc3 7/25/2011 Computer Engineering 12

7 Execution Control of Computer: Sequential Execution of Instructions Program Description Sequential execution of process1, process 2, process 3 proc1 proc2 proc3 Memory allocation for instructions address Inst.1 for proc. 1 Inst.2 for proc. 2 Inst.3 for proc. 3 Behavior of computer for instructions execution Step Fetch/decode/execute instruction1 Step Fetch/decode/execute instruction2 Step Fetch/decode/execute instruction3 Fetch/decode/execute following instructions 7/25/2011 Computer Engineering 13 Execution Control of Computer Execution of Conditional Branches satisfied Proc1 Program description If condition then proc 1 else proc 2 Cond Not satisfied Proc2 Memory allocation for instructions address Inst. for cond evaluation Instruction for moving the next execution to address 004, if eval of cond is not satisfied Inst for proc 1 Instruction for moving the next execution to address 005 Inst for proc2 Behavior of computer for instructions execution Step fetch/decode/execute instruction for evaluating the condition at address 000 Step fetch/decode/execute instruction for instruction for moving the next execution at address 004, if condition is not satisfied, otherwise, execute the next instruction at 002 (if condition satisfied) Step fetch/decode/execute instruction for proc1 Step fetch/decode/execute instruction for moving the next execution at address 005 if condition not satisfied Step fetch/decode/execute instruction for proc2 Fetch/decode/execute following instructions at address 005 or later 7/25/2011 Computer Engineering 14

8 Execution Control of Computer Execution of Loop (Iterations) Program description While condition do proc Proc Cond satisfied proc1 Not satisfied proc2 Memory allocation for instructions addres Inst. for cond evaluation Instruction for moving the next execution to address 004, if eval of cond is not satisfied Inst for proc1 Instruction for moving the next execution to address 000 Inst for proc2 Behavior of computer for instructions execution Step fetch/decode/execute instruction for evaluating the condition at address 000 Step fetch/decode/execute instruction for moving the next execution at address 004, if condition is not satisfied, otherwise, execute the next instruction at 002 (if condition satisfied) Step fetch/decode/execute instruction for proc1 Step fetch/decode/execute instruction for moving the next execution at address 000 Repeat Steps 1 to 4 if condition not satisfied after several iteration Step fetch/decode/execute instruction for proc2 Fetch/decode/execute following instructions at address 005 or later 7/25/2011 Computer Engineering 15 Format of Machine Instructions An instruction has a fixed bit width (for example, 32-bit) and consists of an operation code and its operands & Opecode (OPEration CODE) specifies an operation to be performed Arithmetic operations 8-bit 8-bit 8-bit 8-bit AND OR! Data movement opcode Operand Operand Operand load/store instructions Execution Control Unconditional Jump Conditional Branch Operands is an one of inputs (arguments) of an opcode Example of a 32-bit instruction format with one opcode and three operands Bits of an instruction are divided into the opcode field and operand field 7/25/2011 Computer Engineering 16

9 Roles of Opecode and Operands Three-operand instruction Three operands, two for inputs and one for output, are specified Registers or memory Instruction Format 7/25/2011 Computer Engineering 17 Other Types of Operand Specification: Reducing the Number of Operand Fields One-operand instruction Specify one operand and the others are defined implicitly Implicitly defined internal register is called Accumulator Registers or memory Two-operand instruction Two operands specified, and one of them is also used as a destination (output) Registers or memory 7/25/2011 Computer Engineering 18

10 Other Instruction Formats (1/2): Data Movement between registers and memory LD(LoaD) Instruction move data from memory to internal register Case where implicitly specified register is used LD address 1-operand (acc) " (address):always accumulator register is used as a destination Case where explicitly specify internal register used LD Reg. address 2-operand (Reg) " (address): can specify any register as a destination ST(STore) instruction move data from register to memory Case where implicitly specified register is used ST address 1-operand (acc) # (address):always accumulator register implicitly specified Case where a register explicitly specified ST Reg. address 2-operand (Reg) # (address): any register can be specified as source register 7/25/2011 Computer Engineering 19 Other Instruction Formats (2/2): Execution Control Instructions Unconditional Jump JP(JumP) instruction execute an instruction at address specified by operand JP address : 1 operand Conditional Branch $ Conditionally execute an instruction at address specified by operand based on the content of specified register JPZ(JumP Zero) instruction: if the content of implicitly or explicitly specified register is 0, execute instruction at address specified by operand JPZ address : if implicitly specified register (accumulator) is 0 goto address specified for the next execution 1-operand JPZ Reg address : if explicitly specified register is 0 go to address specified for the next execution 2-operand Similarly, JPNZ(JumP NonZero)are also defined If specified register is not zero, execute the next instruction at address specified (1 or 2 operand instructions defined 7/25/2011 Computer Engineering 20

11 Summary of Machine Instructions Commands to Computer Programming language at the lowest level to command data movement, arithmetic operations and execution control to a computer Load instructions: move data from memory to internal registers Example: Load Register1 MemoryAddress : (Reg1)"(MemAdrs) Store Instructions: move data from registers to memory Example: Store Register1 MemoryAddress : (MemAdrs)"(Reg1) Perform an operation on data stored in registers/memory Example: Add Reg1 Reg2 Reg3 : Reg1=Reg2+Reg3 Change the instruction execution flow Unconditional jump instructions: Jump Address Conditional branch instructions: BranchOnZero MemAdrs Sub-routine (procedure) call instruction Call MemAdrs Evaluation of condition for conditional branch instructions For conditions a=b, and a>b (or a<b), calculate a-b, and evaluate the result is equal to 0/Non-0, and positive ( or negative), respectively Machine-dependent X86 instruction set for Intel processors 7/25/2011 Computer Engineering 21 Example of 16-bit machine instructions A model computer handles a 16-bit word has one internal register named accumulator executes 16-bit instructions each of which consists of one opecode (4-bit) and one operand (12-bit) One operand instruction format 16 kinds of operations specified A 12-bit operand specifies a memory address between 000 and FFF (4K memory space addressable by 12-bit) Accumulator is implicitly used as operands Acc is not specified in an instruction (Acc) " (Acc) Opecode Operand Load memory to (Acc) Store (Acc) to memory Instructions and data are stored in memory 16-bit word operation Instruction format Memory space 000~FFF(12-bit addressable) Operand 1 Operand 2 Accumulator ALU: Arithmetic Logic Unit opecode Operand(to specify mem) 4-bit 12-bit 7/25/2011 Computer Engineering 22

12 16 Kinds of Instructions Defined Symbol( ) Code Meaning (*** is a 12-bit memory address) Move data to accumulator from memory Move data from accumulator to memory Unconditional jump Note: -[A] means the contents of accumulator -PC is a program counter that specifies the address of the next instruction to be executed. Shift left Shift right Stop program execution Stop program execution 7/25/2011 Computer Engineering 23 Program example Sum of integers 1 to 10 Address Instruction code (binary representation) Machine code in symbolic representation (Assembly code) Special instruction to specify data space DC: Define Constant DS: Define Storage 7/25/2011 Computer Engineering 24

13 Summary: Execution Control of a Computer Flow of instruction execution (Fetch/Decode/Exection of Instructions) Program counter Instruction decoder Memory Registers(accumulator) 7/25/2011 Computer Engineering 25 Summary: Control and Data Flow in a Computer Main memory Control Unit Program Counter Instruction fetch Specify an address of instruction to be executed Instruction area Machine Instructions Opecode Operands Specify an operation Specify operands Input/Output Unit Arithmetic Logic Unit Registers Operand fetch Result store Data Area Data Processing Unit (Processor) 7/25/2011 Computer Engineering 26

14 Schedule 8/8 Final Exam: all the registered students should take and mark a certain score for the credit. You may refer to printed-handouts given by this class during the exam. Other reference materials are not allowed. The result of the final exam, pass or not, will be announced at the class web site. Check the web in the week of Aug. 15. Make-up Exam or home assignment will be given to those who cannot pass 8/8 exam. The details will also be announced at the web. 7/25/2011 Computer Engineering 27