NetBSD on Marvell Armada XP System on a Chip
|
|
- Dorcas Short
- 6 years ago
- Views:
Transcription
1 NetBSD on Marvell Armada XP System on a Chip Zbigniew Bodek zbb@semihalf.com EuroBSDCon 2013, Malta 1
2 Presentation outline Justification for choice Hardware overview Prerequisites Device drivers Validation Integration to mainline NetBSD Comparison with the mainline FreeBSD 2
3 Justification for choice Why should we be interested in ARM? 3
4 Justification for choice Why should we be interested in ARM? Industry trend to save energy High performance solutions = new markets 4
5 Justification for choice Why should we be interested in ARM? Industry trend to save energy High performance solutions = new markets Why we invested our work in? 5
6 Justification for choice Why should we be interested in ARM? Industry trend to save energy High performance solutions = new markets Why we invested our work in? Customer requirement Known of it s portability Friendly license Active community Good alternative to other similar 6
7 Justification for choice Advantages Building for ARMv7 supported Memory management supported Whole set of drivers for older Marvell chips Disadvantages No settled support for ARMv7 platform (at the time) No SMP for ARM 7
8 Hardware overview Marvell Armada XP Quad core PJ4Bv7 2MB shared L2 cache Hardware cache coherency, I/O coherency Integrated storage (USB 2.0, SATA II, NAND, NOR...) High speed networking (NETA) PCI-Express Cryptographic engines DMA engines Advanced power management 8
9 Prerequisites Arrange booting environment Define code base Compiler availability Support for similar platform 6.0-RC1 / BEAGLE / ARMADAXP 9
10 Prerequisites Understand work to be done Is the CPU core supported? Is the SoC family supported? Is the particular board supported? What peripheral devices are supported? Armada XP New CPU core - PJ4B New SoC family - Armada XP New evaluation boards Some peripherals matching existing drivers 10
11 Prerequisites Arrange configuration files Processor specific under sys/arch/arm/marvell/files.marvell Defines core device specification for whole chip family Evaluation board specific under sys/arch/evbarm/conf/ Board specific files and option definitions files.armadaxp Extra specification for Makefile mk.armadaxp Set of board specific configuration options std.armadaxp Kernel configuration file ARMADAXP 11
12 CPU core support What does it mean? 12
13 CPU core support What does it mean? NetBSD/arm utilizes a set of cpu functions defined in: sys/arch/arm/include/cpufunc.h (see struct cpu_functions) Function wrappers for basic CPU-related operations such as: cache manipulation routines core detection and configuration (including MMU) read/write buffers, branch predictor management other 13
14 CPU core support Do not increase redundancy - sufficient CPU functions can be reused Remember of the core bugs and/or erratum Example: ENTRY(pj4b_setttb)! /* Cache synchronization is not required as this core has PIPT caches */! dsb #if defined(l2cache_enable) && defined(aurora_l2_pt_walk)! orr! r2, r0, #TTB_FLAGS_UP #else! bic! r2, r0, #0x18 #endif! mcr! p15, 0, r0, c2, c0, 0! /* load new TTB */! mov! r0, #0! isb! mcr! p15, 0, r0, c8, c7, 0! /* invalidate I+D TLBs */! RET 14
15 CPU core support 1. Create custom CPU functions sys/arch/arm/arm/cpufunc_asm_pj4b.s 2.Add new CPU to configuration files sys/arch/arm/conf/files.arm sys/arch/evbarm/conf/armadaxp 3.Add CPU class and CPU ID to auto-detection sys/arch/arm/arm32/cpu.c 4.Fill-up cpu_functions structure with the desired CPU ops 4.1.Implement <cpu>_setup routine 15
16 Start code Assumptions: Basic SoC initialization is done by firmware First part of the kernel to be executed Start code file and object is defined in mk.armadaxp Written in Assembly language: To allow relocation No environment for C code Goals to achieve: Remap kernel to the true VA Redirect to locore.s for stack initialization 16
17 Start code VA PA MMU ON 0xC MMU OFF 0x
18 Machine initialization initarm() from sys/arch/evbarm/armadaxp/armadaxp_machdep.c First C code executed Includes all actions that need to be performed before jumping to main() Goals to achieve: Bootstrap virtual memory! Create initial page tables pmap_bootstrap() Map devices for bus_space_map() Allocate and create mappings for exception vectors page, message buffer, stack, etc. Inform UVM about the available pages 18
19 Machine initialization initarm() from sys/arch/evbarm/armadaxp/armadaxp_machdep.c First C code executed Includes all actions that need to be performed before jumping to main() Goals to achieve: Initialize all crucial chip features CPU (functions) Decoding windows Clocks (time base) Interrupts (preconfigure) L2 cache I/O cache coherency 19
20 Machine initialization initarm() from sys/arch/evbarm/armadaxp/armadaxp_machdep.c First C code executed Includes all actions that need to be performed before jumping to main() Goals to achieve: Other important configurations Abort handlers Stack pointer System console KGDB 20
21 L2 cache management CPU L1 CACHE CACHE L2 CACHE 21
22 L2 cache management 1. Set L2 policy (LRU, WB) 2. Enable cache and TLB maintenance broadcast 3. Invalidate cache 4. Set PoC and PoU 5. Finally... enable L2 cache CPU functions for cache maintenance will do the rest 22
23 I/O cache coherency The Coherency Fabric i.a. forwards transactions initiated by the I/O devices and tagged with a shared attribute onto the processors snoop engine. On-chip caches can then snoop these transactions COHERENT DMA 23
24 I/O cache coherency The Coherency Fabric CPU L2 CACHE L1 CACHE COHERENCY FABRIC DRAM controller BUS DEV DEV 24
25 I/O cache coherency Adjustments (hacks) to the bus_dma and pmap Set the pages attributes to shared Override default non-coherent settings in _bus_dmamap_load_mbuf() _bus_dmamap_load_buffer() Add HW synchronization barrier to _bus_dmamap_sync() NO NEED FOR SW CACHE MAINTENANCE ON I/O! 25
26 Atomic operations Issues with atomic byte swapping required for locking Deprecated swp and swpb instructions resulted in undefined instruction exceptions in kernel. Exchanged to ldrex strex pair Added barriers after acquiring the lock & before releasing More issues with the building distribution. Undefined instructions (swp & swpb) in shared libraries. Need for passing ARM_ARCH_7 definition to distribution build Inserting barrier instruction opcode for non-kernel builds DMB!.word 0xf57ff05f 26
27 Interrupts Multiprocessor Interrupt Controller CPU 4 HW prioritization MPIC DEV0 DEV1 DEV2 DEV3 27
28 Interrupts Multiprocessor Interrupt Controller Great for implementing NetBSD SPL mechanism Increasing/decreasing prio done in HW Controller takes care of proper interrupts notification Much faster and simpler than the solution for older Marvell chips All pic_ops needed to be implemented - establishing - blocking - unblocking 28
29 Marvell SoC abstract bus (mvsoc) Armada XP support attached to the existing mvsoc mvsoc bus uses direct configuration method Resource description is not taken from the array dynamically created by config(8) basing on the configuration nodes from kernel configuration file All resources are defined in advance Bus needs to probe drivers to know their existence 29
30 Marvell SoC abstract bus (mvsoc) Generic bus for all Marvell platforms Unified autoconfiguration process Unified chip-detection Common resource management Was already in the tree Difficult to maintain for a large number of platforms 30
31 Device drivers Reused in-tree drivers for: Timers (with significant changes) Serial IF (added support for ns16750) PCIe (mvpex with adjustments) USB (with changes) SATA RTC I2C (with changes) Developed Network Accelerator SPI (for Flash) 31
32 Validation Testing with ATF (Automated Testing Framework) Simple way for overall system reliability check atf-run atf-report and wait (then read log) Helped in finding undefined instructions in libraries 2904 passed test cases 71 failed test cases (mostly known issues for that baseline) Testing suites: LMbench iperf Long runs of distribution buils 32
33 Integration to mainline NetBSD Changes in the current development branch Fixed bugs with atomic operations Unified and simplified initarm() NetBSD/arm community remarks Upstreamed features: Armada XP essentials ns16750 support SPI driver Bug fixes to: spiflash.c, mvpex.c 33
34 Integration to mainline NetBSD Not in the mainline: Networking driver I/O cache coherency support 34
35 Comparison with the mainline FreeBSD SMP support (quad core operations) FDT support Superpages support Existing device drivers: MPIC Timers UART PCIe SATA USB 2.0 I2C UP only Hard-coded device descriptions Existing device drivers: MPIC Timers UART PCIe SATA USB 2.0 I2C SDIO SPI 35
36 Acknowledgements Mentors of the project Rafał Jaworowski (Semihalf, The FreeBSD Project) Bartłomiej Sięka (Semihalf) People involved Grzegorz Bernacki Michał Dubiel Grzegorz Jaszczyk Pablo Ribalta Marcin Wojtas 36
37 Acknowledgements Special thanks to Radosław Kujawa (NetBSD project) Shadi Ammouri (Marvell) 37
38 Any questions? 38
FreeBSD and NetBSD on APM86290 System on Chip
FreeBSD and NetBSD on APM86290 System on Chip Zbigniew Bodek Semihalf zbb@semihalf.com Abstract This paper covers recent development work on porting FreeBSD/powerpc and NetBSD/evbppc to the new APM86290
More informationARMv8-A Software Development
ARMv8-A Software Development Course Description ARMv8-A software development is a 4 days ARM official course. The course goes into great depth and provides all necessary know-how to develop software for
More informationSpring 2017 :: CSE 506. Device Programming. Nima Honarmand
Device Programming Nima Honarmand read/write interrupt read/write Spring 2017 :: CSE 506 Device Interface (Logical View) Device Interface Components: Device registers Device Memory DMA buffers Interrupt
More informationCortex-A9 MPCore Software Development
Cortex-A9 MPCore Software Development Course Description Cortex-A9 MPCore software development is a 4 days ARM official course. The course goes into great depth and provides all necessary know-how to develop
More informationI/O Devices. Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau)
I/O Devices Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau) Hardware Support for I/O CPU RAM Network Card Graphics Card Memory Bus General I/O Bus (e.g., PCI) Canonical Device OS reads/writes
More informationCortex-A15 MPCore Software Development
Cortex-A15 MPCore Software Development Course Description Cortex-A15 MPCore software development is a 4 days ARM official course. The course goes into great depth and provides all necessary know-how to
More informationFreeBSD on Cavium ThunderX System on a Chip
FreeBSD on Cavium ThunderX System on a Chip Zbigniew Bodek, Wojciech Macek Semihalf, zbb@{semihalf.com, freebsd.org}, wma@semihalf.com Abstract This paper describes the FreeBSD operating system port for
More informationDepartment of Computer Science, Institute for System Architecture, Operating Systems Group. Real-Time Systems '08 / '09. Hardware.
Department of Computer Science, Institute for System Architecture, Operating Systems Group Real-Time Systems '08 / '09 Hardware Marcus Völp Outlook Hardware is Source of Unpredictability Caches Pipeline
More informationARM CORTEX-R52. Target Audience: Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecture.
ARM CORTEX-R52 Course Family: ARMv8-R Cortex-R CPU Target Audience: Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecture. Duration: 4 days Prerequisites and related
More informationMicrokernels and Portability. What is Portability wrt Operating Systems? Reuse of code for different platforms and processor architectures.
Microkernels and Portability What is Portability wrt Operating Systems? Reuse of code for different platforms and processor architectures. Contents Overview History Towards Portability L4 Microkernels
More informationFCQ2 - P2020 QorIQ implementation
Formation P2020 QorIQ implementation: This course covers NXP QorIQ P2010 and P2020 - Processeurs PowerPC: NXP Power CPUs FCQ2 - P2020 QorIQ implementation This course covers NXP QorIQ P2010 and P2020 Objectives
More informationCopyright 2016 Xilinx
Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building
More informationCortex-A5 MPCore Software Development
Cortex-A5 MPCore Software Development תיאורהקורס קורסDevelopment Cortex-A5 MPCore Software הינו הקורס הרשמי שלחברת ARM בן 4 ימים, מעמיקמאודומכסהאתכלהנושאיםהקשוריםבפיתוחתוכנה לפלטפורמותמבוססותליבת.Cortex-A5
More information19: I/O. Mark Handley. Direct Memory Access (DMA)
19: I/O Mark Handley Direct Memory Access (DMA) 1 Interrupts Revisited Connections between devices and interrupt controller actually use interrupt lines on the bus rather than dedicated wires. Interrupts
More informationPCIe driver development for Exynos SoC
PCIe driver development for Exynos SoC Korea Linux Forum 2013 Jingoo Han Samsung Electronics Introduction S/W engineer at Samsung Electronics since 2005 Linux kernel development for Samsung Exynos ARM
More informationCS5460: Operating Systems
CS5460: Operating Systems Lecture 2: OS Hardware Interface (Chapter 2) Course web page: http://www.eng.utah.edu/~cs5460/ CADE lab: WEB L224 and L226 http://www.cade.utah.edu/ Projects will be on Linux
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 5. Large and Fast: Exploiting Memory Hierarchy
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 5 Large and Fast: Exploiting Memory Hierarchy Principle of Locality Programs access a small proportion of their address
More informationCavium ThunderX2 CN99XX PMU Events (Abridged) July 31, 2018
Cavium ThunderX2 CN99XX PMU s (Abridged) July 31, 2018 1 Introduction The ARM architecture defines several events as part of the Performance Monitor Unit (PMU) Extension. The Cavium ThunderX2 CN99XX processor
More informationVeloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics
Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2 Veloce Emulation Use
More informationFPQ9 - MPC8360E implementation
Training MPC8360E implementation: This course covers PowerQUICC II Pro MPC8360E - PowerPC processors: NXP Power CPUs FPQ9 - MPC8360E implementation This course covers PowerQUICC II Pro MPC8360E Objectives
More information«Real Time Embedded systems» Multi Masters Systems
«Real Time Embedded systems» Multi Masters Systems rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Chargé de cours rene.beuchat@hesge.ch LSN/hepia Prof. HES 1 Multi Master on Chip On a System On Chip, Master can
More informationCortex-R5 Software Development
Cortex-R5 Software Development Course Description Cortex-R5 software development is a three days ARM official course. The course goes into great depth, and provides all necessary know-how to develop software
More informationMemory management units
Memory management units Memory management unit (MMU) translates addresses: CPU logical address memory management unit physical address main memory Computers as Components 1 Access time comparison Media
More informationDesigning with NXP i.mx8m SoC
Designing with NXP i.mx8m SoC Course Description Designing with NXP i.mx8m SoC is a 3 days deep dive training to the latest NXP application processor family. The first part of the course starts by overviewing
More informationComputer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2.
BASIC ELEMENTS Simplified view: Processor Slide 1 Computer System Overview Operating Systems Slide 3 Main Memory referred to as real memory or primary memory volatile modules 2004/S2 secondary memory devices
More informationPorting FreeBSD to AArch64
Porting FreeBSD to AArch64 Andrew Turner andrew@fubar.geek.nz 12 June 2015 About me Source committer focusing on ARM Freelance Software Engineer Status of arm64 (AArch64) Support to boot in QEMU committed
More informationEmbedded Systems: Architecture
Embedded Systems: Architecture Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu)
More informationShared Memory Multiprocessors. Symmetric Shared Memory Architecture (SMP) Cache Coherence. Cache Coherence Mechanism. Interconnection Network
Shared Memory Multis Processor Processor Processor i Processor n Symmetric Shared Memory Architecture (SMP) cache cache cache cache Interconnection Network Main Memory I/O System Cache Coherence Cache
More informationI/O Systems. Jo, Heeseung
I/O Systems Jo, Heeseung Today's Topics Device characteristics Block device vs. Character device Direct I/O vs. Memory-mapped I/O Polling vs. Interrupts Programmed I/O vs. DMA Blocking vs. Non-blocking
More informationHardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015
Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs August 2015 SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal Software DSP Software Bare Metal Software
More informationEmbedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi
Embedded Systems Dr. Santanu Chaudhury Department of Electrical Engineering Indian Institute of Technology, Delhi Lecture - 13 Virtual memory and memory management unit In the last class, we had discussed
More informationInput/Output. Today. Next. Principles of I/O hardware & software I/O software layers Disks. Protection & Security
Input/Output Today Principles of I/O hardware & software I/O software layers Disks Next Protection & Security Operating Systems and I/O Two key operating system goals Control I/O devices Provide a simple,
More informationComputer Architecture CS 355 Busses & I/O System
Computer Architecture CS 355 Busses & I/O System Text: Computer Organization & Design, Patterson & Hennessy Chapter 6.5-6.6 Objectives: During this class the student shall learn to: Describe the two basic
More informationARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or
More informationLinux Driver and Embedded Developer
Linux Driver and Embedded Developer Course Highlights The flagship training program from Veda Solutions, successfully being conducted from the past 10 years A comprehensive expert level course covering
More informationEarly Software Development Through Emulation for a Complex SoC
Early Software Development Through Emulation for a Complex SoC FTF-NET-F0204 Raghav U. Nayak Senior Validation Engineer A P R. 2 0 1 4 TM External Use Session Objectives After completing this session you
More informationSoftware Driven Verification at SoC Level. Perspec System Verifier Overview
Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015 IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to
More informationChapter 5 (Part II) Large and Fast: Exploiting Memory Hierarchy. Baback Izadi Division of Engineering Programs
Chapter 5 (Part II) Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Virtual Machines Host computer emulates guest operating system and machine resources Improved isolation of multiple
More informationMigrating RC3233x Software to the RC32434/5 Device
Migrating RC3233x Software to the RC32434/5 Device Application Note AN-445 Introduction By Harpinder Singh and Nebojsa Bjegovic Operating system kernels, board support packages, and other processor-aware
More informationZynq-7000 All Programmable SoC Product Overview
Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform
More information27 March 2018 Mikael Arguedas and Morgan Quigley
27 March 2018 Mikael Arguedas and Morgan Quigley Separate devices: (prototypes 0-3) Unified camera: (prototypes 4-5) Unified system: (prototypes 6+) USB3 USB Host USB3 USB2 USB3 USB Host PCIe root
More informationAn Overview of the BLITZ Computer Hardware
An Overview of the BLITZ Computer Hardware Introduction Harry H. Porter III Department of Computer Science Portland State University The BLITZ computer was designed solely to support the development of
More informationComputer System Overview
Computer System Overview Operating Systems 2005/S2 1 What are the objectives of an Operating System? 2 What are the objectives of an Operating System? convenience & abstraction the OS should facilitate
More informationAddress Translation. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
Address Translation Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics How to reduce the size of page tables? How to reduce the time for
More informationi.mx 7 - Hetereogenous Multiprocessing Architecture
i.mx 7 - Hetereogenous Multiprocessing Architecture Overview Toradex Innovative Business Model Independent Companies Direct Sales Publicly disclosed Sales Prices Local Warehouses In-house HW and SW Development
More informationMemory management. Requirements. Relocation: program loading. Terms. Relocation. Protection. Sharing. Logical organization. Physical organization
Requirements Relocation Memory management ability to change process image position Protection ability to avoid unwanted memory accesses Sharing ability to share memory portions among processes Logical
More informationHardware OS & OS- Application interface
CS 4410 Operating Systems Hardware OS & OS- Application interface Summer 2013 Cornell University 1 Today How my device becomes useful for the user? HW-OS interface Device controller Device driver Interrupts
More informationVT-d and FreeBSD. Константин Белоусов 21 сентября 2013 г. Revision : Константин Белоусов VT-d and FreeBSD
VT-d and FreeBSD Константин Белоусов kib@freebsd.org 21 сентября 2013 г. Revision : 1.12 PCIe Example PCI Express Topology Root & Switch CPU Bus CPU Root RCRB Bus 0 PCIe Root Complex PCIe PCIe Memory Virtual
More informationVirtual Memory. Reading. Sections 5.4, 5.5, 5.6, 5.8, 5.10 (2) Lecture notes from MKP and S. Yalamanchili
Virtual Memory Lecture notes from MKP and S. Yalamanchili Sections 5.4, 5.5, 5.6, 5.8, 5.10 Reading (2) 1 The Memory Hierarchy ALU registers Cache Memory Memory Memory Managed by the compiler Memory Managed
More informationMisc. Third Generation Batch Multiprogramming. Fourth Generation Time Sharing. Last Time Evolution of OSs
Third Generation Batch Multiprogramming Misc. Problem: but I/O still expensive; can happen in middle of job Idea: have a pool of ready jobs in memory, switch to one when another needs I/O When one job
More informationARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview
ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview M J Brockway January 25, 2016 UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All
More informationECE 598 Advanced Operating Systems Lecture 4
ECE 598 Advanced Operating Systems Lecture 4 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 28 January 2016 Announcements HW#1 was due HW#2 was posted, will be tricky Let me know
More informationCEC 450 Real-Time Systems
CEC 450 Real-Time Systems Lecture 10 Device Interface Drivers and MMIO October 29, 2015 Sam Siewert MMIO Interfacing to Off-Chip Devices Sam Siewert 2 Embedded I/O (HW View) Analog I/O DAC analog output:
More informationLecture 21: Virtual Memory. Spring 2018 Jason Tang
Lecture 21: Virtual Memory Spring 2018 Jason Tang 1 Topics Virtual addressing Page tables Translation lookaside buffer 2 Computer Organization Computer Processor Memory Devices Control Datapath Input Output
More information14 May 2012 Virtual Memory. Definition: A process is an instance of a running program
Virtual Memory (VM) Overview and motivation VM as tool for caching VM as tool for memory management VM as tool for memory protection Address translation 4 May 22 Virtual Memory Processes Definition: A
More informationEE108B Lecture 17 I/O Buses and Interfacing to CPU. Christos Kozyrakis Stanford University
EE108B Lecture 17 I/O Buses and Interfacing to CPU Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Remaining deliverables PA2.2. today HW4 on 3/13 Lab4 on 3/19
More informationARMv8-A Memory Systems. Systems. Version 0.1. Version 1.0. Copyright 2016 ARM Limited or its affiliates. All rights reserved.
Connect ARMv8-A User Memory Guide Systems Version 0.1 Version 1.0 Page 1 of 17 Revision Information The following revisions have been made to this User Guide. Date Issue Confidentiality Change 28 February
More informationFreescale i.mx6 Architecture
Freescale i.mx6 Architecture Course Description Freescale i.mx6 architecture is a 3 days Freescale official course. The course goes into great depth and provides all necessary know-how to develop software
More informationCortex-A15 MPCore Software Development
Cortex-A15 MPCore Software Development תיאור הקורס קורסDevelopment Cortex-A15 MPCore Software הינו הקורסהרשמי שלחברת ARM בן 4 ימים, מעמיקמאודומכסהאתכלהנושאיםהקשוריםבפיתוחתוכנה לפלטפורמותמבוססותליבתMPCore.Cortex-A15
More informationA Cache Hierarchy in a Computer System
A Cache Hierarchy in a Computer System Ideally one would desire an indefinitely large memory capacity such that any particular... word would be immediately available... We are... forced to recognize the
More informationArria V SX and ST SoC Errata
2015.07.14 Arria V SX and ST SoC Errata ES-1041 Subscribe This document lists the errata for the Arria V SX and ST SoC devices. Included in this document are the following errata: Altera -specific Arria
More informationInput-Output (I/O) Input - Output. I/O Devices. I/O Devices. I/O Devices. I/O Devices. operating system must control all I/O devices.
Input - Output Input-Output (I/O) operating system must control all I/O devices issue commands to devices catch interrupts handle errors provide interface between devices and rest of system main categories
More informationCISC RISC. Compiler. Compiler. Processor. Processor
Q1. Explain briefly the RISC design philosophy. Answer: RISC is a design philosophy aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed. The RISC
More informationVirtual Memory. 1 Administrivia. Tom Kelliher, CS 240. May. 1, Announcements. Homework, toolboxes due Friday. Assignment.
Virtual Memory Tom Kelliher, CS 240 May. 1, 2002 1 Administrivia Announcements Homework, toolboxes due Friday. Assignment From Last Time Introduction to caches. Outline 1. Virtual memory. 2. System support:
More informationSmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User s Guide
SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User s Guide SmartFusion2 SoC FPGA Demo: Code Shadowing from SPI Flash to SDR Memory User's Guide Table of Contents SmartFusion2
More informationLast class: Today: Course administration OS definition, some history. Background on Computer Architecture
1 Last class: Course administration OS definition, some history Today: Background on Computer Architecture 2 Canonical System Hardware CPU: Processor to perform computations Memory: Programs and data I/O
More informationLec 22: Interrupts. Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University. Announcements
Lec 22: Interrupts Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University HW 3 HW4: due this Friday Announcements PA 3 out Nov 14 th Due Nov 25 th (feel free to turn it in early) Demos and
More informationCSE 120 Principles of Operating Systems
CSE 120 Principles of Operating Systems Spring 2018 Lecture 10: Paging Geoffrey M. Voelker Lecture Overview Today we ll cover more paging mechanisms: Optimizations Managing page tables (space) Efficient
More informationProduct Technical Brief S3C2440X Series Rev 2.0, Oct. 2003
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003 S3C2440X is a derivative product of Samsung s S3C24XXX family of microprocessors for mobile communication market. The S3C2440X s main enhancement
More information1993 Paper 3 Question 6
993 Paper 3 Question 6 Describe the functionality you would expect to find in the file system directory service of a multi-user operating system. [0 marks] Describe two ways in which multiple names for
More information(Advanced) Computer Organization & Architechture. Prof. Dr. Hasan Hüseyin BALIK (3 rd Week)
+ (Advanced) Computer Organization & Architechture Prof. Dr. Hasan Hüseyin BALIK (3 rd Week) + Outline 2. The computer system 2.1 A Top-Level View of Computer Function and Interconnection 2.2 Cache Memory
More informationECE 411 Exam 1 Practice Problems
ECE 411 Exam 1 Practice Problems Topics Single-Cycle vs Multi-Cycle ISA Tradeoffs Performance Memory Hierarchy Caches (including interactions with VM) 1.) Suppose a single cycle design uses a clock period
More informationTrusted Firmware Deep Dive. Dan Handley Charles Garcia-Tobin
Trusted Firmware Deep Dive Dan Handley Charles Garcia-Tobin 1 Agenda Architecture overview Memory usage Code organisation Cold boot deep dive PSCI deep dive 2 Example System Architecture Normal World Secure
More informationVirtual Memory Nov 9, 2009"
Virtual Memory Nov 9, 2009" Administrivia" 2! 3! Motivations for Virtual Memory" Motivation #1: DRAM a Cache for Disk" SRAM" DRAM" Disk" 4! Levels in Memory Hierarchy" cache! virtual memory! CPU" regs"
More information64 bit Bare Metal Programming on RPI-3. Tristan Gingold
64 bit Bare Metal Programming on RPI-3 Tristan Gingold gingold@adacore.com What is Bare Metal? Images: Wikipedia No box What is Bare Metal? No Operating System Your application is the OS Why Bare Board?
More informationSMP Implementation for OpenBSD/sgi. Takuya
SMP Implementation for OpenBSD/sgi Takuya ASADA Introduction I was working to add SMP & 64bit support to a BSD-based embedded OS at The target device was MIPS64 There s no complete *BSD/MIPS
More informationEmbedded Linux kernel and driver development training 5-day session
Embedded Linux kernel and driver development training 5-day session Title Embedded Linux kernel and driver development training Overview Understanding the Linux kernel Developing Linux device drivers Linux
More informationArchitecture and OS. To do. q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure
Architecture and OS To do q Architecture impact on OS q OS impact on architecture q Next time: OS components and structure Computer architecture and OS OS is intimately tied to the hardware it runs on
More informationProduct Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
More informationSheevaPlug Development Kit Reference Design. Rev 1.2
SheevaPlug Development Kit Reference Design Rev 1.2 INTRODUCTION...4 SECTION 1 OVERVIEW...6 1.1 SHEEVAPLUG DESCRIPTION....6 Figure 1.1: SHEEVAPLUG Components and JTAG test card...6 Figure 1.2: SheevaPlug
More informationLinux Device Drivers: Case Study of a Storage Controller. Manolis Marazakis FORTH-ICS (CARV)
Linux Device Drivers: Case Study of a Storage Controller Manolis Marazakis FORTH-ICS (CARV) IOP348-based I/O Controller Programmable I/O Controller Continuous Data Protection: Versioning (snapshots), Migration,
More informationMEMORY MANAGEMENT UNITS
Memory Management Units memory management unit (MMU) simply converts a virtual address generated by a CPU into a physical address which is applied to the memory system address space divided into fixed
More informationSMP bring up on ARM SoCs
Embedded Linux Conference 2014 SMP bring up on ARM SoCs Gregory CLEMENT Bootlin gregory.clement@bootlin.com - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com
More informationLecture 29 Review" CPU time: the best metric" Be sure you understand CC, clock period" Common (and good) performance metrics"
Be sure you understand CC, clock period Lecture 29 Review Suggested reading: Everything Q1: D[8] = D[8] + RF[1] + RF[4] I[15]: Add R2, R1, R4 RF[1] = 4 I[16]: MOV R3, 8 RF[4] = 5 I[17]: Add R2, R2, R3
More informationComputer Architecture Computer Science & Engineering. Chapter 5. Memory Hierachy BK TP.HCM
Computer Architecture Computer Science & Engineering Chapter 5 Memory Hierachy Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic
More informationC02: Interrupts and I/O
CISC 7310X C02: Interrupts and I/O Hui Chen Department of Computer & Information Science CUNY Brooklyn College 2/8/2018 CUNY Brooklyn College 1 Von Neumann Computers Process and memory connected by a bus
More informationFPQ6 - MPC8313E implementation
Formation MPC8313E implementation: This course covers PowerQUICC II Pro MPC8313 - Processeurs PowerPC: NXP Power CPUs FPQ6 - MPC8313E implementation This course covers PowerQUICC II Pro MPC8313 Objectives
More informationArchitectural Support for Operating Systems
Architectural Support for Operating Systems Today Computer system overview Next time OS components & structure Computer architecture and OS OS is intimately tied to the hardware it runs on The OS design
More informationECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 3 September 2015 Announcements HW#1 will be posted today, due next Thursday. I will send out
More informationFujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02
Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC
More informationMemory Hierarchies 2009 DAT105
Memory Hierarchies Cache performance issues (5.1) Virtual memory (C.4) Cache performance improvement techniques (5.2) Hit-time improvement techniques Miss-rate improvement techniques Miss-penalty improvement
More informationFredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт.
SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University
More informationMemory Technology. Chapter 5. Principle of Locality. Chapter 5 Large and Fast: Exploiting Memory Hierarchy 1
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5 th Edition Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic
More informationARM Processors ARM ISA. ARM 1 in 1985 By 2001, more than 1 billion ARM processors shipped Widely used in many successful 32-bit embedded systems
ARM Processors ARM Microprocessor 1 ARM 1 in 1985 By 2001, more than 1 billion ARM processors shipped Widely used in many successful 32-bit embedded systems stems 1 2 ARM Design Philosophy hl h Low power
More information9/19/18. COS 318: Operating Systems. Overview. Important Times. Hardware of A Typical Computer. Today CPU. I/O bus. Network
Important Times COS 318: Operating Systems Overview Jaswinder Pal Singh and a Fabulous Course Staff Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) u Precepts:
More informationUC Santa Barbara. Operating Systems. Christopher Kruegel Department of Computer Science UC Santa Barbara
Operating Systems Christopher Kruegel Department of Computer Science http://www.cs.ucsb.edu/~chris/ Input and Output Input/Output Devices The OS is responsible for managing I/O devices Issue requests Manage
More informationChapter 5. Large and Fast: Exploiting Memory Hierarchy
Chapter 5 Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic disk 5ms 20ms, $0.20 $2 per
More informationPorting Nouveau to Tegra K1
Porting Nouveau to Tegra K1 How NVIDIA became a Nouveau contributor Alexandre Courbot, NVIDIA FOSDEM 2015 The Story So Far... In 2014 NVIDIA released the Tegra K1 SoC 32 bit quad-core or 64-bit dual core
More informationEITF20: Computer Architecture Part 5.2.1: IO and MultiProcessor
EITF20: Computer Architecture Part 5.2.1: IO and MultiProcessor Liang Liu liang.liu@eit.lth.se 1 Outline Reiteration I/O MultiProcessor Summary 2 Virtual memory benifits Using physical memory efficiently
More informationModeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces
Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces Li Chen, Staff AE Cadence China Agenda Performance Challenges Current Approaches Traffic Profiles Intro Traffic Profiles Implementation
More information