ECEU530. Homework 4 due Wednesday Oct 25. ECE U530 Digital Hardware Synthesis. VHDL for Synthesis with Xilinx. Schedule
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1 EEU530 EE U530 igital Hardware Synthesis Lecture 11: Prof. Miriam Leeser October 18, 2005 Sequential Logic in VHL Finite State Machines in VHL Project proposals due now HW 4 due Wednesday, October 25 Use the discussion board to post questions Homework 4 due Wednesday Oct 25 Write a testbench for the ALU from Homework 3 Write the MUX function from lecture 10 Write code that calls the MUX function EE U530 F06 2 Schedule Homework 4 due Wednesday, October 25 Review in class on Monday, October 30 Midterm in class on Wednesday, November 1 Homework 5: based on EEU323 Lab 4 ue Wednesday November 8 VHL for Synthesis with Xilinx ocumentation available from Xilinx: link on course web page (External Links) From the PF collection, we are interested in: Synthesis and Verification esign Guide XST Users Guide Some material in this lecture is from: XST Users Guide hapter 6 VHL language support: Sequential ircuits 3 4
2 EEU530 Sequential HW in VHL We will describe synchronous, sequential hardware in VHL Synchronous, sequential hardware is clocked flip-flops registers and shift registers counters state machines I can describe sequential hardware with sequential VHL statements concurrent VHL statements signal assignments same as combinational hardware ombinational Hardware in VHL Process has no wait statements or clock signals All signals on RHS of assignments appear in process sensitivity list Example of a good combinational HW description: A B process(a, B, ) variable : Std_Logic; if A='1' then := B; else := B or ; F <= ; F 5 6 Good ombinational Techniques All signals that effect result go in process sensity list Any signal assigned in one branch is assigned in all branches: of a case statement of if-then-else clause Use case statements (NOT nested if-then-else statements) to avoid inferring priority encoder Use don t cares to assign to outputs Never use don t cares in a comparison statement Sequential Logic when you don t want it You can write combinational VHL that synthesizes to sequential hardware that you did not intend No clock signal, no wait signal latches are synthesized If you use the VHL term unaffected Why? If you use the VHL term null Why? If you do NOT put the same assignment on every branch of your if--then--else or ASE statements Why? 7 8
3 EEU530 GOO If statement example signal A, B,, P1, P2, Y, Z: std_logic; process ( A, B,, P1, P2 ) Y <= 0 ; Z <= 1 ; if (P1 = 1 ) then Y <= A; elsif (P2 = 0 ) then Y <= B; else Z <= ; Null and Unaffected case opcode is when add => Acc1 <= Acc + operand; when subtract => Acc1 <= Acc - operand; when nop => null; end case; with sel select Z <= A when 0, Z <= B when 1, Z <= unaffected when others; 9 10 Sequential Logic when you want it Process statement with lock on sensitivity list or wait statement Wait statement or sensitivity list, never both locked, sequential hardware with sensitivity list o NOT put all signals on Right hand side on sensitivity list o put on sensitivity list clock plus any asynchronous inputs: lock, or lock and reset, or lock and set, or lock and reset and set 11 wait statements wait can be used to suspend a process for a specified time period Example: Using wait in a testbench: -- ********************************* -- process for simulating the clock process clk <= not(clk); wait for 20 ns; -- ********************************* an also wait on a signal or on an event wait until clk event wait until clk event and clk = 1 wait until clk event and clk = 0
4 EEU530 Process Simulation Process can have wait statement or sensitivity list, but not both If process has sensitivity list, process is executed once at simulation start up, and after that when a signal on the sensitivity list changes If process has has a wait statement, process is executed at simulation start up, until wait statement is executed, then it suspends Process wakes up when wait condition is met Sequential vs. ombinational HW ombinational ircuits Output depends on current values of inputs only No feedback No memory Sequential Hardware Feedback Output depends on current inputs and current state ircuit has memory elements Sequential Hardware = ombinational Hardware plus memory elements: latches, flipflops, memories Sequential Hardware in VHL Synchronous Only lock May or may not have a reset signal Sequential Hardware is defined with a particular style VHL synthesis tool looks for hardware described using that style, and translates it to flip-flops and combinational logic lock signal is special. Usually called LK 15 Latch in VHL -- _LATH.VH library IEEE; use IEEE.std_logic_1164.all; entity d_latch is port ( EN, ATA: in ST_LOGI; Q: out ST_LOGI); end d_latch; architecture BEHAV of d_latch is LATH: process (EN, ATA) if (EN = '1') then Q <= ATA; end BEHAV; 16
5 EEU530 -Flipflop library IEEE; use IEEE.std_logic_1164.all; entity d_ff is port ( LK, ATA: in ST_LOGI; Q: out ST_LOGI ); end d_ff; architecture BEHAV of d_ff is process (LK) if (LK'event and LK='1') then Q <= ATA; end BEHAV; -Flipflop with wait statement library IEEE; use IEEE.std_logic_1164.all; entity d_ff is port ( LK, ATA: in ST_LOGI; Q: out ST_LOGI ); end d_ff; architecture with_wait of d_ff is process wait until rising_edge(lk); Q <= ATA; end BEHAV; Edge etection Functions FUNTION rising_edge (SIGNAL s : std_logic) RETURN BOOLEAN IS BEGIN RETURN (s EVENT AN (s = 1 )); EN; FUNTION falling_edge (SIGNAL s : std_logic) RETURN BOOLEAN IS BEGIN RETURN (s'event AN s = 0 )); EN; IMPORTANT: Use these only with the clk signal -FF with Reset process (LK, RST) if RST = '1' then Q <= 0 ; elsif LK'EVENT and LK = '1' then Q <= ata; Asynchronous Set is similar 19 20
6 EEU530 -FF with lock Enable Not supported: wait until LOK'event and LOK = '0' and ENABLE = '1' ; Supported: wait until LOK'event and LOK = '0' ; if ENABLE = '1' then... process() if 'event and ='1' then -- or rising_edge() if ENABLE = '1' then Q <= ATA; -FF with Asynchronous Reset and Synchronous Enable process(rst, ) if Rst = '0' then Q <= '0'; elsif rising_edge() then if EN = 1 then Q <= ; locked Flip-flop Active Low Reset on a FF Q Q Q Q process() if rising_edge() then Q <= ; -- or -- process wait until rising_edge(lk); Q <= ; end process Rst R process(rst, ) if Rst = '0' then Q <= '0'; elsif rising_edge() then Q <= ; Active low 23 24
7 EEU530 (7 downto 0) Q(7 downto 0) Register (Eight-bit) (7) (6) (5) (4) (3) (2) (1) (0) process() if rising_edge() then Q <= ; This register has no reset 25 Q(7) Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) 8 bit register entity EXAMPLE is port (I : in ST_LOGI_VETOR (7 downto 0); LK : in ST_LOGI; O : out ST_LOGI_VETOR (7 downto 0)); end EXAMPLE; architecture ARH1 of EXAMPLE is process (LK) if LK'EVENT and LK = '1' then O <= I ; end ARH1; architecture ARH2 of EXAMPLE is process wait until LK'EVENT and LK = '1'; O <= I; end ARH2; 26 8 bit register with reset entity EXAMPLE is port ( I : in ST_LOGI_VETOR (7 downto 0); LK : in ST_LOGI; RST : in ST_LOGI; O : out ST_LOGI_VETOR (7 downto 0) ); end EXAMPLE; architecture ARHI of EXAMPLE is process (LK, RST) if RST = '1' then O <= " "; elsif LK'EVENT and LK = '1' then O <= I ; end ARHI; Shift Register (Eight-bit) Ser_In Q(7 downto 0) process() if rising_edge() then Q <= Q(6 downto 0) & Ser_In; 27 28
8 EEU530 Parallel-In/Serial-Out Shift Register (Eight-bit) signal :Std_Logic_Vector(7 downto 0); ount Binary ounter (Eight-bit) Q(7 downto 0) Ser_Out <= Q(7); process() if rising_edge() then if Load = '0' then Q <= ; else Q <= Q(6 downto 0) & '0'; Load Ser_Out " " + Q(7 downto 0) process() ount if rising_edge() then if ount = '1' then Q <= Q + 1; Note: The VHL shown must have a function "+" defined to be complete ounter with Asynchronous Reset What hardware gets inferred? entity EXAMPLE is port (LK : in ST_LOGI; RST : in ST_LOGI; O : out ST_LOGI_VETOR (7 downto 0) ); end EXAMPLE; architecture ARHI of EXAMPLE is process (LK, RST) variable OUNT : ST_LOGI_VETOR (7 downto 0); if RST = '1' then OUNT := " "; elsif LK'EVENT and LK = '1' then OUNT := OUNT + " "; O <= OUNT; end ARHI; <= A and B; <= not ; process() if rising_edge() then Q_r <= ; A B Q Q_r 31 32
9 EEU530 What hardware gets inferred? process() if rising_edge() then <= A and B; <= not ; Q_r <= ; A B 33 Q clk Q clk Q clk Q_r A B Q A B SAs with Processes (one flip-flop) 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns Q Q_r <= A and B after 5 ns; <= not after 10 ns; process() if rising_edge() then Q_r <= ; 34 SAs with Processes (multiple flip-flops) A B A_r Q B_r 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns B A Q Q A_r B_r Q Q_r <= A_r and B_r after 5 ns; <= not after 10 ns; process() if rising_edge() then Q_r <= ; A_r <= A; B_r <= B; 35 36
10 EEU Latches Flip-Flops Registers Shift registers ounters Sequential Hardware Finite state machines 39 40
11 EEU530 Sequential Hardware Model Finite State Machine Input Present State Variables omb kt Memory Feedback Outputs Next State Variables Inputs Next state logic State register This is a Moore machine Outputs depend on current state only Output Logic Outputs Finite State Machine State Machine iagram State Name Inputs Next state logic State register Output Logic Outputs State0 Out1<= 0 Out2<= 1 Moore Machine Outputs Moore machine: outputs depend on current state only Mealy machine: outputs depend on current state and inputs Asynch reset will be shown once In1= 0 and In2= 1 Reset ondition to transition between states 43 44
12 EEU530 Example: Stop Watch 1 State iagram Inputs: Start_stop, Reset Outputs: ount enable: advance time lear: reset time START_STOP E RESET STOPWATH LEAR ounter and isplay To escribe an FSM in VHL Next state function Output function State register to store current state Each can be its own process Which processes are combinational? Which processes are sequential? FSM escription in VHL architecture FSM of EMO is type STATE_TYPE is ( ); signal URRENT_STATE, NEXT_STATE : STATE_TYPE; STATE_REG: process(lk, RESET)... NEXT_STATE_LOGI: process(urrent_state, <inputs>)... OUTPUT_LOGI: process(urrent_state)... end FSM; 47 48
13 EEU530 Stopwatch FSM Entity library IEEE; use IEEE.std_logic_1164.all; entity STOPWATH is port( LK, RESET, START_STOP: in std_logic; E, LEAR: out std_logic); end STOPWATH; START_STOP E efining States architecture FSM of STOPWATH is type STATE_TYPE is (ZERO, START, OUNT, STOP, STOPPE); end FSM; RESET STOPWATH LEAR ounter and isplay State Register is only Sequential Part architecture FSM of STOPWATH_TRL is type STATE_TYPE is (ZERO, START, OUNT, STOP, STOPPE); signal URRENT_STATE, NEXT_STATE : STATE_TYPE; STATE_REG: process(lk, RESET) if (RESET = '0') then URRENT_STATE <= ZERO; elsif (rising_edge(lk)) then URRENT_STATE <= NEXT_STATE;... end FSM; Next State Logic NS_LOGI: process (URRENT_STATE, START_STOP) case URRENT_STATE is when ZERO => if(start_stop = '1')then NEXT_STATE <= START; else NEXT_STATE <= ZERO; when START => if(start_stop = '1')then NEXT_STATE <= START; else NEXT_STATE <= OUNT; when OUNT => if(start_stop = '1')then NEXT_STATE <= STOP; else NEXT_STATE <= OUNT; 51 52
14 EEU530 Next State Logic (cont d) when STOP => if(start_stop = '1')then NEXT_STATE <= STOP; else NEXT_STATE <= STOPPE; when STOPPE => if(start_stop = '1')then NEXT_STATE <= START; else NEXT_STATE <= STOPPE; when others => NEXT_STATE <= ZERO; end case; Output Logic OUTPUT_LOGI: process(urrent_state) case URRENT_STATE is when ZERO => E <= '0'; LEAR <= '1'; when START => E <= '1'; LEAR <= '0'; when OUNT => E <= '1'; LEAR <= '0'; when STOP => E <= '0'; LEAR <= '0'; when STOPPE => E <= '0'; LEAR <= '0'; when others => E <= '0'; LEAR <= '1'; end case; To escribe FSM in VHL reate an enumerated type for states Three processes for behavior of FSM 1. clocked process for state register 2. combinational process for next state logic sensitivity list : inputs and current state 3. combination process for outputs Moore Machine: sensitivity list: current state Mealy Machine: sensitivity list: current state and inputs Where does reset go? 55 56
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