Department of Computer Science Duke University Ph.D. Qualifying Exam. Computer Architecture 180 minutes

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1 Department of Computer Science Duke University Ph.D. Qualifying Exam Name: Computer Architecture 180 minutes Not all questions are equally difficult. Look at entire exam. Budget time carefully. Please carefully state any assumptions you make. Please write your name on every page in the exam. Signing Academic Policy: Question 1 Question 2 Question 3 Question 4 Question 5 5 pts 15pts 20pts 25pts 20pts 15pts Academic Policy: University policy as codified by the Duke Undergraduate Honor Code will be strictly enforced. Zero tolerance for cheating or plagiarism. If a student is suspected of academic dishonesty, faculty are required to report the matter to the Office of Student Conduct. A student found responsible for academic dishonesty faces formal disciplinary actions, which may include suspension. A student suspended twice for academic dishonesty automatically faces a minimum 5-year separation from Duke University. I have read and understood the academic policy. (signature)

2 Question 1. Caches [ / 5 ] (a) A two-way set associative cache. Capacity is 64B and block size is 16B. Addresses are 8 bits. For each address, complete the entry in the table. Upon completion, the table should (i) (ii) (iii) show how the address is split into tag, index, and offset (i.e., bit strings for each field) show the contents of the cache (i.e., the last address accessed in each way). state the outcome (i.e., whether the cache access produced a hit or miss). Assume an LRU replacement policy. Way 0 should contain the least recently used set (LRU) and Way 1 should contain the most recently used set (MRU) at any given time. The first two entries have been completed for you but we omit the tag, index, and offset. Please complete all entries for every following address. Note addresses are presented in hexadecimal. Set 0 Set 1 Address Tag Index Offset Way 0 Way 1 Way 0 Way 1 Outcome (start) (omitted) (empty) (empty) (empty) (empty) -- CF (omitted) (empty) CF (empty) (empty) M D8 (omitted) (empty) CF (empty) D8 M CE (empty) CF (empty) D8 H (empty) CE D8 10 M F (empty) CE 10 F0 M E CE E8 10 F0 M C E8 C6 10 F0 H (b) What type of locality benefits from increasing the block size? What type of locality benefits from increasing associativity? Spatial locality benefits from increasing the block size. Temporal locality benefits from increasing associativity.

3 Question 2. Virtual Memory [ / 5 / 10] Suppose an architecture uses a 32-bit virtual address. The machine that encloses the processor supplies 1GB of physical memory. The operating system uses 4KB pages. (a) How many virtual pages are there in the address space? How many physical pages? (b) How many bits are there in the virtual page number? How many in the physical page number? (c) Fill in the blanks, according to the prompts shown. Page faults occur when a page table entry cannot be found in (i). The (ii) responds by choosing a (iii) to replace and reading the (iv) from disk. (i) (which virtual memory structure) (ii) (which hardware or software entity) (iii) (what measure of data) (iv) (what measure of data)

4 Question 3. Instruction-Level Parallelism [ / 5 / 5 / 5 / 5] (a) Show a MIPS instruction sequence that would cause a data hazard in a five-stage pipeline. (b) Fill in the blanks by choosing the correct word from the two choices. Pipelining is a performance optimization that takes a datapath and reduces the clock (i), increases the clock (ii), and (iii) increases instruction (iii). (i) (frequency or period) (ii) (frequency or period) (iii) (latency or throughput) (c) Why role does register renaming play in an out-of-order processor? Show a MIPS instruction sequence that benefits from renaming.

5 (d) What structure supports precise exceptions in an implementation of Tomasulo s algorithm? (e) The figure below shows percentage of issue cycles occupied with instructions and delays (e.g., branch mispredictions, cache misses). How does simultaneous multi-threading (SMT) increase utilization when the datapath is idled by these delays? Why might SMT be preferred instead of simply reducing superscalar width?

6 Question 4. Performance Analysis [ / 5 / 5 / 5] 1. What is Amdahl s Law? Write down the equation and explain in words why computer architects care about it. 2. The computer architect has two options for reducing power. First, reduce clock frequency from 3GHz to 1.5GHz. Second, decrease voltage from 1.2 to 1.0V. How much power is saved in each strategy? 3. People often confuse Moore s Law for exponential increases in processor performance. What did Moore say originally? Describe in words (no equations necessary) the relationship between Moore s Law and Dennard scaling. 4. Pipelining was a popular technique for improving performance in the late 1990s. But it encountered higher overheads and diminishing returns in performance. What is the source of overheads when a processor datapath is broken into more and more pipeline stages?

7 Question 5. Assorted Questions [ / 5 / 5] (a) Why are DRAM reads destructive? (b) How does the controller for direct memory access (DMA) notify the processor when it completes a large data transfer from disk to main memory? (c) What is the difference between a snoopy implementation of a coherence protocol and a directory implementation of the same protocol? Why would you prefer one versus the other?

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