ECE473 Computer Architecture and Organization. Processor: Combined Datapath
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1 Computer Architecture and Organization Processor: Combined path Lecturer: Prof. Yifeng Zhu Fall, 2014 Portions of these slides are derived from: Dave Patterson CB 1
2 Where are we? Want to build a processor for the IPS instruction subset: emory reference (lw, sw), Arithmetic-logical (add, sub, and, or, slt), and Branch (beq, j) Last class we looked at simplified datapath for each subset Today we review them in similar fashion and begin to put together a datapath for all three subsets Coming next: Corresponding control unit design To read along, see Sections 5.3 and 5.4 2
3 Simple Implementation Include the functional units we need for each instruction address emwrite memory PC Add a. memory b. Program counter c. Adder Sum Address Write data Read data memory Sign extend emread Register numbers Read register 1 Read register 2 Write register Write Registers Read data 1 Read data 2 4 operation Zero result a. memory unit b. Sign-extension unit Why do we need this stuff? RegWrite a. Registers b. 3
4 RTL Code for IPS add 1. Fetch = RO[PC], PC=PC+4 2. Read Operands 3. Add Op1 = Registers[rs-value], Op2 = Registers[rt-value] Out = Op1+Op2 4. Write Result Registers[rd-value] = Out 4
5 path Connections for IPS add add R1, R2, R3 P C address Inst. R1 R2 R3 add WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 CLK 5
6 path Connections for IPS add add R1, R2, R3 P C address Inst. R1 R2 R3 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 add CLK Interconnections 6
7 Critical Path for IPS add add R1, R2, R3 P C address Inst. R1 R2 R3 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 add CLK Interconnections Critical path 7
8 path Components for IPS lw/sw lw R1, -100(R2) sw R1, -100(R2) P C address RO Inst. R1 R2-100 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 emory lw/sw REGISTERS Address In Out SIGN-ETEND RA emory 8
9 Connections for lw lw R1, -100(R2) P C address RO Inst. R1 R2-100 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 emory lw REGISTERS SIGN-ETEND Address Out In RA emory 9
10 Critical Path for lw lw R1, -100(R2) P C address RO Inst. emory R1 (rt) R2 (rs) (Imm) -100 lw WriteRegister Port#1 ReadRegister#1 Port#2 ReadRegister#2 REGISTERS SIGN-ETEND Address Out In RA emory 10
11 Connections for sw sw R1, -100(R2) P C address RO Inst. R1 R2-100 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 emory sw REGISTERS SIGN-ETEND Address Out In RA emory 11
12 Critical Path for sw sw R1, -100(R2) P C address RO Inst. R1 R2-100 WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 emory sw REGISTERS SIGN-ETEND Address Out In RA emory 12
13 path Connections for IPS add and lw add R1, R2, R3 CLK P C address Inst. R1 R2 R3 add WriteRegister Port#1 ReadRegister#1 ReadRegister#2 Port#2 lw R1, -100(R2) P C address Inst. emory R1 R2-100 lw WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 SIGN-ETEND Addres s Out In RA emory 13
14 path Connections for IPS add and lw P C address Inst. emory R1 R2-100 lw WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 NEED SIGN-ETEND Addres s Out In RA emory 14
15 Combined path: R-Type and Load/Store s RN1 RN2 WN 1 Register File Operation 3 Zero 2 RegWrite E T N D Src emwrite e mory emread emtoreg 15
16 Combined path: Executing and R-Type add rd,rs,rt RN1 RN2 WN 1 Register File Operation 3 Zero 2 RegWrite E T N D Src emwrite e mory emread emtoreg
17 Combined path: Executing a load instruction lw rt,offset(rs) RN1 RN2 WN 1 Register File Operation 3 Zero 2 RegWrite E T N D Src emwrite e mory emread emtoreg 17
18 Combined path: Executing a store instruction sw rt,offset(rs) RN1 RN2 WN 1 Register File Operation 3 Zero 2 RegWrite E T N D Src emwrite e mory emread emtoreg 18
19 path Components for IPS beq beq $R1, $R2, -100 if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4 P C address RO Inst. emory R1 R2-100 beq WriteRegister Port#1 ReadRegister#1 Port#2 ReadRegister#2 REGISTERS zero SHIFT LEFT 2 SIGN-ETEND 19
20 path Connections for IPS beq beq $R1, $R2, -100 if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4 P C address RO Inst. emory R1 R2-100 beq WriteRegister ReadRegister#1 ReadRegister#2 Port#1 Port#2 REGISTERS PC+4 zero To branch Control SHIFT LEFT 2 SIGN-ETEND 20
21 Complete Single-Cycle path 4 PC emory 5 5 RN1 RN2 WN 1 Register File 5 <<2 Operation 3 Zero PCSrc RegWrite 2 E T N D Src emwrite emory emread emtoreg 21
22 Complete path Executing add 4 PC emory 5 5 RN1 RN2 WN 1 Register File 5 <<2 Operation 3 Zero PCSrc add rd, rs, rt RegWrite 2 E T N D Src emwrite emory emread emtoreg 22
23 Complete path Executing load 4 PC emory 5 5 RN1 RN2 WN 1 Register File 5 <<2 Operation 3 Zero PCSrc lw rt,offset(rs) RegWrite 2 E T N D Src emwrite emory emread emtoreg 23
24 Complete path Executing store 4 PC emory 5 5 RN1 RN2 WN 1 Register File 5 <<2 Operation 3 Zero PCSrc sw rt,offset(rs) RegWrite 2 E T N D Src emwrite emory emread emtoreg 24
25 Complete path Executing branch 4 PC emory 5 5 RN1 RN2 WN 1 Register File 5 <<2 Operation 3 Zero PCSrc beq r1,r2,offset RegWrite 2 E T N D Src emwrite emory emread emtoreg 25
26 Refining the Complete path Depending on the instruction, register file input WN is fed by different fields of the instruction R-Type s: rd field (bits 15:11) Load Instructin: rt field (bits 21:) Result: need an additional multiplexer on WN input 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct 6 bits 5 bits 5 bits bits op rs rt offset R-Format I-Format 26
27 Complete path (Refined) PC 4 emory immediate/ offset I[15:0] rs I[25:21] I rt I[21:] 5 5 RN1 RN2 WN 1 Register File Reg Write 5 2 E T N D rd I[15:11] 5 RegDst Sr c <<2 Oper ation 3 Zero PCSrc em Write emory em Read em toreg 27
28 Complete Single-Cycle path PC 4 emory immediate/ off set I[1 5:0] Control signals shown in blue I rs I[25:21] rt I[20:] 5 5 RN1 RN2 WN 1 Register File RegWrite 0 rd I[15:11] E T N D RegDst 0 1 Sr c <<2 Oper ation 3 Zero 0 1 PCSrc em Write emory em Read em toreg
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