EEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
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1 EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2
2 An Abstract View of the Implementation Ideal Address Net Address PC 5 Rs 5 Rw Ra 5 Rb -bit A B Signals Conditions path Address In Ideal Out Lec 3.3 Recap: A Single Cycle path We have everything ecept control signals (underline) RegDst Rs RegWr imm -bit npc_sel Etender EtOp Src Fetch Unit ctr In <3:> Zero <2:25> Rs <:2> MemWr <:5> <:5> Imm MemtoReg Lec 3.4
3 Recap: Meaning of the Signals npc_mux_sel: PC < PC + 4 PC < PC SignEt(Im) npc_mux_sel 4 Adr Inst imm PC Et Adder Adder PC Lec 3.5 Recap: Meaning of the Signals EtOp: zero, sign src: regb; immed ctr: add, sub, or MemWr: MemtoReg: RegDst: RegWr: write memory ; Mem rt ; rd write register RegDst Equal RegWr 5 Rs 5 5 -bit imm Etender ctr = MemWr In MemtoReg EtOp Src Lec 3.
4 RTL: The Add op rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the net instruction s address Lec 3.7 Fetch Unit at the Beginning of Add Fetch the instruction from memory: <- mem[pc] Same for all instructions Inst Adr <3:> npc_mux_sel 4 Adder imm Adder PC Lec 3.8
5 The Single Cycle path During Add R[rd] <- R[rs] + R[rt] RegDst = Rs RegWr = imm -bit Etender EtOp = npc_sel= +4 ctr = Add Src= Fetch Unit In <3:> Zero <2:25> Rs <:2> MemWr= <:5> <:5> Imm MemtoReg = Lec 3.9 Fetch Unit at the End of Add PC <- PC + 4 This is the same for all instructions ecept: Branch and Jump Inst Adr <3:> npc_mux_sel 4 Adder PC imm Adder Lec 3.
6 The Single Cycle path During Or Immediate R[rt] <- R[rs] or ZeroEt[Imm] RegDst = Rs RegWr = imm -bit npc_sel = Etender ctr = Src = Fetch Unit In <3:> Zero <2:25> Rs <:2> MemWr = <:5> <:5> Imm MemtoReg = EtOp = Lec 3. The Single Cycle path During Or Immediate RegDst = RegWr = Rs imm -bit Etender EtOp = npc_sel= +4 ctr = Or Src = Fetch Unit In <3:> <2:25> <:2> <:5> <:5> Rs Imm MemtoReg = Zero MemWr = Lec 3.2
7 The Single Cycle path During Load R[rt] <- [ R[rs] + SignEt[imm] ] RegDst = Rs RegWr = imm -bit Etender EtOp = npc_sel= +4 ctr=add Src = Fetch Unit In <3:> Zero <2:25> Rs <:2> MemWr = <:5> Imm MemtoReg = <:5> Lec 3.3 The Single Cycle path During Store [ R[rs] + SignEt[imm] ] <- R[rt] RegDst = Rs RegWr = imm -bit npc_sel = Etender EtOp = ctr = Src = Fetch Unit In <3:> Zero <2:25> Rs <:2> MemWr = <:5> <:5> Imm MemtoReg = Lec 3.4
8 The Single Cycle path During Store RegDst = Rs RegWr = imm -bit Etender EtOp = npc_sel= +4 ctr= Add Fetch Unit Src = In <3:> Zero <2:25> Rs <:2> MemWr = <:5> <:5> Imm MemtoReg = Lec 3.5 The Single Cycle path During Branch if (R[rs] - R[rt] == ) then Zero <- ; else Zero <- RegDst = Rs RegWr = imm -bit npc_sel= Br Etender ctr= Sub Src = Fetch Unit In <3:> <2:25> <:2> <:5> <:5> Rs Imm MemtoReg = Zero MemWr = EtOp = Lec 3.
9 Fetch Unit at the End of Branch npc_sel Inst Adr <3:> Zero npc_mux_sel What is encoding of npc_sel? imm 4 Adder Adder PC Direct MUX select? Branch / not branch npc_sel zero? MUX Lec 3.7 Step 4: Given path: RTL -> <3:> Inst Adr Op <2:25> <2:25> Fun <:5> <:5> <:2> Rs Imm npc_sel RegWr RegDstEtOpSrcctr MemWr MemtoReg Zero DATA PATH Lec 3.8
10 Summary of Signals inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 src = RegB, ctr = add, RegDst = rd, RegWr, npc_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 src = RegB, ctr = sub, RegDst = rd, RegWr, npc_sel = +4 ORi R[rt] < R[rs] + zero_et(imm); PC < PC + 4 src = Im, Etop = Z, ctr = or, RegDst = rt, RegWr, npc_sel = +4 LOAD R[rt] < MEM[ R[rs] + sign_et(imm)]; PC < PC + 4 src = Im, Etop = Sn, ctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_et(imm)] < R[rt]; PC < PC + 4 src = Im, Etop = Sn, ctr = add, MemWr, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < [PC + sign_et(imm)] else PC < PC + 4 npc_sel = Br, ctr = sub Lec 3.9 Summary of the Signals See We Don t Care :-) Appendi A op add sub ori lw sw beq RegDst Src MemtoReg RegWrite MemWrite npcsel EtOp ctr<2:> Add Sub Or Add Add Sub Lec 3.2
11 Concept of Local Decoding op R-type ori lw sw beq RegDst Src MemtoReg RegWrite MemWrite Branch EtO p op<n:> R-type Or Add Add Sub op Main op N (Local) ctr 3 Lec 3.2 Encoding of op op Main op N (Local) ctr 3 In this eercise, op has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, op has to be 3 bits to represent: () R-type instructions I-type instructions that require the to perform: - (2) Or, (3) Add, (4) Subtract, (5) And, and () Xor R-type ori lw sw beq op (Symbolic) R-type Or Add Add Sub op<2:> Lec 3.22
12 Decoding of the Field op Main op N (Local) ctr 3 R-type ori lw sw beq op (Symbolic) R-type Or Add Add Sub op<2:> R-type op rs rt rd shamt t t<5:> Operation add subtract and or set-on-less-than ctr ctr<2:> Operation And Or Add Subtract Set-on-less-than Lec 3.23 Truth Table for ctr op R-type ori lw sw beq (Symbolic) R-type Or Add Add Sub op<2:> t<3:> Op. add subtract and or set-on-less-than op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> Operation ctr bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on < Lec 3.24
13 Logic Equation for ctr<2> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<2> This makes <3> a don t care ctr<2> =!op<2> & op<> + op<2> &!<2> & <> &!<> Lec 3.25 Logic Equation for ctr<> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> ctr<> =!op<2> &!op<> +!op<2> & op<> + op<2> &!<2> &!<> Lec 3.2
14 Logic Equation for ctr<> op bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> ctr<> =!op<2> & op<> + op<2> &!<3> & <2> &!<> & <> + op<2> & <3> &!<2> & <> &!<> Lec 3.27 Block op 3 (Local) ctr 3 ctr<2> =!op<2> & op<> + op<2> &!<2> & <> &!<> ctr<> =!op<2> &!op<> +!op<2> & op<> op<2> &!<2> &!<> ctr<> =!op<2> & op<> + op<2> &!<3> & <2> &!<> & <> + op<2> & <3> &!<2> & <> &!<> Lec 3.28
15 Step 5: Logic For Each Signal npc_sel <= if (OP == BEQ) then Br else +4 src ctr EtOp MemWr <= if (OP == ype ) then regb else immed <= if (OP == ype ) then t elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add <= <= MemtoReg <= RegWr: RegDst: <= <= Lec 3.29 Step 5: Logic for Each Signal npc_sel <= if (OP == BEQ) then Br else +4 src ctr EtOp MemWr <= if (OP == ype ) then regb else immed <= if (OP == ype ) then t elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add <= if (OP == ORi) then zero else sign <= (OP == Store) MemtoReg <= (OP == Load) RegWr: <= if ((OP == Store) (OP == BEQ)) then else RegDst: <= if ((OP == Load) (OP == ORi)) then else Lec 3.3
16 Truth Table for the Main op Main RegDst Src : op 3 (Local) ctr 3 RegDst Src MemtoReg RegWrite MemWrite npc_sel op R-type ori lw sw beq EtOp op (Symbolic) R-type Or Add Add Subtract op <2> op <> op <> Lec 3.3 Truth Table for RegWrite op RegWrite = R-type + ori + lw R-type ori lw sw beq RegWrite =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> R-type ori lw sw beq RegWrite Lec 3.
17 PLA Implementation of the Main op<5>. op<5>. op<5>. op<5>. op<5>.. <>. <>. <>. <>. <> R-type ori lw sw beq RegWrite Src RegDst MemtoReg MemWrite Branch EtOp op<2> op<> op<> Lec 3.33 Putting it All Together: A Single Cycle Processor Instr<3:2> op RegDst Rs RegWr Main imm Instr<5:> -bit op RegDst Src : Etender 3 npc_sel Instr<5:> Src Fetch Unit ctr In Zero <3:> <2:25> Rs <:2> MemWr ctr <:5> 3 <:5> Imm MemtoReg EtOp Lec 3.34
18 Recap: An Abstract View of the Critical Path (Load) Address Net Address Ideal PC 5 Rs 5 Rw Ra 5 Rb -bit Imm A B Critical Path (Load Operation) = PC s -to-q + s Access Time + Register File s Access Time + to Perform a -bit Add + Access Time + Setup Time for Register File Write + Clock Skew Address In Ideal Lec 3.35 Worst Case Timing (Load) PC Rs,,, Op, Func ctr Old Value -to-q New Value Old Value Old Value Access Time New Value Delay through Logic New Value EtOp Old Value New Value Src Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value Old Value Delay through Etender & Old Value Register Write Occurs Register File Access Time New Value New Value Delay Address Old Value New Value Access Time Old Value New Lec 3.3
19 Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Access Time + Register File Access Time + Delay (address calculation) + Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions Lec 3.37 Summary Single cycle datapath => CPI=, CCT => long 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic is the hard part MIPS makes control easier s same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Processor path Input Output Lec 3.38
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