Chapter 4. The Processor. Computer Architecture and IC Design Lab
|
|
- Josephine Doyle
- 6 years ago
- Views:
Transcription
1 Chapter 4 The Processor
2 Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version (Single cycle implementation) A more realistic pipelined version Multi cycle version is removed in this version) Implement simple subset, but shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j CPU Time Instruction Count 4. Introduction 3
3 Review: MIPS Instruction Set Architecture (ISA) Instruction Categories Arithmetic Load/Store Jump and Branch Floating Point coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R R3 PC HI LO OP OP OP rs rt rd sa funct rs rt immediate jump target R format I format J format 4
4 Review: MIPS Register Convention Name Register Number Usage Preserve on call? $zero constant (hardware) n.a. $at reserved for assembler n.a. $v - $v 2-3 returned values no $a - $a3 4-7 arguments yes $t - $t7 8-5 temporaries no $s - $s saved values yes $t8 - $t temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 3 frame pointer yes $ra 3 return addr (hardware) yes
5 Instruction Execution PC (Program counter) is used to fetch instruction in the instruction memory) After instruction is obtained, register numbers in instructions is used to read registers in register files. PC PC +4 for sequentially execution 6
6 Different actions for different instruction classes Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address add $t, $s, $s2 lw $s, 2($s2) bne $t, $s5, Exit lw $s, 2($s2) j Loop 7
7 Multiplexers Can t just join wires together Use multiplexers 8
8 CPU Overview We need three Muxes to avoid problems Details of each Mux and Control will be introduced later 9
9 Logic Design Basics Information encoded in binary Low voltage =, High voltage = One wire per bit Multi bit data encoded on multi wire buses 4.2 Logic Design Conventions Combinational element (See next slide) Operate on data Output is a function of input State (sequential) elements 32 bit bus Output is a function of input and current states Store information
10 Review: Combinational Elements AND gate Y = A & B Adder Y = A + B A B + Y A B Multiplexer I I M u x S Y Y = S? I : I Y Arithmetic/Logic Unit Y = F(A, B) A ALU Y B F
11 Review: Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge triggered: update when Clk changes ( > or > ) The following figure is positive edge triggered: update when Clk changes from to D Clk Q Clk D Q 2
12 Review: Sequential Elements (with write enable) Register with write control Only updates on clock edge when write control input is Used when stored value is required later Clk D Write Clk Q Write D Q Q is not changed when Write= 3
13 Building a Datapath Datapath : Elements that process data and addresses in the CPU Registers, ALUs, mux s, memories, 4.3 Building a Datapath We will show how to build MIPS datapath 5
14 Instruction Fetch 32 bit register Increment by 4 for next instruction 6
15 Read two register operands Perform arithmetic/logical operation Write results into destination registers add $t, $s, $s2 R Format Instructions Instruction $s $s2 $t Read register Read register 2 Registers Write register Write data Read data Read data 2 3 ALU operation Zero ALU ALU result RegWrite 7
16 Load/Store Instructions (need 4 components) Read register operands =>register files Calculate address using 6 bit offset Use ALU, but sign extend offset Load/store: read memory and update register, and write register value to memory Need data memory lw $t, 4($s3) #load word from memory sw $t, 8($s3) #store word to memory 2
17 Load/store Datapath: Load/Store Instruction Instruction Read register Read register 2 Registers Write register Write data RegWrite Read data Read data 2 3 ALU operation Zero ALU ALU result Address Write data MemWrite Data memory Read data 6 Sign 32 extend MemRead Datapath Two additional elements (sign extension and data memory) used To implement load/stores 2
18 Load e.g. lw $t, 4($s3) Animating the Datapath load op rs rt offset/immediate WD 5 5 RN RN2 WN RD Register File RegWrite 5 RD2 E T N D 6 32 RN: register number RN2: register number 2 WN: register number that will be written WD: write data 6 Operation 3 ALU lw rt, offset(rs) R[rt] <- MEM[R[rs] + s_extend(offset)]; 4 Zero MemWrite ADDR Memory WD MemRead RD 22
19 store Animating the Datapath store sw $t, 8($s3) op rs rt offset/immediate WD 5 5 RN RN2 WN RD Register File RegWrite 5 RD2 6 E T N D 32 6 Operation 3 ALU sw rt, offset(rs) MEM[R[rs] + sign_extend(offset)] <- R[rt] Zero MemWrite ADDR Memory WD MemRead RD 23
20 Review: Specifying Branch Destinations MIPS conditional branch instructions: op rs rt offset 6 bits 5 bits 5 bits 6 bits PC relative addressing Target address = PC + offset 4 PC already incremented by 4 by this time from the low order 6 bits of the branch instruction sign extend PC 32 6 offset Add Add 32 2 beq $s $t C Target Address (address of next instruction) =? Each word is 4 bytes? 2C branch dst address 24
21 Read register operands Compare operands Use ALU, subtract and check Zero output Calculate target address Sign extend offset Shift left 2 bits (word displacement) Add to PC + 4 (already calculated by instruction fetch) Datapath: Branch Instructions See animation in the next slide 25
22 beq Animating the Datapath (beq) e.g. beq $s $t 2 op rs rt offset/immediate 6 PC +4 from instruction datapath ADD WD 5 5 RN RN2 WN RD Register File Operation ALU Zero <<2 RegWrite RD2 6 E T N D 32 beq rs, rt, offset if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2) 26
23 Sign extension and shift left by 2 hardware Simple hardware is used for sign extension and shift left by 2 msb lsb Shift left by 2 lsb Signed extension hardware 27 Sign bit wire replicated
24 Composing the Elements Make Data path do an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions 28
25 R Type/Load/Store Datapath A Single Cycle Datapath Correct Control signal (RegWrite, ALUSrc, ALU operation, MemWrite, MemtoReg, MemRead) are needed to make sure correct operation is done 29
26 Full Datapath (Single Cycle Datapath) 3
27 Control for the single cycle CPU Designing a processor A single cycle implementation (the datapath) Control for the single cycle CPU Control of CPU operations ALU controller Main controller 4.4 A Simple Implementation Scheme 3
28 Next: Building Datapath With Control
29 Main Control and ALU Control Main Control: Based on opcode: generate RegDst, Branch, MemRead MemtoReg, ALUOp MemWrite, ALUSrc, RegWrite ALU Control: Based on 2 bit ALUop and the 6 bit func field of instruction, the ALU control unit generates the 3 bit ALU control field R-type op rs rt rd shamt funct func Op code 6 6 Main Control ALUop 2 ALU Control Unit ALU control 3 ALU 33
30 Deciding ALU Control Assume 2 bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw load word add? sw store word add? beq branch equal subtract? R-type add add? subtract subtract? AND AND? OR OR? set-on-less-than set-on-less-than?
31 ALU Control ALU Control has 4 four bits: Ainvert, Binvert, and Operation (2 bits) Function ALU control AND OR add subtract set-on-lessthan NOR If NOR is not supported, we just need three bits (MSB bit is always
32 ALU used for ALU Control Load/Store: function = add Branch: function = subtract R type: function depends on funct field Assume 2 bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw load word add sw store word add beq branch equal subtract R-type add add subtract subtract AND AND OR OR set-on-less-than set-on-less-than
33 Control l signal Hopefully, generate Inst. Memory Addr Deciding Main Control Signals Instruction<3:> Op <3:26> <2:25> Rs Rt <6:2> Rd <:5> Control <:5> Imm6 <:5> Funct PCsrc RegDst ALUSrc RegWr MemRd ALUctr (ALUOp) MemWr MemtoReg Equal Datapath 37
34 Review: The Main Control Unit Control signals derived from instruction R-type Load/ Store Branch rs rt rd shamt funct 3:26 25:2 2:6 5: :6 5: 35 or 43 rs rt offset 3:26 25:2 2:6 5: 4 rs rt offset 3:26 25:2 2:6 5: opcode always read read, except for load write for R type and load sign extend and add
35 Control Signals for R Type Instruction PC 4 ADDR ADD Instruction Memory RD immediate/ offset I[5:] Control signals shown in blue Instruction I 32 6 rs I[25:2] WD rt I[2:6] 5 5 RN RN2 WN RD Register File RegWrite rd I[5:] 5 MU 5 RD2 E 6 32 T N D RegDst M U ALUSrc <<2??? Operation 3 ALU ADD Value depends on funct Zero M U PCSrc MemWrite ADDR Data Memory WD MemRead RD MemtoReg M U 39
36 Control Signals: lw Instruction PC 4 ADDR ADD Instruction Memory RD immediate/ offset I[5:] Instruction I 32 6 rs I[25:2] WD rt I[2:6] 5 5 RN RN2 WN RD Register File RegWrite rd I[5:] 5 MU 5 RD2 E 6 32 T N D RegDst M U ALUSrc <<2 Operation 3 ALU ADD Zero M U PCSrc MemWrite ADDR Data Memory WD MemRead RD MemtoReg M U 4
37 Control Signals: sw Instruction PC 4 ADDR ADD Instruction Memory RD immediate/ offset I[5:] Instruction I 32 6 rs I[25:2] WD rt I[2:6] 5 5 RN RN2 WN RD Register File RegWrite rd I[5:] 5 MU 5 RD2 E 6 32 T N D RegDst M U ALUSrc <<2 Operation 3 ALU ADD Zero M U PCSrc MemWrite ADDR Data Memory WD MemRead RD MemtoReg M U 43
38 Control Signals: beq Instruction PC 4 ADDR ADD Instruction Memory RD immediate/ offset I[5:] Instruction I 32 6 rs I[25:2] WD rt I[2:6] 5 5 RN RN2 WN RD Register File RegWrite rd I[5:] 5 MU 5 RD2 E 6 32 T N D RegDst M U ALUSrc <<2 Operation 3 ALU ADD Zero M U PCSrc PCSrc= if Zero= MemWrite ADDR Data Memory WD MemRead RD MemtoReg M U 44
39 Review: Target address of Jump Assume PC=4 6, what is the target address of the jump instruction? 6 bits 26 bits Address in the instruction= x2 Target Address= PC[3:28]+2 6 *4= x484 46
40 Review: Implementing Jumps Jump 2 address 3:26 25: Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26 bit jump address Need an extra control signal decoded from opcode 26 PC+4 Address (25:) 3:28 + New Target Address 47
41 Datapath Executing j j PC 4 ADDR ADD Instruction Memory RD jmpaddr I[25:] op I[3: Control Unit 6 WD <<2 ALUOp RN RN2 WN RD Register File RegWrite 28 ALU Control CONCAT op 6 I[3:26] funct 6 I[5:] Instruction I 5 MU 5 RD2 6 E T N D 32 RegDst 32 PC+4[3-28] M U ALUSrc <<2 Operation 3 ALU ADD Zero PCSrc M U M U Jump Branch MemWrite ADDR Data Memory WD MemRead RD MemtoReg M U 48
42 Truth Table for Main Control Signals Current design of control is for lw, sw, beq, and, or, add, sub, slt I format: lw, sw, beq R format: and, or, add, sub, slt Given 4 OP codes (each 6 bits) as inputs, the outputs are as follows => a main control logic (the next slide) inputs Instruction RegDst ALUSrc Memto Reg outputs Reg Write Mem Read See appendix D for details Mem Write Branch ALUOp ALUOp R format lw sw beq 5
43 Inputs Outputs Implementation of Main Control Block (Use PLA) Use PLA Signal R- lw sw beq name format Op5 Op4 Op3 Op2 Op Op RegDst x x ALUSrc MemtoReg x x RegWrite MemRead MemWrite Branch ALUOp ALUOP Truth table for main control signals Inputs Op5 Op4 Op3 Op2 Op Op R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp ALUOpO Main control PLA (programmable logic array) ALUSrc=? 5
44 Truth Table for ALU control signals inputs outputs Merge LW & SW ALUOp Funct field Operation ALUOp ALUOp F5 F4 F3 F2 F F C 3 C 2 C C 52 add subtract add subtract and or slt
45 C3= Implementation of ALU Control Block C2 ALUOp= is able to identify branch instruction C C ALUOp ALUOp ALUOp ALU control block C2 ALUOp or ALUOp and F F3 C F(5 ) F2 F F C C Operation
46 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pipelining
47 Backup Slides 55
Processor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationThe Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationSystems Architecture
Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationChapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations
Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations
More informationChapter 4. The Processor Designing the datapath
Chapter 4 The Processor Designing the datapath Introduction CPU performance determined by Instruction Count Clock Cycles per Instruction (CPI) and Cycle time Determined by Instruction Set Architecure (ISA)
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 14: One Cycle MIPs Datapath Adapted from Computer Organization and Design, Patterson & Hennessy, UCB R-Format Instructions Read two register operands Perform
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationThe MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationCPU Organization (Design)
ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationChapter 4 The Processor 1. Chapter 4A. The Processor
Chapter 4 The Processor 1 Chapter 4A The Processor Chapter 4 The Processor 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware
More informationIntroduction. Datapath Basics
Introduction CPU performance factors - Instruction count; determined by ISA and compiler - CPI and Cycle time; determined by CPU hardware 1 We will examine a simplified MIPS implementation in this course
More informationLECTURE 5. Single-Cycle Datapath and Control
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.
More informationECE260: Fundamentals of Computer Engineering
Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction
More informationTDT4255 Computer Design. Lecture 4. Magnus Jahre. TDT4255 Computer Design
1 TDT4255 Computer Design Lecture 4 Magnus Jahre 2 Outline Chapter 4.1 to 4.4 A Multi-cycle Processor Appendix D 3 Chapter 4 The Processor Acknowledgement: Slides are adapted from Morgan Kaufmann companion
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationInf2C - Computer Systems Lecture Processor Design Single Cycle
Inf2C - Computer Systems Lecture 10-11 Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh Previous lectures Combinational circuits Combinations of gates (INV, AND, OR,
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationComputer and Information Sciences College / Computer Science Department The Processor: Datapath and Control
Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control Chapter 5 The Processor: Datapath and Control Big Picture: Where are We Now? Performance of a
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationSingle Cycle Datapath
Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.1-4.4 Appendices B.3, B.7, B.8, B.11,.2 ing Note: Appendices A-E in the hardcopy text correspond to chapters 7-11 in
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor 4.1 Introduction Introduction CPU performance factors Instruction count CPI and Cycle time Determined
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationThe Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath
The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:
More informationSingle Cycle Datapath
Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.-4.4 Appendices B.7, B.8, B.,.2 Practice Problems:, 4, 6, 9 ing (2) Introduction We will examine two MIPS implementations
More informationMIPS-Lite Single-Cycle Control
MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More informationSingle Cycle CPU Design. Mehran Rezaei
Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction The Branch
More informationLecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.
Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control
More information361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control
36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationIntroduction. Chapter 4. Instruction Execution. CPU Overview. University of the District of Columbia 30 September, Chapter 4 The Processor 1
Chapter 4 The Processor Introduction CPU performance factors Instruction count etermined by IS and compiler CPI and Cycle time etermined by CPU hardware We will examine two MIPS implementations simplified
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationCSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content
3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design
More informationCSEN 601: Computer System Architecture Summer 2014
CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following
More informationECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationCSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4
More informationCS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)
CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,
More informationReview: Abstract Implementation View
Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationCS 110 Computer Architecture Single-Cycle CPU Datapath & Control
CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides
More informationCS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science A simple MIPS We will design a simple MIPS processor that supports a small instruction
More informationCS/COE0447: Computer Organization
A simple MIPS CS/COE447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science We will design a simple MIPS processor that supports a small instruction
More informationComputer Architecture, IFE CS and T&CS, 4 th sem. Single-Cycle Architecture
Single-Cycle Architecture Data flow Data flow is synchronized with clock (edge) in sequential systems Architecture Elements - assumptions Program (Instruction) memory: All instructions & buses are 32-bit
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationTopic #6. Processor Design
Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between
More informationENGN1640: Design of Computing Systems Topic 04: Single-Cycle Processor Design
ENGN64: Design of Computing Systems Topic 4: Single-Cycle Processor Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
More informationLaboratory 5 Processor Datapath
Laboratory 5 Processor Datapath Description of HW Instruction Set Architecture 16 bit data bus 8 bit address bus Starting address of every program = 0 (PC initialized to 0 by a reset to begin execution)
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. 5 th. Edition. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationECE369. Chapter 5 ECE369
Chapter 5 1 State Elements Unclocked vs. Clocked Clocks used in synchronous logic Clocks are needed in sequential logic to decide when an element that contains state should be updated. State element 1
More informationCC 311- Computer Architecture. The Processor - Control
CC 311- Computer Architecture The Processor - Control Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor
More informationECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath
ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath
More informationChapter 5: The Processor: Datapath and Control
Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor
More informationMark Redekopp and Gandhi Puvvada, All rights reserved. EE 357 Unit 15. Single-Cycle CPU Datapath and Control
EE 37 Unit Single-Cycle CPU path and Control CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationCS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering
CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate:
More informationAdding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20)
Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and
More informationCOMPUTER ORGANIZATION AND DESIGN
ARM COMPUTER ORGANIZATION AND DESIGN Edition The Hardware/Software Interface Chapter 4 The Processor Modified and extended by R.J. Leduc - 2016 To understand this chapter, you will need to understand some
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationSystems Architecture I
Systems Architecture I Topics A Simple Implementation of MIPS * A Multicycle Implementation of MIPS ** *This lecture was derived from material in the text (sec. 5.1-5.3). **This lecture was derived from
More informationDesign of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
More informationCh 5: Designing a Single Cycle Datapath
Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic:
More informationRISC Processor Design
RISC Processor Design Single Cycle Implementation - MIPS Virendra Singh Indian Institute of Science Bangalore virendra@computer.org Lecture 13 SE-273: Processor Design Feb 07, 2011 SE-273@SERC 1 Courtesy:
More informationCPE 335. Basic MIPS Architecture Part II
CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture
More informationCS 351 Exam 2 Mon. 11/2/2015
CS 351 Exam 2 Mon. 11/2/2015 Name: Rules and Hints The MIPS cheat sheet and datapath diagram are attached at the end of this exam for your reference. You may use one handwritten 8.5 11 cheat sheet (front
More informationCPU Design Steps. EECC550 - Shaaban
CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the
More informationHow to design a controller to produce signals to control the datapath
ECE48 Computer Organization and Architecture Designing Single Cycle How to design a controller to produce signals to control the datapath ECE48. 2--7 Recap: The MIPS Formats All MIPS instructions are bits
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University The Processor Logic Design Conventions Building a Datapath A Simple Implementation Scheme An Overview of Pipelining Pipelined
More informationENE 334 Microprocessors
ENE 334 Microprocessors Lecture 6: Datapath and Control : Dejwoot KHAWPARISUTH Adapted from Computer Organization and Design, 3 th & 4 th Edition, Patterson & Hennessy, 2005/2008, Elsevier (MK) http://webstaff.kmutt.ac.th/~dejwoot.kha/
More informationEEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC
More informationLecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1
Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1 Introduction Chapter 4.1 Chapter 4.2 Review: MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions small number
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationDesigning a Multicycle Processor
Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-
More informationWorking on the Pipeline
Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder
More informationData paths for MIPS instructions
You are familiar with how MIPS programs step from one instruction to the next, and how branches can occur conditionally or unconditionally. We next examine the machine level representation of how MIPS
More informationDesign of the MIPS Processor
Design of the MIPS Processor We will study the design of a simple version of MIPS that can support the following instructions: I-type instructions LW, SW R-type instructions, like ADD, SUB Conditional
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/ Review:
More informationChapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance
Chapter 1 Computer Abstractions and Technology Lesson 3: Understanding Performance Manufacturing ICs 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer Chapter 1 Computer Abstractions
More informationﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control
معماري كامپيوتر پيشرفته معماري MIPS data path and control abbasi@basu.ac.ir Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions
More information