CS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)

Transcription

1 CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza [Adapted from lectures on Computer Organization and Design, Patterson & Hennessy, 5 th edition, 23]

2 Review: Processor Design 5 steps Step : Analyze instruction set to determine datapath requirements Meaning of each instruction is given by register transfers Datapath must include storage element for ISA registers Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic 2

3 Processor Design: 5 steps Step : Analyze instruction set to determine datapath requirements Meaning of each instruction is given by register transfers Datapath must include storage element for ISA registers Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic 3

4 Register-Register Timing: One Complete Cycle (Add/Sub) Clk PC Old Value Rs,, Rd, Op, Func ALUctr New Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value ALU Delay busw Old Value New Value RegWr busw Rd 5 5 Rw Rs Ra Rb RegFile 5 busa busb ALUctr ALU Register Write Occurs Here 4

5 Register-Register Timing: One Complete Cycle Clk PC Old Value Rs,, Rd, Op, Func ALUctr New Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value ALU Delay busw Old Value New Value RegWr busw Rd 5 5 Rw Rs Ra Rb RegFile 5 busa busb ALUctr ALU Register Write Occurs Here 5

6 3c: Logical Op (or) with Immediate R[rt] = R[rs] op ZeroExt[imm6] RegDst RegWr Rd 5 5 Rw imm6 Rs Ra Rb RegFile op rs rt immediate 3 6 bits 5 bits 5 bits bits ZeroExt busa busb 6 bits ALUSrc ALUctr 6 immediate 6 bits Writing to register (not Rd)!! ALU What about Read? 6

7 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm6]] Example: lw rt,rs,imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst Rd RegWr 5 5 Rs Rw Ra Rb RegFile 5 busa busb ALUctr ALU imm6 6 ZeroExt ALUSrc 7

8 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm6]] Example: lw rt,rs,imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd 5 5 Rw imm6 Rs Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU MemtoReg Adr Data Memory 8

9 3e: Store Operations Mem[ R[rs] + SignExt[imm6] ] = R[rt] Ex.: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd 5 5 imm6 Rs Rw Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data Memory MemtoReg 9

10 3e: Store Operations Mem[ R[rs] + SignExt[imm6] ] = R[rt] Ex.: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd 5 5 imm6 Rs Rw Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data Memory MemtoReg

11 3f: The Branch Instruction beq rs, rt, imm6 mem[pc] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction s address PC = PC ( SignExt(imm6) x 4 ) else 3 PC = PC op 2 rs 6 rt immediate 6 bits 5 bits 5 bits 6 bits

12 Datapath for Branch Operations beq rs, rt, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits Datapath generates condition (Equal) Inst Address 4 PC Ext imm6 Adder Adder npc_sel Mux PC RegWr busw 5 5 Rs Rw Ra Rb RegFile busa busb ALUctr Already have mux, adder, need special sign extender for PC, need equal compare (sub?) 5 Equal = ALU 2

13 Instruction Fetch Unit including Branch op rs rt immediate if (Zero == ) then PC = PC SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Inst Memory Adr Instruction<3:> Equal MUX ctrl npc_sel How to encode npc_sel? Direct MUX select? imm6 4 PC Ext Adder Adder Mux PC Branch inst. / not branch inst. Let s pick 2nd option npc_sel zero? MUX x Q: What logic gate? 3

14 Putting it All Together: A Single Cycle Datapath 4 PC Ext imm6 Adder Adder npc_sel Mux Inst Memory PC Adr Rs RegDst RegWr busw Rd <2:25> 5 5 imm6 <6:2> Rs Rw Ra Rb RegFile 6 Rd 5 <:5> Extender busa busb ExtOp <:5> Imm6 Equal Instruction<3:> ALUSrc ALUctr = ALU Data In MemWr WrEn Adr Data Memory MemtoReg 4

15 Datapath Control Signals ExtOp: zero, sign ALUsrc: regb; immed ALUctr: ADD, SUB, OR MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext imm6 Adder Adder Inst Address npc_sel & Equal Mux PC RegDst RegWr busw Rd 5 5 Rw imm6 Rs Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr Data In ALU MemWr WrEn Adr Data Memory MemtoReg 5

16 Given Datapath: RTL Control Instruction<3:> Inst Memory Adr <26:3> <:5> <2:25> <6:2> <:5> <:5> Op Fun Rs Rd Imm6 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg DATA PATH 6

17 RTL: The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction s address 7

18 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions Inst Memory Instruction<3:> 4 PC Ext npc_sel Mux Adder Adder PC Inst Address imm6 8

19 Single Cycle Datapath during Add op rs rt rd shamt funct R[rd] = R[rs] + R[rt] RegDst= Rd RegWr= busw 6 npc_sel= Rw imm6 Rs Ra Rb RegFile 6 5 ExtOp=x Extender busa busb instr fetch unit zero ALUSrc= 6 Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=ADD MemtoReg= = Data In ALU <6:2> <:5> MemWr= WrEn Adr Data Memory <:5> 9

20 Instruction Fetch Unit at End of Add PC = PC + 4 Same for all instructions except: Branch and Jump Inst Memory 4 PC Ext npc_sel=+4 Mux Adder Adder PC Inst Address imm6 2

21 P&H Figure 4.7 2

22 Summary of the Control Signals (/2) inst Register Transfer add R[rd] R[rs] + R[rt]; PC PC + 4 ALUsrc=RegB, ALUctr= ADD, RegDst=rd, RegWr, npc_sel= +4 sub R[rd] R[rs] R[rt]; PC PC + 4 ALUsrc=RegB, ALUctr= SUB, RegDst=rd, RegWr, npc_sel= +4 ori R[rt] R[rs] + zero_ext(imm6); PC PC + 4 ALUsrc=Im, Extop= Z, ALUctr= OR, RegDst=rt,RegWr, npc_sel= +4 lw R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 ALUsrc=Im, Extop= sn, ALUctr= ADD, MemtoReg, RegDst=rt, RegWr, npc_sel = +4 sw MEM[ R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 ALUsrc=Im, Extop= sn, ALUctr = ADD, MemWr, npc_sel = +4 beq if (R[rs] == R[rt]) then PC PC + sign_ext(imm6)] else PC PC + 4 npc_sel = br, ALUctr = SUB 22

23 Summary of the Control Signals (2/2) See func We Don t Care :-) Appendix A op RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr<2:> add sub ori lw sw beq jump x Add x Subtract Or Add x x Add x x x Subtract x x x? x x R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump 23

24 Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw npcsel = beq Jump = jump ExtOp = lw + sw ALUctr[] = sub + beq (assume ALUctr is ADD, SUB, OR) ALUctr[] = or Where: rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op ~op, ori = ~op 5 ~op 4 op 3 op 2 ~op op lw = op 5 ~op 4 ~op 3 ~op 2 op op sw = op 5 ~op 4 op 3 ~op 2 op op beq = ~op 5 ~op 4 ~op 3 op 2 ~op ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op ~op How do we implement this in gates? add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func ~func 24

25 Controller Implementation opcode func AND logic add sub ori lw sw beq jump OR logic RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr[] ALUctr[] 25

26 Summary: Single-cycle Processor Five steps to design a processor:. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements Processor Control Datapath Memory 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Input Output 26