ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

Size: px

Start display at page:

Download "ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation"

Robert Lambert
6 years ago
Views:

1 ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right logical Load upper immediate Load word Store word Load byte Store byte Branch on equal (zero) Branch on not equal (zero) CPI in a Multicycle CPU Q) : Using the SPECINT2000 instruction mix shown in Figure, what is the CPI, assuming that each state in the multicycle CPU requires 1 clock cycle? Add Core MIPS Add immediate Add unsigned Name add addi addu addiu subu and andi or ori nor sll srl Lui lw sw lbu sb beq bne Integer 7% 12% 3% 3% 7% 2% 3% 2% 24% 9% FI.pt. 2 2% 2% 2% 5% 15% 2% Core MIPS Jump and link Jump register Set less than Set less than immediate Set less than unsigned Set less than imm. Uns. Arithmetic core + MIPS-32 FP add double FP subtract double FP mutiply double FP divide double Load word to FP double Store word to FP double Shift right arithmetic Load half Branch less than zero 6% Lecture Slides 2% on Computer 5% multiply Branch greater or equal zero Branch less or equal zero Name jal Jr Slt Slti Sltu Sltiu Name add.d sub.d mul.d div.d l.d s.d sra lhu bltz bgez blez mul Integer 2% Integer FI.pt. FI.pt. 8% 3% 8% 15% 7% 2 1

2 CPI in a Multicycle CPU Given the number of clock cycles for each instruction class : Loads: 5 Stores: 4 ALU instructions: 4 Branches: 3 Jumps: 3 From the figure, the integer mix is 25% loads ( load byte + 24% load word), 1 stores ( store byte + 9% store word), 1 branches (6% beq, 5% bne), 2% jumps ( jal + jr), and 52% ALU (all the rest of the mix, which we assume to be ALU instructions). 3 Multi-Cycle Implementation CPU clock cycles = Instruction count i x CPI i The CPI is given by the following: CPI = CPU Clock Cycles = instruction count i x CPI i Instruction count Instruction count The ratio instruction count i Instruction count is simply the instruction frequency for the instruction class i Hence we can write, CPI = 0.25 x x x x x 3 = 4.12 This CPI is better than the worst-case CPI of 5.0 when all the instructions take the same number of clock cycles. The multicycle design is probably also more cost-effective, since it uses fewer separate components in the datapath. 4 2

3 Multi-Cycle Implementation - Control Defining the Control Two different techniques to specify the control. Finite State Machines (FSMs) : The first technique is based on finite state machines that graphically. are usually represented Micrprogramming : The second technique, called microprogramming, uses a programming representation for control. Both of these techniques represent the control in a form that allows the detailed implementation using gates, ROMs, or PLAs to be synthesized by a CAD system. 5 Multi-Cycle Implementation Control Alternate methods for specifying and implementing control 6 3

4 Multi-Cycle Control - FSM Finite State Machine (FSM) to specify the multicycle control A finite state machine consists of a set of states and directions on how to change states. The directions are defined by a next-state function, which maps the current state and the inputs to a new state. When we use a finite state machine for control, each state also specifies a set of outputs that are asserted when the machine is in that state. The implementation of a finite state machine usually assumes that all outputs that are not explicitly asserted are deasserted. Similarly, the correct operation of the datapath depend on the fact that a signal that is not the explicitly asserted is deasserted, rather than acting as a don t care. 7 Multi-Cycle Control - FSM The finite state control essentially corresponds to the five steps of execution. Each state in the finite state machine will take 1 clock cycle. The finite state machine will consist of several parts. Since the first two steps of execution are identical for every instruction, the initial two states of the finite state machine will be common for all instructions. Step 3 through 5 differ, depending on the opcode. After the execution of the last step for a particular instruction class, the finite state machine will return to the initial state to begin fetching the next instruction. The finite state machine has four arcs existing state 1, corresponding to the four instruction classes: memory reference, R-type, branch on equal, and jump. This process of branching to different states depending on the instruction is called decoding, since the choice of the next state, and hence the actions that follow, depend on the instruction class. 8 4

5 Multi-Cycle Control - FSM High level view of the Finite State Machine Control 9 Multi-Cycle Implementation - Control State 0 State

6 Multi-Cycle Implementation - Control From State 1 State 2 State 3 State 5 State 4 To State 0 11 Multi-Cycle Implementation - Control From State 1 State 6 State 7 Lecture Slides on To Computer State

7 Multi-Cycle Implementation - Control From State 1 State 8 To State 0 13 Multi-Cycle Implementation - Control From State 1 State 9 To State

8 Multi-Cycle Control - FSM State 0 State 1 State 2 State 6 State 8 State 9 State 3 State 5 State 7 State 4 Complete Finite State Machine Control for the datapath 15 Multi-Cycle Control - FSM A finite state machine can be implemented with a temporary register that holds the current state and a block of combinatorial logic that determines both the datapath signals to be asserted as well as the next state. The combinatorial control logic for the finite state machine of the figure is implemented both with a ROM (read-only memory) and a PLA (programmable logic array). The style of finite state machine in the figure is called a Moore machine, after Edward Moore. Its identifying characteristics is that the output depends only on the current state. For a Moore machine, the box labeled combinatorial control logic can be split into two pieces. One piece has the control output and only the state input, while the other has only the next-state output. 16 8

9 Multi-Cycle Control - FSM Finite State Machine Controller 17 Multi-Cycle Implementation An alternative style of machine is a Mealy machine, named after George Mealy. The Mealy machine allows both the input and the current state to be used to determine the output. Moore machines have potential implementation advantages in speed and size of the control unit. The speed advantages arise because the control outputs, which are needed early in the clock cycle, do not depend on the inputs, but only on the current state. 18 9

10 Multi-Cycle Implementation Exceptions An exception is an unexpected event from within the processor; Example : arithmetic overflow An interrupt is an event that also causes an unexpected change in control flow but comes from outside of the processor. Type of event I/O device request Invoke the operating system from user program Arithmetic overflow Using an undefined instruction Hardware malfunctions From where? External Internal Internal Internal Either MIPS terminology Interrupt Exception Exception Exception Exception or interrupt 19 Multi-Cycle Implementation - Exceptions How Exceptions Are Handled The two types of exceptions that our current implementation can generate are execution of an undefined instruction and an arithmetic overflow. The basic action that the machine must perform when an exception occurs is to save the address of the offending instruction in the exception program counter (EPC) and then transfer control to the operating system at some specified address. The operating system can then take the appropriate action, which may involve providing some service to the user program, taking some predefined action in response to an overflow, or stopping the execution of the program and reporting an error. After performing whatever action is required because of the exception, the operating system can terminate the program or may continue its execution, using the EPC to determine where to restart the execution of the program

11 Multi-Cycle Implementation - Exceptions For the operating system to handle the exception, it must know the reason for the exception, in addition to the instruction that caused it. There are two main methods used to communicate the reason for an exception. The method used in the MIPS architecture is to include a status register (called the Cause register), which holds a field that indicates the reason for the exception. A second method is to use vectored interrupts. In a vectored interrupt, the address to which control is transferred is determined by the cause of the exception. For example, to accommodate the two exception types, we define the following two exception vector addresses: Exception type Undefined instruction Arithmetic overflow Exception vector address ( in hex) C hex C hex 21 Multi-Cycle Implementation - Exceptions The operating system knows the reason for the exception by the address at which it is initiated. The addresses are separated by 32 bytes or 8 instructions, and the operating system must record the reason for the exception and may perform some limited processing in this sequence. When the exception is not vectored, a single entry point for all exceptions can be used, and the operating system decodes the status register to find the cause. We can perform the processing required for exceptions by adding a few extra registers and control signals to our basic implementation and by slightly extending the finite state machine

12 Multi-Cycle Implementation - Exceptions Need to add two additional registers to the datapath: EPC: A 32-bit register used to hold the address of the affected instruction. (Such a register is needed even exceptions are vectored.) Cause: A register used to record the cause of the exception. In the MIPS architecture, this register is 32- bits, although some bits are currently unused. Assume that the low-order bit of this register encodes the two possible exception sources: undefined instruction = 0 and arithmetic overflow =1. 23 Multi-Cycle Implementation - Exceptions need to add two control signals to cause the EPC and Cause registers to be written; call these EPCWrite and CauseWrite. In addition, we will need a 1-bit control signal to set the loworder bit of the Cause register appropriately; call this signal IntCause. Finally, we will need to be able to write the exception address, which is the operating system entry point for exception handling, into the PC; in the MIPS architecture, this address is hex. (the SPIM simulator for MIPS uses hex.) Currently, the PC is fed from the output of a three-way multiplexor, which is controlled by the signal PCSource. We can change this to a four-way multiplexor, with additional input wired to the constant value hex. Then PCSource can be set to 11 two to select this value to be written into the PC

13 Multi-Cycle Implementation - Exceptions Because the PC is incremented during the first cycle of every instruction, we cannot adjust the value of the PC into the EPC, since the value in the PC will be the instruction address plus 4. However, we can use the ALU to subtract 4 from the PC and write the output into the EPC. This requires no additional control signals or paths, since we can use the ALU to subtract, and the constant 4 is already a selectable ALU input. The data write port of the EPC, therefore, is connected to the ALU output. 25 Multi-Cycle Implementation Exceptions Multicycle datapath wih the addition needed to implement exceptions 26 13

14 Multi-Cycle Implementation- Exceptions State 0 State 1 State 2 State 6 State 8 State 9 State 3 State 5 State 7 State 11 State 10 State 4 FSM with the additional states to handle exception detection 27 Reading Assignments Chapter 5 : Sections 5.1 to 5.9 Also Refer CD 28 14

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers