TDT4255 Computer Design. Lecture 4. Magnus Jahre. TDT4255 Computer Design
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1 1 TDT4255 Computer Design Lecture 4 Magnus Jahre
2 2 Outline Chapter 4.1 to 4.4 A Multi-cycle Processor Appendix D
3 3 Chapter 4 The Processor Acknowledgement: Slides are adapted from Morgan Kaufmann companion material
4 4 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine three MIPS implementations Single cycle and multi cycle (today) Pipelined (later lectures) Simple, informative instruction subset Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j
5 5 Instruction Execution 1. PC instruction memory, fetch instruction 2. Register numbers register file, read registers 3. Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4
6 6 CPU Overview
7 7 Multiplexers Can t just join wires together Use multiplexers Control signals determine which input is used
8 8 4.2: Logic Design Conventions
9 9 Logic Design Repetition Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information
10 10 Combinational Elements AND-gate Y = A & B Adder Y = A + B A B + Y A B I0 I1 M u x S Y Multiplexer Y = S? I1 : I0 Y Arithmetic/Logic Unit Y = F(A, B) A ALU Y B F
11 11 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q Clk D Q
12 12 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Write Clk Q Write D Q
13 13 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay (critical path) determines clock period
14 14 4.3: Building a Datapath
15 15 Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, mux s, memories, We will build a MIPS datapath incrementally Design goal: Efficiently implement the three instruction formats: We ll start with these
16 16 Instruction Fetch 32-bit register Increment by 4 for next instruction
17 17 R-Format Instructions 1. Read two register operands 2. Perform arithmetic/logical operation 3. Write register result
18 18 Load/Store Instructions 1. Read register operands 2. Calculate address using 16-bit offset Use ALU, but sign-extend offset 3. Finish instruction: Load: Read memory and update register Store: Write register value to memory
19 19 Branch Instructions 1. Read register operands 2. Compare operands Use ALU, subtract and check Zero output 3. Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch
20 20 Branch Instructions Just re-routes wires Sign-bit wire replicated
21 21 Composing the Elements First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions
22 22 5 minute assignment: Draw your own datapath
23 23 Rough R-Type/Load/Store Datapath
24 24 4.4: A Simple Implementation Scheme A Single Cycle Processor
25 25 ALU Control ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR
26 26 ALU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add add 0010 subtract subtract 0110 AND AND 0000 OR OR 0001 set-on-less-than set-on-less-than 0111
27 27 The Main Control Unit Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read read, except for load write for R-type and load sign-extend and add
28 28 Datapath With Control
29 29 R-Type Instruction Example add $t0, $s1, $s2
30 30 Load Instruction Example lw $t0, 32($s3)
31 31 Branch-on-Equal Instruction Example beq $t0, $t1, label
32 32 Implementing Jumps Jump 2 address 31:26 25:0 Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 Need an extra control signal decoded from opcode
33 33 Datapath With Jumps Added
34 34 Single Cycle Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast Possible improvements: A multi-cycle implementation (not so common) Pipelining (very common)
35 35 A Multi-cycle Processor
36 36 Motivation Not all instructions use all functional units Idea: Use more than one cycle per instruction Different phases of an instruction can reuse hardware resources (reduces area) Instructions that need less resources can use less cycles (may improve performance) Nice example of FSMs in control units Applicable to many other designs than processors
37 37 Datapath Changes (1/2) Idea: Add registers at strategic points in the datapath Activate only needed functional units with control signals
38 38 Datapath Changes (2/2) Area savings possible (but not necessary) Only one memory Only one ALU
39 39 Digression: Exercise Architecture Memory access takes one cycle FPGA block RAM is built that way Questions: command bus_address_in bus_data_in status bus_data_out TDT4255_COM (com) read_addr read_data write_addr write_data write_enable write_imem processor_enable DMEM_MUX w_address w_data w_enable address data DATA_MEMORY (mem) Can we use a single memory implementation? Do we want to? PROCESSOR processor_enable dmem_address dmem_address_wr dmem_write_enable dmem_data_out dmem_data_in INSTRUCTION_MEMORY (mem) w_address w_data Remember: Design choices in other parts of the system add constraints and possibilities imem_address imem_data_in w_enable address data
40 40 MIPS Multi-Cycle
41 41 Control State Machine Step name Action R-type Action Load/Store Action Branch Action Jump Instruction Fetch IR <= Memory[PC] PC <= PC + 4 Instruction decode Register fetch A <= REG [rs] B <= REG [rt] ALUOut <= PC + (sign-extended immediate << 2) Execution/Branch completion/jump completion ALUOut <= A op B ALUOut <= A + signextended immediate If (Zero) => PC <= AluOut PC <= PC[31:28]:IR[25:0]:00 (: is concatenation) Memory access R-type completion Reg[rd] <= ALUOut Load: MDR <= Memory[ALUOut] Store: Memory[ALUOut] <= B Load completion Load: REG[rt] <= MDR
42 42 Datapath and Control
43 43 Final Multi-Cycle Design Datapath Finite State Machine (FSM) Datapath with control signals
44 44 Multi-cycle Evaluation Uses less hardware than our single cycle datapath Adds a few registers and MUXes but saves two ALUs and a memory Still limited possibilities for making the common case fast: Performance determined by resource needs Branch/Jump take 3 cycles ALU/Store instructions take 4 cycles Loads take 5 cycles Multi-cycle CPUs are not widely used Performance inferior to pipelining
45 45 Appendix D Mapping Control to Hardware
46 46 Control Units Combinatorial control units Lacks state The single cycle processor has a combinatorial control unit: All state is determined by the current instruction Sequential control units Larger and more complex than combinatorial control units Can use smaller combinatorial units internally Finite state machines vs. Microprograms
47 47 D.2: Implementing Combinatorial Control Units
48 48 Mapping Control Functions to Gates PLA realization of single cycle opcode to control signal control Modern synthesis tools does this operation for us PLA = Programmable Logic Array
49 49 D.3: Implementing Finite State Machine Control
50 50 FSM Implementation ROM realization Input bit pattern is address and output pattern is the value But: cannot have don t cares Solution: Partition into multiple smaller ROMs (still not ideal) PLA realization Simplify logic to sum-of-products form (handles don t cares) Sum of products = ORs of ANDs
51 51 D.4: Implementing Next-State Function with a Sequencer
52 52 Sequencer Motivation Implementing the next state function with combinatorial logic adds overhead Can we do better? Two ROM implementation: 94% of values used to code next state function Trick: Lets code the states such that the next state is commonly represented by the current state value + 1 Add branch logic for other FSM paths
53 53 Sequencer-based FSM Implementation
54 54 Further Reducing FSM Logic Logic Minimization Uses the logic structure and don t cares to reduce the amount of logic required Cleverly choosing state codes can add optimization possibilities The synthesis tool does this for us Did it work? (read synthesis tool output!) State Assignment Choose state to bit pattern mappings that simplify well
55 55 Microprogrammed Control A Sequencer-based FSM is very similar to a simple computer Completing the abstraction: Microprogram counter Microinstructions Microprogram
56 56 Concluding Remarks Single-cycle processor Very simple control Single cycle datapath is a good starting point for more advanced architectures Multi-cycle processor Example of a system with more complex control Not very different from a pipelined processor Pipelining idea: store control signals and data in registers More on this later
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