INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

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1 INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II - B. Tech Branch : ECE Year : 0 0 Course Coordinator : Mr. Khalandhar Basha Course Faculty : Mr. k arun sai, Ms.parvathi sreekumar OBJECTIVES Designing digital circuits at behavioral and RTL modeling of digital circuits using verilog HDL. verifying these models, and synthesizing RTL models to standard cell libraries and FPGAs. Students gain practical experience by designing, modeling, implementing and verifying several digital circuits. This course aims provide students with the understanding of different technologies related to HDLs, constructs, compile and execute verilog HDL programs using provided software tools. Design digital components and circuits that are testable, reusable and synthesizable.. Group - A (Short Answer Questions) S. No QUESTION 0 Blooms Taxonomy Level UNIT-I INTRODUCTION TO VERILOG HDL Define verilog HDL? Remember List levels of design description in verilog HDL? Remember Describe is concurrency? Remember What is simulation and synthesis? Evaluate What is functional verification? Evaluate What are system tasks? Evaluate Write short notes on programming language interface (PLI). Evaluate What is module? Evaluate What is a simulation and synthesis tool? Evaluate What is test bench? Evaluate Course Outcome P a g e

2 Blooms Taxonomy Course S. No QUESTION. Define keywords and identifiers? Remember What are white space characters? Evaluate Define comments and numbers? Remember Define strings and logic values? Remember What is a data types? And what are those? Evaluate Define scalars and vectors? Remember Define parameters and memory operators? Remember Define system tasks? Remember UNIT-II GATE LEVEL MODELING AND MODELING AT DATAFLOW LEVEL What is gate level modeling? Evaluate What is AND gate primitive? Evaluate What is module structure? Give the example of module structure. Evaluate Define tri-state gate? Remember What is array of instances of primitives? Evaluate Define delay? Remember Define strengths and content resolution? Remember What is a net data type? Evaluate How many types of net data types? Evaluate How many tri-state gates are there in verilog? Evaluate What is continuous assignment structure? Evaluate What is assignment to vectors? Evaluate Define operators in verilog? Remember UNIT-III BEHAVIORAL MODELING. What is behavioral modeling? Evaluate. What are operations and assignments? Evaluate. Define functional Bifurcation. Remember P a g e

3 S. No QUESTION Blooms Taxonomy Course. Define initial construct. Remember. Define always construct. Remember. Explain assignments with delays Understand. Define wait construct Remember Explain multiple always blocks Understand. Define blocking and non-blocking assignments Remember 0. Explain the case statement Understand. Draw a simulation flow chart Analyze. Explain if and if-else construct Understand. Explain assign and de-assign construct. Understand. Define repeat construct Remember. Write the syntax for a for loop Apply. Write the syntax for a while loop and forever loop Apply. Explain parallel blocks Understand Explain force release construct Understand UNIT-IV SWITCH LEVEL MODELING, SYSTEM TASKS FUNCTIONS AND COMPILER DIRECTIVES. Explain basic transistor switches. Understand. Define basic switch primitive. Remember. Explain the operation of nmos switch. Understand... Explain the operation of pmos switch. Understand Define resistive switches. Remember Define cmos switch. Remember Explain Bi-Directional gates. Understand. How to insatiate with strength and delays. Understand.. Define system task. Remember Define parameter. Remember Explain parameter declaration and assignments. Understand Define module paths. Remember Define specify block. Remember Define system function. Remember P a g e

4 S. No QUESTION Blooms Taxonomy Course. Explain $display Task. Understand. Explain file based tasks and functions. Understand. Explain compiler directives. Understand. Define hierarchical access. Remember UNIT-V SEQUENTIAL CIRCUIT DESCRIPTION, COMPONENT TEST VERIFICATION What are the types of sequential models? Evaluate Explain Feedback model. Understand Explain capacitive model. Understand Explain implicit model. Understand What are the basic memory components? Evaluate Explain functional register. Understand Define state machine coding. Remember How do you explain sequential synthesis? Understand What is test bench? Evaluate 0 How to test a combinational circuit. Understand. What is sequential circuit testing? Evaluate. Explain test bench techniques. Understand. Define design verification. Remember 0. Define assertion verification. Remember 0. Group - II (Long Answer Questions) S. No Question Blooms Taxonomy Level UNIT-I INTRODUCTION TO VERILOG HDL Write short note on Verilog as HDL Understanding Discuss Level of design description. Demonstrate Explain top-down design methodology with example. Understand Program Outcome P a g e

5 S. No Question Write short notes on, Blooms Taxonomy Program Apply (a) Concurrency (b) Functional verification Define the following terms relevant to Verilog HDL, Remember (a). Simulation versus synthesis. (b). PLI (c). System tasks. what are the system tasks available in Verilog for making and controlling simulation? Explain about, (a). Display tasks (b). Strobe tasks (c). Monitor tasks with examples. Define the following terms relevant to Verilog HDL. (a). Module (b). Test bench. Evaluate Understand Remember 0... Write a syntax functions and tasks with one example. Apply Write about $readmemb with example. Apply Write value change dump file. Apply Explain the synthesis procedure in Verilog HDL. Understand. Give the surfaces for Verilog module and explain gate instantiations with examples. create UNIT-II GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING Explain in brief built-in primitive gates that are available in Verilog HDL. Understand Explain NAND gate primitive with Verilog module. Understand P a g e

6 Blooms Taxonomy Program S. No Question Explain NOR gate primitive with Verilog module. Understand Design a module for addition of bit words. Analyze Write Verilog module for addition bit words. Apply What is a three-state gate and explain each type of three-state gate with truth tables? Evaluate Write a Verilog code for tri-state devices. Apply,. Write Verilog HDL source code for a gate level description of to multiplexer circuit. Draw the relevant logic diagram. Implement Verilog HDL source code and draw the logic diagram of a -to- decoder circuit. Give the gate level description. Apply, Evaluate, Design module and a test bench for a half-adder. Analyze Design module and a test bench for a to multiples module. Analyze Explain simple latch with Verilog module. Understand Design a RS-flip with NAND gates. Analyze Write a Verilog code for RS flip-flop with NAND gates. Apply Explain clocked RS flip-flop Verilog module and test bench. Understand Design a D-Flip-flop with gate primitives and write its Verilog code. Analyze Design a D flip flop using NAND gates. Create Write a Verilog code for D flip flop using NAND gates. Apply Classify delays and explain. Creating Explain inertial and intra-assignment delays in Verilog. Understand Design a JK flip flop using NAND gates. Create Write a Verilog code for JK flip flop using NAND gates. Apply. Explain the design approach of a master slave flip-flop with gate primitives. (OR) Design a master slave JK flip-flop using NAND gates. Apply. Write a Verilog code for master slave JK flip flop using NAND gates. Apply P a g e

7 Blooms Taxonomy Program S. No Question. Design a T flip flop using NAND gates. Create Write a Verilog code for T flip flop using NAND gates. Apply Write notes on gate delays with necessary instantiations. Apply Explain delays with tristate gates. Apply Classify and explain strength and contention resolution. Creating Design module to illustrate use if the wand-type net and test bench with stimulation results. Create. Draw the half adder circuits in terms of EX-OR and AND gates. Prepare the half adder module and test bench in terms of and AND gate primitives. Evaluate.... Design a module and test bench for a full-adder. Create Design a X multiplier circuit and write its Verilog HDL code. Create Write a Verilog HDL code for ripple-carry adder using generic specification? Apply Design a bit full adder using gate level primitives and write its HDL code. Create. Design a to demultiplexer module by using to decoder, and white its Verilog code. Create. Explain continuous assignment structures with examples. Understand. Explain about the concurrent statements in data flow level. Give one Understand example to each one.. Explain net delay with assignment delay and effects of net delay with Understand suitable example. 0. Explain combining assignment and net declarations with examples. Understand UNIT-III BEHAVIORAL MODELING Write a short note on, Apply (a). Functional bifurcation (b). Intra-assignment delays. Write the differences between begin-end and fork-blocks with examples. Apply Design up counter coding procedural assignment. Create Write up counter test bench, simulation results. Analysis Write the syntax for the following constructs and Apply P a g e

8 S. No Question give one example for each relevant to behavioral Blooms Taxonomy Level Program Outcome Verilog HDL modeling. (a). initial construct, (b). always construct (c). wait construct. What is the difference between an intra- statement delay and an interstatement delay? explain using an example. Write short notes on the following with examples, (a). Intra-assignment delays (b). Delay assignments (c). Zero delay. remembering Apply 0 What are the advantages of multiple always blocks? Explain with example. remembering Write a Verilog module for a rudimentary serial transmitter module. Apply Explain multiple always blocks. Understand. Write a model using the behavioral modeling style to describe the behavior of a JK flip- flop using an always statement. Apply.. (a). Design Verilog module to identify the highest priority interrupts. (b). Write test bench simulation results of above questions with explanation (a). Design module to convert angels in radians to one in degrees. (b). Write Verilog code above question with explanation. Create Create. Explain blocking and non-blocking statement with examples. Understand.. Write a Verilog HDL code for n-bit shift register with an enable input using blocking assignments. Draw the flowchart for the simulation flow. OR Explain flowchart for the simulation flow. Apply Understand. Write Verilog code using case statement for any one example. Apply P a g e

9 S. No Question Write the syntax for the following constructs and give one example for each levant to behavioral Verilog HDL modeling. Blooms Taxonomy Program Apply. (a). The case statement (b). If and if-else constructs. UNIT-IV SWITCH LEVEL MODELING Design half subtractor using CMOS switches. Create Write the Verilog code for half subtractor using CMOS switches. Apply Design code, test bench, results for CMOS switch with a single control line. Create Design CMOS flip-flop. Create Design Verilog module for CMOS flip-flop. Create Explain bi-directional gates with suitable logic diagrams and give their switch Understand level modeling Design half -adder using CMOS switches. Create Write the Verilog code for half adder using CMOS switches. Apply Write about basic switch primitives. Apply 0 Write notes on time delays with switch primitives relevant to switch level modeling. understanding How strength and delays are instantiated? Explain. OR Write notes on instantiations with strength and delays relevant to switch level modeling. understanding Define and explain the following terms relevant to Verilog HDL, (a) Module parameters Remember (b) File-based tasks and functions (c) Compiler directives. Explain parameter declaration and assignments. Understand Explain type declaration for parameters. Understand Explain automatic(recursive) function. Understand Explain about module paths. Understand Define and explain the following terms relevant to Verilog HDL, Remember (a) Hierarchical access (b) Path delays. Explain $ finish task with example. Understand Explain $ random function with example. Understand 0 Explain asymmetric sequence generator with example. Understand UNIT-V SEQUENTIAL CIRCUIT DESCRIPTION What are the various sequential memory storage models? Explain in detail Evaluate P a g e

10 S. No Question about each of them. Blooms Taxonomy Level Program Outcome Explain cross-coupled NOR latch and ALL NAND clocked SR latch with the help Understand of neat sketches and write the Verilog cods for each of them. Draw the block diagram of master-slave flip-flop constructed using latches analyze and write the Verilog code for the same. Explain about sequential UDP with the help of an example. Understand Draw and explain the block diagram of master-slave flip-flop with two feedback blocks using assign statements. Also write the Verilog code for the same. analyze Explain behavioral modeling for D-type latch and the use of non-blocking Understand assignments in latch modeling. Also with the Verilog code for each of them. Write and explain the Verilog module for positive edge trigger flip-flop. Understanding 0 Write a Verilog module for D flip-flop with synchronous control and Understanding 0 asynchronous control. And compare the controls of both. What is function of fork-join construct? Design a Verilog module for D flip- Evaluate 0 flop using this construct. 0 Write a Verilog code for D flip-flop using assign and deassign statements. Understanding 0 Define setup time. Write a Verilog code for D flip-flop setup time. Remember 0 Define hold time. Design a Verilog module for D flip-flop with hold time. Remember 0 Discuss about setup hold, width and period checks used in Verilog. Write a Remember 0 Verilog module for D flip-flop using setup hold, width and period checks. Design a Verilog module for the following, Create 0 (i) -bit transparent D-Latch (ii) -bit register with tri-state output. How the memory initialization does is carried out in Verilog? Explain with the Create 0 help of an example. What are the rules to be followed to declare and to use the bidirectional Evaluate 0 lines? Write a Verilog module for PLA. Understand 0 What is functional register? Write and explain the Verilog module for basic Evaluate 0 shift register? Design and explain the Verilog module for universal shift register. Create 0 0 Explain about shift register that uses separates combinational and Understand 0 sequential blocks. Also write a Verilog code for the same. Write a Verilog code for -binary up-down counter. Understanding 0 Write a short notes on gray-code counter. Also design a Verilog module for Understanding 0 the same. Explain about LFSR and design its Verilog module in structural model. Understand 0 Explain MISR with the help of a neat sketch and also write the Verilog code Understand 0 for the same. Explain about FIFO Queue with the help of block diagram. Understand 0 Write a Verilog code for FIFO Queue. Understanding 0 Write a short notes on Moore 0 sequence detector. And write the Understanding 0 Verilog code for the same. Explain in brief about Mealy 0 sequence detector. Understand 0 Explain how the state machine is designed for large number of input-output Understand 0 line. 0 P a g e

11 S. No Question Blooms Taxonomy Program 0 Write a Verilog code for moore detector using Huffman model. Also explain Understanding 0 it. Explain about ROM-based controller. Write the Verilog code for the same. Understand 0 Explain about the following with the help of neat block diagram, Understand 0 (a) Implementation of FPGA latch (b) Implementation of FPGA flip-flop. Write a Verilog module for -bit ALU, also obtain its test bench and Understanding 0 simulation results. Write and explain the test bench for multi input signature register. Understanding 0. Group - III (Analytical Questions) S.No QUESTIONS UNIT-I INTRODUCTION TO VERILOG HDL Using examples, explain about concurrent and procedural statement with syntaxes. Blooms Taxonomy Level Understand Program Outcome Explain port declaration with an example using Verilog code. Understand Explain the components of a Verilog module with block diagram. Understand Define the following terms relevant to Verilog HDL construct and onventions. Remember (a). Identifiers (b). Strings (c). Data types. Define the following terms relevant to Verilog HDL constructs and conventions. Remember (a). Keywords (b). Strengths (c). Parameters. Explain about number system used in Verilog. Understand Define the following terms relevant to Verilog HDL construct and conventions. Remember (a). Comments, (b). Scalars and vectors. (b). Scalars and vectors. Write about and differences scalars vectors in Verilog module with examples. Apply P a g e

12 S.No QUESTIONS Using examples, explain about concurrent and procedural statement with syntaxes. Blooms Taxonomy Program comprehension 0 Explain port declaration with an example using Verilog code. Understand Define the following terms relevant to Verilog HDL constructs and conventions. Remember (a). Logic values (b). Operators. Write about white space characters and variables with examples. Apply UNIT-II GATE LEVEL MODELING AND DATAFLOW LEVEL MODELING Write a Verilog HDL code for n-bit right-to-left shift register using data flow Apply level. Give the list of operations in data flow level and give one example for each one. Apply OR Comprehension Write short notes for the following with examples. (a) Unary operators (b) (c) (d) Binary operators Arithmetic operators Logical operators. Explain about operator priority with examples. Understand Explain bit widths of expressions. Understand Design a Verilog module for a to vector multiplexer or module at data flow Create level. Give the block diagram of one digit BCD adder and write its Verilog HDL code. OR Create Design a Verilog module for a BCD adder module at the data flow level. Write a data flow model for a -bit parity generator circuit. Use only two assignment statements. Specify rise and fall delays as well. Apply Explain NMOS enhancement with conditions. Understand Design a Verilog module of a -bit bus switcher at the data flow level. Create 0 Design Verilog module of an edge triggered flip-flop built with the latch at the data flow level. Create UNIT-III BEHAVIORAL MODELING Write the syntax for the following constructs and give one example for each Apply P a g e

13 S.No QUESTIONS relevant to behavioral Verilog HDL modeling. (a). assign-deassign construct (b). repeat construct (c). for loop. Write the syntax for the following constructs and give one example for each relevant to behavioural Verilog HDL modeling. (a). The disable construct (b). While loop (c). force-release construct. Blooms Taxonomy Level Apply Program Outcome Explain about forever loop. Apply Define while loop, write syntax with flow chart. Remembering What is the difference between a sequential block and a parallel block? Explain using an example. (a) Design Verilog code of OR gate using for and disable. (b) Write simulation results of above question with explanation. Write syntax for for while loop and write a Verilog code for n bit Johnson counter. Evaluate creating Evaluate Explain event construct in a module. Understand Explain stratified event queue. Understand 0 Design Verilog module event construct for a serial data receive and test bench for the same. Create m UNIT-IV SWITCH LEVEL MODELING Explain automatic(re-entrant) tasks with example. Understand Explain and design Verilog module of timing related parameter with example. Understand Explain edge sensitive path using an example. Understand Explain overriding parameters. Understand Design Verilog module for left/right shifter. Create Design Verilog module using path delay. Create (a) Design Verilog module use of specify block to specify out rise end full time Create P a g e

14 S.No QUESTIONS Blooms Taxonomy Program separation for spin delays. (b)write test bench and simulation for the above. (a) Design the use of group delay with an ALU module. Create (b) Write test bench and simulation results for the above. What do you mean by User Defined Primitives (UDP) and explain the types with understand examples 0 Give the syntax for function and write a program for -to- multiplexer using unserstand function. UNIT-V SEQUENTIAL CIRCUIT DESCRIPTION Design a Verilog module for 0 moore detector and also obtain its test bench. Create How the simulation of test bench can be controlled? Explain with help of an Understanding example. Write a test bench for moore detector for synchronized data input. Understand Write a test bench for moore detector to display the synchronization result. Understanding Write a test bench for moore detector to observe its states. Understanding Write a Verilog module for 0 moore detector. Also obtain its test bench and Understanding 0 simulation results. Write an interactive test bench for 0 moore detector using display tasks. Understanding 0 Write a test bench for moore detector to control the delay. Understanding 0 Write a test bench for moore detector which makes uses of buffer to hold the Understanding 0 data. 0 Explain in detail about formal verification of a system. understand Write in detail about assertion verification. Also give its benefits. Understanding What is the function of assert_always monitor? Explain with the help of an Evaluate 0 example. Explain the assert_change and assert_one_hot monitor with the help of an Understand 0 example. What is the use of assert_cycle_sequence and assert next? Explain using an Evaluate 0 example. With the help of an example explain about the resetting sequqnce of controller. Evaluate 0 Explain the following, Understand (i) Initial resetting (ii) Assert_implication. How the valid states of a machine can be checked? Explain using an example. Understand 0 Prepared By: Mr. Khalandhar Basha P a g e

MLR Institute of Technology

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