Elementary Educational Computer

Transcription

1 Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified form cosistig of oly basic compoets. (.) Structure of the EEC preseted i Aex 5. (.3). Presetatio of the EEC uits.. Memory Uit (MU) Oe level memory cosistig of the Mai Memory (MM) Every locatio idetified by its ow address o k bits. Commuicatio with other uits through: a) MAR Memory Address Register b) MBR Memory Buffer Register or Memory Data Register Orgaizatio of the memory: k locatios of bits, thus k memory array Two operatios are allowed: ad WRITE, cotrolled by the Cotrol Uit Descriptio of the cycle ) Address placed i MAR ) cotrol sigal 3) Extractio from the addressed locatio 4) Store data i MBR 5- (..) (..) (..3) (..4) (..5) (..6) Descriptio of the WRITE cycle ) Address placed i MAR ) Data trasferred i MBR 3) WRITE cotrol sigal 4) Store data i the addressed locatio Types of WRITE ad commads issued by the Cotrol Uit: two idepedet(r,w) or oe commo (R / W ).. Arithmetic ad Logic Uit (ALU) 5- (..7) (..8) Implemets biary arithmetic o bits (..) Dimesio of ALU operatioal uits is assumed (..) All registers iside ALU are -dimesioal (..3) ALU cotais a simple register file ad a (..4) processig device Processig sectio cosists of a Adder/Subtractor (..5) ad a Shifter Register file cosists of a Accumulator, three auxiliary registers RX,, ad a Flag (..6) (Status) register () ALU performs a limited set of primitive (..7) operatios Commuicatio betwee ALU ad CU: CU seds the commads via cotrol lies, whereas ALU seds the status of the registers cotet (status (..8) sigals, flags, coditio sigals), usually of the Accumulator. Possible set of status bits: zero, parity, sig, (..9) overflow etc. Operads are extracted either from register file (local memory) or from MM. Extractio from (..0) MM implies a cycle. Role of the Accumulator: it is a special register commuicatig directly with the processig (..) device, that cotais oe of the operads ad where the result after processig is stored.

2 The Arithmetic ad Logic operatios performed i ALU are o oe or two operads (moadic or diadic operatios)..3. Cotrol Uit (CU) The CU is formed of the followig blocks: ) Program Couter (), o k bits ) Istructio Register (), o bits 3) Fuctio decoder (DEC L/ L ) 4) Cotrol Block (Logic Sequecer, Cotrol Sequecer) Program Couter cotais a memory address where the ext istructio to be executed is stored; sice the addressig space of MM is k, the dimesio of is k (idetical with the dimesio of MAR). has the icremetig facility, as well as a parallel load facility. Istructio Register () cotais the curret istructio which is i executio. The width of coicides with the width of a istructio ad i the case of EEC it is. is divided i two subregisters accordig to the format of the istructio. Structure of the : (..) (.3.) (.3.) (.3.3) (.3.4) (.3.5) (.3.6) The Address subregister cotais a address of the MM where oe operad is stored. I case of two operads operatio it is assumed that the other operad is i the Accumulator. For reaso of simplicity, there are missig the Fuctio Register ad the Address Register. Also, the address field cotais always the effective address of the operad (ot the logical address). The cetral role i the CU is played by the Cotrol Block (Cotrol Sequecer), which geerates the cotrol sigals for the other uits accordig to the operatio (fuctio) to be executed. The iputs i the Cotrol Block are the decoded (iterpreted) fuctio, master clock (from a Clock Geerator) ad status flags (from ALU). Cotrol Block is a complex sequetial machie, that is why it is also called Cotrol Sequecer..4. Iput/Output uits (I/O) I case of EEC the I/O system is composed of simple Iput/Output devices, at the lowest level a register o bits. They are commuicatig with the ALU (Accumulator) ad MM (MBR), as well as with the Cotrol Uit (Istructio Register). 3. The register structure of the EEC (.3.9) (.3.0) (.3.) (.3.) (.3.3) (.3.4) L K OODE ADDRESS SUBREGISTER SUBREGISTER The OODE subregister commuicates with the fuctio decoder to iterpret the curret istructio (to decide which fuctio must be executed) (.3.7) (.3.8) Ay digital system ca be viewed as a uio of geeralized registers ad the data paths itercoectig them. Eve the memory formed of k locatios ca be cosidered as formed of k registers, as each locatio is a -bit register. By mergig ALU with CU, to form the, the etire structure of the EEC ca be reduced to the followig set of registers (3.3): (3.) (3.)

3 AX AX AX3 x x y y y y z z z z k Addresses 0 zzzz k - Mai Memory WRITE x x y y y y IU OU (3.3) 4. Mode of operatio 4. Geeral cosideratios Accordig to the vo Neuma's priciples, both istructios ad data are located i memory, i biary coded form. Ay istructio is executed i two major phases FETCH phase, cosistig i extractig the curret istructio from the memory ad decodig the OODE field EXECUTE phase, cosistig i effective executio of the operatio o the defied operads (data). 4.. FETCH phase (4..) (4..) Where: = flag register (status register), o bits = Accumulator, o bits AX, AX, AX3 = auxiliary registers, o bits = Istructio Register, o bits (3.4) xx = the opcode field of the istructio, o L bits = the address field of the istructio, o k bits = Program Couter, o k bits IU = Iput uit, o bits OU = Output uit, o bits This register view of the EEC is useful for explaiig the flow of operatios that take place for executio of istructios. (3.5) The iitial address of the first istructio to be executed is already stored i (4..) The cotet of is trasferred to MAR. (4..) CU is issuig a commad to MM ad a read cycle is iitiated. (4..3) The cotet of the read locatio, represetig a Istructio, is trasferred to MBR. (4..4) From MBR the istructio is trasferred to from CU. (4..5) The subregister cotaiig OODE, o L bits, is trasferred to the Fuctio Decoder. (4..6) Fuctio Decoder decodes the OODE ad iforms the Cotrol Block of the CU, which, i tur, issues the (4..7) appropriate cotrol sigals to the other uits. CU is icremetig the to poit to the ext istructio. (4..8)

4 I a simplified RTL (Register Trasfer Laguage) the FETCH phase ca be described i the followig form:. MAR (). 3. (MBR) 4. DEC () OODE 5. ()+ 6. Go to EXECUTE phase (4..9) where: () OODE meas the cotet of the OODE subregister of the ; () meas the cotet of the ; (MBR) meas the cotet of the MBR. Schematically, this phase ca be represeted i the register view of the EEC as follows (4..) AX AX AX3 4 x x y y y y z z z z 5 3 zzzz Memory x x y y y y (4..0) (4..) IU OU 4.3. EXECUTE phase As stated before, the FETCH phase is commo for all Istructios, whereas EXECUTE phase is specific for (4.3.) each kid of Istructio. I what follows there are described extesively several simple Istructios that are executed i EEC. (4.3.) A) ADD, address This represets the additio of two operads Istructio, where the first operad is i the Accumulator, the secod operad is i the memory at the address (), while the sum is saved i the Accumulator. I a symbolic maer this operatio ca be described as follows: () + (Memory) ADDRESS The address () of the secod operad is give i the Istructio beig stored i the () ADDRESS subregister. The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito MAR, which meas trasfer ito MAR.. Iitiate a operatio from the locatio havig the address. 3. Trasfer of the extracted operad ito the ALU, i register RX. 4. Perform the additio betwee the cotets of ad AX, the store the result i the Accumulator 5. Chage the correspodig flags from the. 6. Go to the ext FETCH phase I RTL otatio:. MAR () ADDRESS. 3. (RX) (Memory) ADDRESS 4. () + (RX) 5. New flags 6. Go to FETCH phase (4.3.3) (4.3.4) (4.3.5) (4.3.6)

5 I the register view of the EEC the realizatio of ADD (4.3.7) Istructio is preseted i (4.3.8) Mai Memory NEW FLAGS RX OPERAND 3 OPERAND 4 4 result ADD (4.3.8) B) SUB, address This represets the subtractio operatio, where the subtrahed, that is the first operad, is i the Accumulator, while the miued, that is the secod (4.3.9) operad, is i the memory at the address specified explicitly i the istructio. The realizatio of the subtractio assumes readig from the memory of the secod operad ad trasferrig it ito the ALU, i the register RX. After that, the (4.3.0) subtractio takes place i the processig device ad the differece is saved i, accompaied by the correspodig chages of flags i the. Symbolically: () (Memory) ADDRESS (4.3.) The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito (4.3.) OPERAND MAR, which meas trasfer of ito MAR.. Iitiate a cycle, to extract the cotet of the locatio havig the address 3. Trasfer of the extracted operad i ALU, i the register RX. 4. The subtractio operatio takes place i the processig device by subtractig the cotet of RX from the cotet of ; the differece is saved i the Accumulator. 5. Chage the appropriate status bits i 6. Go to the ext FETCH phase. I RTL otatio:. MAR () ADDRESS. 3. RX (Memory) ADDRESS 4. () (RX) 5. New Flags 6. Go to FETCH phase I the register view the executio of SUB istructio is represeted i the ext figure (4.3.5) Mai Memory RX 4 NEW FLAGS OPERAND OPERAND 4 differece SUBTRACTION OPERAND (4.3.) (4.3.3) (4.3.4) (4.3.5)

6 C) LOAD, address The LOAD Istructio esures readig of a operad from the memory at the address () specified i the istructio ad trasferrig it ito the Accumulator. Symbolically: (Memory) ADDRESS The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito MAR, which meas trasfer ito MAR.. Iitiate a operatio from the locatio with the address. 3. Trasfer the extracted operad ito the ALU, i the Accumulator ad chage the flags from. 4. Go to the ext FETCH phase. I the register view of the EEC the realizatio of LOAD Istructio is preseted i the ext figure (4.3.0): RX NEW FLAGS OPERAND 4 3 Memory Uit OPERAND (4.3.6) (4.3.7) (4.3.8) (4.3.9) (4.3.0) Observatio: if i the OODE there is provided a subfield specifyig the destiatio register from the ALU, the there ca be defied variats of the LOAD istructio: RX (Memory) ADDRESS (Memory) ADDRESS (Memory) ADDRESS D) STORE, address The STORE Istructio esures the trasfer of the cotet of the Accumulator ito the memory ad storig it i the locatio havig the address () give i the istructio. Symbolically: Memory ADDRESS () The etire operatio takes place i the followig steps:. Trasfer the cotet of the () ADDRESS ito the MAR; the cotet of MAR becomes.. Trasfer the cotet of the Accumulator ito the MBR; i this way the operad is prepared for further storig i the memory. 3. Iitiate a WRITE operatio, realisig storig of the cotet from the MAR ito the locatio with the address. 4. Go to the ext FETCH phase. I the register view of the EEC this istructio is represeted i (4.3.6): (4.3.) (4.3.) (4.3.3) (4.3.4) (4.3.5) 5-5-

7 RX Mai Memory WRITE 3 I the register view of EEC represetatio the executio of this istructio is give i (4.3.30): Memory RX OPERAND OPERAND (4.3.6) (4.3.30) Observatio: The STORE Istructio ca preset variatios by icludig i the OODE a subfield specifyig the source register from ALU; i this way, the cotet of RX, or ca be stored i the memory at the specified address give i the Istructio (Memory) ADDRESS (RX) (Memory) ADDRESS () (Memory) ADDRESS () E) JUMP, address This is a ucoditioal JUMP at the address specified i the Istructio. The implemetatio is quite simple by trasferrig the address from the () ADDRESS ito the. I this way, istead of usig the address (), the address () will be used i the ext FETCH phase for extractig the ext istructio from the memory. The executio of this ucoditioal JUMP Istructio is very simple:. () () ADDRESS. Go to the ext FETCH phase. (4.3.7) (4.3.8) (4.3.9) F) Coditioal JUMP, address The coditioal JUMP Istructio tests a coditio ad if it is true the a jump takes place at the give address i the Istructio; otherwise the ormal flow of executio cotiues, that is the cotet of remais ualtered, so that the ext FETCH will take place at the address (). The test operatio cosists i checkig a flag (a coditio bit) from the Flag Register,. As metioed before, amog the usual flags the followig are commo: ZERO flag if the cotet of the Accumulator is 0 SIGN flag reproducig the most sigificat bit of the Accumulator (if it is 0, the a positive umber is i the, if it is, the a egative umber is i the ) Istructio to be fetched (4.3.3) (4.3.3)

8 PARITY flag shows if the umber of s i the Accumulator is odd or eve CARRY flag if after a additio/subtractio (4.3.3) operatio it was geerated a carry from the most sigificat colum. The OODE for this coditioal JUMP will cotai a subfield to idetify which flag is to be tested; thereby (4.3.33) there are may Coditioal JUMP Istructios depedig o how may flags are defied i the architecture. Symbolically, (4.3.34) If (coditio) go to (address) else () The steps of implemetig these istructios are:. Test the flag defied by the OODE. If the coditio is TRUE the trasfer the address (4.3.35) from () ADDRESS ito the, ad go to 4 3. If the coditio is FALSE the go to 4 4. Go to ext FETCH phase. I the register view of the EEC represetatio (4.3.37): (4.3.36) Memory RX Fj flag idetificatio switch / TRUE 5-5 Next Istructio for FALSE cod Next Istructio for TRUE cod (4.3.37) G) INPUT, address The address field would specify oe of the set of Iput Registers represetig the INPUT UNIT. I this particular case it was used a simple iput register, therefore the address field is irrelevat. But, i geeral case, there are defied k differet addresses of iput registers. This Istructio reads the cotet of the addressed register 5-6 (4.3.38) (4.3.39) ad trasfers it ito the, i the Accumulator. Thus, symbolically: (4.3.40) (Iput Register) ADDRESS The steps of implemetatio:. Idetify the Iput Register from the address stored i () ADDRESS. the addressed Iput Register ad trasfer its cotet ito the. 3. Go to ext FETCH phase. I the register view of the EEC the executio of this istructio is preseted i (4.3.43): Memory RX dddddd (4.3.4) (4.4.4) (4.3.43) Iput Register dddddd Output Register

9 H) OUPUT, address The address field would specify oe of the set of Output Registers represetig the Output Uit. I this particular case of EEC there is provided a sigle Output Register, so that the address field has o sigificace. I geeral case, there ca be defied k differet addresses of Output Registers. This istructio trasfers the cotet of the Accumulator to the addressed Output Register ad writes it i. Thus, symbolically: Output Register ADDRESS () The steps of the implemetatio:. Idetify the Output Register from the address existig i () ADDRESS. Trasfer the operad from to the idetified Output Register ad write it i the register. 3. Go to ext FETCH phase. I the register view of the EEC the executio of this istructio is preseted i (4.3.50): Mai Memory (4.3.44) (4.3.45) (4.3.46) (4.3.47) (4.3.48) (4.3.49) RX dddddd 5-7 WRITE (4.3.50) Iput Register Output Register dddddd