Virtual Memory 1. To do. q Segmentation q Paging q A hybrid system

Transcription

1 Virtual Memory 1 To do q Segmentation q Paging q A hybrid system

2 Address spaces and multiple processes IBM OS/360 Split memory in n parts (possible!= sizes) A process per partition Program Code Heap Operating System Partition 1 Partition K 128K (free) Stack Partition 3 Partition 4 256K 320K 512K How do deal with large address spaces with potentially a lot of free space? 2

3 The overlay solution Split programs into pieces (overlays), keep in memory only what s needed Overlay approach (~1960s) Swapping was done by the OS, but Splitting was done manually by the user Easy on the OS, hard on programmers Overlay for a two-pass assembler: Pass 1 70KB Pass 2 80KB Symbol Table 20KB Common Routines 30KB Total 200KB Two overlays: KB 70K Pass 1 Symbol tables Common routines Overlay driver 20K 30K 10K Pass 2 80K 3

4 Virtual memory Goals Transparency Programs should not know that memory is virtualized Program flexibility processes can run in machines with less physical memory than they need Efficiency Both in time and space; not making processes too slow and using physical memory efficiently Protection Isolating processes from each other; i.e., a process should not be able to access the memory of any other or the OS itself 4

5 Virtual memory Segmentation Hide the complexity, let the OS do the job How? A related idea, to generalize base/limit Each segment can grow independently Only used space is allocated Yes, segmentation fault (segfault) comes from this! Stack <base> <limit> Program Code Heap (free) Heap <base> <limit> Code <base> <limit> Stack Stack Heap Program Code 5

6 Which segment? How does the HW know which segment an address refers to? Explicit approach With three segments, use two bits of the virtual address The rest are offset into the segment // Get segment number Segment = (VirtAddr & SEG_MASK) >> SEG_SHIFT; // Now get offset Offset = VirtAddr & OFFSET_MASK; if (Offset >= Limit[Segment]) /* protection fault */ else PhysAddr = Base[Segment] + Offset Segment Offset... Implicit how was the address formed? PC? Code segment; from the stack or base pointer? Stack... 6

7 Sharing and fragmentation With a little bit more HW support sharing memory segments (e.g., code) Just a few bits per segments for read/write/execute rights Rather than code, stack, finer grain segmentation OS can keep track of segments in use and manage memory more efficiently A segment table to track them Need more HW support Many small variable-sized segments External fragmentation! Compaction is expensive, free-list management may help a bit 7

8 And then came paging Avoid fragmentation from variable-sized blocks Use fixed-sized blocks pages Virtual address space split into pages Each a contiguous range of addresses Physical memory split into page frames Virtual memory Page 0 Page 1 Page 2 Pages mapped to page frames Physical memory Page frame 0 Page frame 1 Page N Page frame M 8

9 Virtual memory paging Pages and page frames are, typically, = size Many processors support multiple page sizes (e.g., x86-64: 4KB, 2MB, 1GB) Pages are mapped onto frames Doing the translation OS + MMU Key not all pages have to be in at once If page is in memory, system does the mapping else, OS is told to get the missing page and re-execute the failed instruction 9

10 Paging Good for everyone For developers Memory seems a contiguous address space with size independent of hardware Simple and flexible no assumptions on how memory is used For memory manager Physical memory can be used efficiently with minimal internal (small units) & no external fragmentation (fixed size units) Protection is easy since processes can t access each other s memory 10

11 Address translation with paging Virtual to physical address Two parts virtual page number and offset Virtual Page # Offset Virtual page number index into a page table Page table maps virtual pages to page frames Managed by the OS One entry per page in virtual address space Physical address page number and offset 11

12 Address translation with paging Virtual address Virtual page # offset Page table Physical memory Page frame 0 Page frame # Physical address Page frame # offset Page frame i Page frame N Each process has its own page table 12

13 Translation in action MMU with 16 4KB pages Page # (first 4 bits) index into page table If not there Page fault Else Output register + 12 bit offset 15 bit physical address Physical Page # Offset Present Bit Virtual Page # Offset 13

14 Pages, page frames and tables A simple example with 64KB virtual address space 4KB pages 32KB physical address space 16 pages and 8 page frames Virtual address space 60-64K X 56-60K X Try to access : MOV REG, 0 Virtual address 0 Page frame 2 Physical address K X 48-52K X 44-48K K X 36-40K K X 28-32K X 24-28K X 20-24K K K K 6 4-8K 1 0-4K 2 Physical memory address 28-32K 24-28K 20-24K 16-20K 12-16K 8-12K 4-8K 0-4K 14

15 Pages, page frames and tables A simple example with 64KB virtual address space 4KB pages 32KB physical address space 16 pages and 8 page frames Virtual address space 60-64K X 56-60K X Try to access : MOV REG, 8192 Virtual address 8192 Page frame 6 Physical address MOV REG, Virtual address ( ) Page frame 3 Physical address K X 48-52K X 44-48K K X 36-40K K X 28-32K X 24-28K X 20-24K K K K 6 4-8K 1 0-4K 2 Physical memory address 28-32K 24-28K 20-24K 16-20K 12-16K 8-12K 4-8K 0-4K 15

16 Since virtual memory >> physical memory Use a present/absent bit MMU checks If not there, page fault to the OS (trap) OS picks a victim (?) sends victim to disk brings new one updates page table MOVE REG, Virtual address Virtual page 8, byte 12 ( ) Page is unmapped page fault! Virtual address space 60-64K X 56-60K X 52-56K X 48-52K X 44-48K K X 36-40K K X 28-32K X 24-28K X 20-24K K K K 6 4-8K 1 0-4K 2 Physical memory address 28-32K 24-28K 20-24K 16-20K 12-16K 8-12K 4-8K 0-4K 16

17 Page table entry An opportunity there s a PTE lookup per memory ref., what else can we do with it? Looking at the details Caching disabled Modified Present/absent Page frame number Referenced Protection Page frame number the most important field Protection 1 bit for R&W or R or 3 bits for RWX 17

18 Page table entry Looking at the details Caching disabled Modified Present/absent Page frame number Referenced Protection Present/absent bit Says whether or not the virtual address is used Modified (M): dirty bit Set when a write to the page has occurred Referenced (R): Has it being used? To ensure we are not reading from cache (D) Key for pages that map onto device registers rather than memory 18

19 Segmentation and paging Segmentation pros and cons It s more logical Facilitates sharing and reuse But all the problems of variable partitions Paging pros and cons Easy to allocate physical memory Naturally leads to virtual memory Address translation time Page tables can be large 19

20 Segmentation w/ paging - MULTICS Large segment? Page them MULTICS, x86 and x86-64 MULTICS: process virtual memory 2 18 segments of ~64K words (36-bit) Each process has a segment table (itself a paged segment) Segment table address found in a Descriptor Base Register; one entry per segment Descriptor segment. Segment desc. Segment desc. Segment desc. Segment desc. Segment desc. Segment desc. Segment desc. 20

21 Segmentation w/ paging - MULTICS Most (but not all) segments are paged Segment descriptor indicates if in memory and points to page table Address of segment in secondary memory in another table Segment # to get segment descriptor Virtual Address Segment # (18b) Page Segment # (6b) offset Offset # (16b) (10b) Descriptor segment Page table. Page entry. Page entry Address within the segment Segment desc. Segment desc. Segment desc. Page entry. Page entry Page entry Page entry 21

22 Segmentation w/ paging - MULTICS If segment in mem, segment s page table is in memory Protection violation? Fault Look at the page table s entry - is page in memory? Page fault Add offset to page origin to get word location to speed things up cache (TLB, first system) Segment Descriptor Main memory address of the page table Segment length (in pages) Page size words 1 = 64 words Segment paged? Misc bits Protection bits 22

23 Next considerations with page tables Two key issues with page tables Mapping must be fast Done on every memory reference, at least 1 per instruction With large address spaces, page tables will be large 32b & 4KB page 12 bit offset, 20 bit page # ~ 1million PTE 64b & 4KB page 2 12 (offset) pages ~ 4.5x10 15!!! Simplest solutions Page table in registers Fast during execution, $$$ & slow to context switch Page table in memory & Page Table Base Register (PTBR) Fast to context switch & cheap, but slow during execution 23

24 And now a short break xkcd 24