Computer Science 141 Computing Hardware

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1 Compute Science 141 Computing Hadwae Fall 2006 Havad Univesity Instucto: Pof. David Books [MIPS Pipeline Slides adapted fom Dave Patteson s UCB CS152 slides and May Jane Iwin s CSE331/431 slides]

2 Review: Single Cycle Data and Contol Path 4 Add Inst[25-0] 26 Op Inst[31-26] Shift left 2 Contol PC+4[31-28] Jump Banch Sc Shift left 2 Add PCSc MemRead MemtoReg MemWite PC Read Addess Instuction Memoy Inst[31-0] RegDst Inst[25-21] Inst[20-16] 0 1 Inst[15-11] RegWite Read Add 1 Registe Read Read Add 2 Data 1 File Wite Add Read Data 2 Wite Data 0 1 ovf zeo Addess Data Memoy Wite Data Read Data 1 0 Inst[15-0] Sign 16 Extend 32 contol Inst[5-0]

3 Disadvantages of the Single Cycle Datapath Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instuction especially poblematic fo moe complex instuctions like floating point multiply Is wasteful of aea since some functional units must be duplicated since they can not be shaed duing an instuction execution e.g., need sepaate addes to do PC update and banch taget addess calculations, as well as an to do R-type aithmetic/logic opeations and data memoy addess calculations

4 Review: Multicycle Data and Contol Path PCWiteCond PCWite IoD MemRead MemWite MemtoReg IRWite Contol FSM ScA RegWite RegDst PCSouce Op ScB PC 0 1 Addess Wite Data Memoy Read Data (Inst. o Data) IR MDR Inst[31-26] Inst[15-0] Inst[5-0] Read Add 1 Registe Read Read Add 2 Data 1 File Wite Add Read Data 2 Wite Data Sign Extend 32 Inst[25-0] Shift left 2 A B PC[31-28] Shift left 2 zeo contol 28 out 2 0 1

5 Review: RTL Summay Step Inst fetch Decode Execute Memoy access R-type Mem Ref Banch Jump IR = Memoy[PC]; PC = PC + 4; A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; Out = PC +(sign-extend(ir[15-0])<< 2); Out = A op B; Witeback Reg[IR[15-11]] = Out; Out = A + sign-extend (IR[15-0]); MDR = Memoy[Out]; o Memoy[Out] = B; Reg[IR[20-16]] = MDR; if (A==B) PC = Out; PC = PC[31-28] (IR[25-0] << 2);

6 Stat PCWite,IRWite, MemWite,RegWite=0 othes=x Review: Multicycle Datapath FSM Unless othewise assigned 2 ScA=1 ScB=10 Op=00 PCWiteCond=0 3 (Op = lw) MemRead IoD=1 PCWiteCond=0 (Op = sw) Memoy Access (Op = lw o sw) Execute 0 IoD=0 Inst Fetch 1 5 MemWite IoD=1 PCWiteCond=0 MemRead;IRWite ScA=0 scb=01 PCSouce,Op=00 PCWite 6 ScA=1 ScB=00 Op=10 PCWiteCond=0 7 RegDst=1 RegWite MemtoReg=0 PCWiteCond=0 (Op = R-type) 8 9 ScA=1 ScB=00 Op=01 PCSouce=01 PCWiteCond (Op = beq) (Op = j) Decode ScA=0 ScB=11 Op=00 PCWiteCond=0 PCSouce=10 PCWite 4 RegDst=0 RegWite MemtoReg=1 PCWiteCond=0 Wite Back

7 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instuction Clk Cycle 1 Cycle 2 Single Cycle Implementation: lw sw Waste Is wasteful of aea since some functional units must (e.g., addes) be duplicated since they can not be shaed duing a clock cycle but Is simple and easy to undestand

8 Multicycle Advantages & Disadvantages Uses the clock cycle efficiently the clock cycle is timed to accommodate the slowest instuction step balance the amount of wok to be done in each step estict each step to use only one majo functional unit Multicycle implementations allow functional units to be used moe than once pe instuction as long as they ae used on diffeent clock cycles faste clock ates diffeent instuctions to take a diffeent numbe of clock cycles but Requies additional intenal state egistes, muxes, and moe complicated (FSM) contol

9 The Five Stages of Load Instuction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 lw IFetch Dec Exec Mem WB IFetch: Instuction Fetch and Update PC Dec: Registes Fetch and Instuction Decode Exec: Execute R-type; calculate memoy addess Mem: Read/wite the data fom/to the Data Memoy WB: Wite the data back to the egiste file

10 Single Cycle vs. Multiple Cycle Timing Single Cycle Implementation: Clk Cycle 1 Cycle 2 lw sw Waste Multiple Cycle Implementation: multicycle clock slowe than 1/5 th of single cycle clock due to stage flipflop ovehead Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch

11 Pipelined MIPS Pocesso Stat the next instuction while still woking on the cuent one impoves thoughput - total amount of wok done in a given time Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB instuction latency (execution time, delay time, esponse time) is not educed - time fom the stat of an instuction to its completion

12 Single Cycle, Multiple Cycle, vs. Pipeline Single Cycle Implementation: Clk Cycle 1 Cycle 2 Load Stoe Waste Multiple Cycle Implementation: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 Clk lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Pipeline Implementation: lw IFetch Dec Exec Mem WB wasted cycle sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB

13 What makes it easy Pipelining the MIPS ISA all instuctions ae the same length (32 bits) can fetch in the 1 st stage and decode in the 2 nd stage few instuction fomats (thee) with symmety acoss fomats can begin eading egiste file in 2 nd stage memoy opeations can occu only in loads and stoes can use the execute stage to calculate memoy addesses each MIPS instuction wites at most one esult (i.e., changes the machine state) and does so nea the end of the pipeline (MEM and WB) What makes it had stuctual hazads: what if we had only one memoy? contol hazads: what about banches? data hazads: what if an instuction s input opeands depend on the output of a pevious instuction?

14 1 0 MIPS Pipeline Datapath Modifications What do we need to add/modify in ou MIPS datapath? State egistes between pipeline stages to isolate them IFetch Dec Exec Mem WB Add PC 4 Instuction Memoy Read Addess IFetch/Dec Read Add 1 Registe Read Read Add 2Data 1 File Wite Add Read Data 2 Wite Data Dec/Exec Shift left Add Exec/Mem Data Addess Memoy Wite Data Read Data Mem/WB 1 0 System Clock Sign 16 Extend 32

15 Coected Datapath to Save RegWite Add Need to peseve the destination egiste addess in the pipeline state egistes IF/ID ID/EX EX/MEM Add PC 4 Instuction Memoy Read Addess Read Add 1 Registe Read Read Add 2Data 1 File Wite Add Read Data 2 Wite Data Shift left 2 Add Addess Wite Data Data Memoy Read Data MEM/WB Sign 16 Extend 32

16 MIPS Pipeline Contol Path Modifications All contol signals can be detemined duing Decode and held in the state egistes between pipeline stages ID/EX EX/MEM IF/ID Contol PC 4 Instuction Memoy Read Addess Add Read Add 1 Registe Read Read Add 2Data 1 File Wite Add Read Data 2 Wite Data Shift left 2 Add Addess Wite Data Data Memoy Read Data MEM/WB Sign 16 Extend 32

17 Gaphically Repesenting MIPS Pipeline Can help with answeing questions like: how many cycles does it take to execute this code? what is the doing duing cycle 4? is thee a hazad, why does it occu, and how can it be fixed?

18 Why Pipeline? Fo Pefomance! Time (clock cycles) I n s t. O d e Inst 0 Inst 1 Inst 2 Inst 3 Once the pipeline is full, one instuction is completed evey cycle, so CPI = 1 Inst 4 Time to fill the pipeline

19 Can Pipelining Get Us Into Touble? Yes: Pipeline Hazads stuctual hazads: attempt to use the same esouce by two diffeent instuctions at the same time data hazads: attempt to use data befoe it is eady An instuction s souce opeand(s) ae poduced by a pio instuction still in the pipeline contol hazads: attempt to make a decision about pogam contol flow befoe the condition has been evaluated and the new PC taget addess calculated banch instuctions Can always esolve hazads by waiting pipeline contol must detect the hazad and take action to esolve hazads

20 A Single Memoy Would Be a Stuctual Hazad Time (clock cycles) I n s t. lw Inst 1 Mem Reg Mem Reg Mem Reg Mem Reg Reading data fom memoy O d e Inst 2 Inst 3 Mem Reg Mem Reg Mem Reg Mem Reg Inst 4 Reading instuction fom memoy Mem Reg Mem Reg Fix with sepaate inst and data memoies (I$ and D$)

21 How About Registe File Access? Time (clock cycles) I n s t. add $1, Inst 1 O d e Inst 2 add $2,$1,

22 One Way to Fix a Data Hazad I n s t. O d e add 1,2,3

23 Anothe Way to Fix a Data Hazad I n s t. add 1, sub 4,1,5 Fix data hazads by fowading esults as soon as they ae available to whee they ae needed O d e and 6,1,7 o 8,1,9 xo 4,1,5

24 Fowading with Load-use Data Hazads I n s t. O d e lw 1,4(2) sub 4,1,5 and 6,1,7 o 8,1,9 xo 4,1,5

25 Banch Instuctions Cause Contol Hazads Dependencies backwad in time cause hazads I n s t. O d e add beq lw Inst 3 Inst 4

26 One Way to Fix a Contol Hazad I n s t. O d e add beq

27 Othe Pipeline Stuctues Ae Possible What about (slow) multiply opeation? let it take two cycles MUL What if the data memoy access is twice as slow as the instuction memoy? make the clock twice as slow o let data memoy access take two cycles (and keep the same clock ate) IM Reg DM1 DM2 Reg

28 Sample Pipeline Altenatives ARM7 IM Reg EX StongARM-1 PC update IM access decode eg access op DM access shift/otate commit esult (wite back) XScale PC update BTB access stat IM access IM1 IM2 Reg DM1 Reg SHFT DM2 IM access decode eg 1 access op shift/otate eg 2 access DM wite eg wite stat DM access exception

29 Summay All moden day pocessos use pipelining Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe of pipe stages Pipeline ate limited by slowest pipeline stage Unbalanced lengths of pipe stages educes speedup Time to fill pipeline and time to dain it educes speedup Must detect and esolve hazads Stalling negatively affects thoughput

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