Lecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón

Transcription

1 ICS 152 Computer Systems Architecture Prof. Juan Luis Aragón Lecture 5 and 6 Multicycle Implementation Introduction to Microprogramming Readings: Sections 5.4 and 5.5 1

2 Review of Last Lecture We have seen one implementation of the MIPS ISA First approach: single-clock cycle Datapath design ALU Control Unit design Main Control Unit design Problems of the Single-Clock Cycle Implementation Clock cycle is equal to the slowest instruction FU duplication There are more efficient approaches Multicycle implementation 2

3 Multicycle Implementation Overview The execution of an instruction can be broken up into multiple steps Each step takes 1 shorter clock cycle Now, each instruction takes more than 1 clock cycle We will be sharing functional units ALU used to compute branch target address and to increment PC Memory used for instruction and data More complex Control Unit We ll use a finite state machine for control 3

4 Multicycle Datapath Overview Modified Multicycle Datapath Only 1 Memory Unit and 1 ALU Introduce internal registers since at the end of a cycle some results must be stored for use in later cycles Requires additional multiplexers PC 0 M ux 1 Address Write data Memory MemData Instruction [25 21] Instruction [20 16] Instruction [15 0] Instruction register Instruction [15 0] Instruction [15 11] 0 M u x 1 0 M ux Read register 1 Read register 2 Registers Write register Write data Read data 1 Read data 2 A B 4 0 M ux M ux 2 3 Zero ALU ALU result ALUOut Memory data register 1 16 Sign extend 32 Shift left 2 4

5 Multicycle Datapath and Control Units New Control Signals For new/extended multiplexers IR and PC registers (what about the others? ) PC 0 M u x 1 Address Write data Memory MemData Instruction [31-26] Instruction [25 21] Instruction [20 16] Instruction [15 0] Instruction register Instruction [15 0] Memory data register PCWriteCond PCWrite IorD Outputs MemRead MemWrite Control MemtoReg IRWrite Instruction [25 0] Instruction [15 11] Op [5 0] 0 M u x 1 0 M u x 1 PCSource ALUOp ALUSrcB ALUSrcA RegDst 16 RegWrite Read register 1 Read register 2 Registers Write register Write data Sign extend Read data 1 Read data 2 32 Shift left 2 A B 4 0 M u x M u 2 x Shift left 2 ALU control PC [31-28] Zero ALU ALU result Jump address [31-0] ALUOut M u x Instruction [5 0] 5

6 Breaking the Execution into Clock Cycles Goal: balance the amount of work done in each cycle Why? Restrictions: each step should contain at most 1 ALU operation 1 register file access 1 memory access What if we allow using 2 FUs in 1 cycle? Remember: at the end of each cycle all generated outputs must be stored for the next cycle in either A major state element (PC, register file, memory) An internal register (IR, MDR, A, B, ALUOut) 6

7 Five Execution Steps Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R-type instruction completion Write-back step (only loads) 7

8 Step 1: Instruction Fetch Use PC to get instruction and put it in IR Increment the PC by 4 and put the result back in the PC IR = Memory[PC]; PC = PC + 4; Control signals MemRead = 1 IRWrite = 1 IorD = 0 (selects the PC to access memory) ALUSrcA = 0 (selects the PC as ALU s first operand) ALUSrcB = 01 (selects 4 as ALU s second operand) ALUOp = 00 (selects addition) PCWrite = 1 PCSource = 00 (selects the PC+4) 8

9 Step 2: Instruction Decode and Register Fetch Remember: we still don t know the instruction type We perform not harmful operations Read registers rs and rt in case we need them Compute the branch address in case of a branch A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(ir[15-0]) << 2); Control signals ALUSrcA = 0 (selects the PC as ALU s first operand) ALUSrcB = 11 (selects the sign-extended/shifted offset as 2 nd ) ALUOp = 00 (selects addition) After this step we KNOW the instruction type 9

10 Step 3: Execution (instruction dependent) Memory Reference: ALUOut = A + sign-extend(ir[15-0]); Control signals ALUSrcA = 1 (selects register A as ALU s first operand) ALUSrcB = 10 (selects the sign-extended offset as 2 nd ) ALUOp = 00 (selects addition) R-type: ALUOut = A op B; Control signals ALUSrcA = 1 (selects register A as ALU s first operand) ALUSrcB = 00 (selects register B as ALU s second operand) ALUOp = 10 (ALU operation depends on funct field) 10

11 Step 3: Execution (instruction dependent) Branch: if (A==B) PC = ALUOut; Control signals ALUSrcA = 1 (selects register A as ALU s first operand) ALUSrcB = 00 (selects register B as ALU s second operand) ALUOp = 01 (selects subtraction) PCSource = 01 (PC comes from ALUout) PCWriteCond = 1 (PC modified if the Zero output is asserted) Jump: PC = PC [31-28] (IR[25-0] <<2); Control signals PCSource = 10 (PC comes from jump target address) PCWrite = 1 (PC is written) 11

12 Step 4: Memory-access or R-type Completion LOADS: MDR = Memory[ALUOut]; MemRead = 1, IorD = 1 STORES: Memory[ALUOut] = B; MemWrite = 1, IorD = 1 R-type instructions finish Reg[IR[15-11]] = ALUOut; RegDst = 1 (destination register comes from rd) RegWrite = 1 (a register is written) MemtoReg = 0 (data to be written comes from ALUout) 12

13 Step 5: Memory Read Completion Loads write-back the value from memory Reg[IR[20-16]]= MDR; Control signals RegDst = 1 (destination register comes from rd) RegWrite = 1 (a register is written) MemtoReg = 0 (data to be written comes from ALUout) What about all the other instructions? 13

14 Summary: Remember: instructions take from 3 to 5 steps Step name Action for R-type instructions Action for memory-reference instructions Action for branches Action for jumps Instruction fetch IR = Memory[PC] PC = PC + 4 Instruction decode/register fetch A = Reg [IR[25-21]] B = Reg [IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Execution, address computation, branch/ jump completion ALUOut = A op B ALUOut = A + sign-extend (IR[15-0]) if (A ==B) then PC = ALUOut PC = PC[31-28] II (IR[25-0]<<2) Memory access or R-type completion Reg[ IR[15-11] ] = ALUOut Load: MDR = Memory[ALUOut] or Store: Memory[ALUOut] = B Memory read completion Load: Reg[ IR[20-16] ] = MDR 14

15 Implementing the Control Unit Value of control signals is dependent upon: What instruction is being executed Which step is being performed Use the information we ve accumulated to specify a Finite State Machine Specify the finite state machine graphically, or Use microprogramming Implementation can be derived from specification Gates PLAs ROMs 15

16 Review: Finite State Machines Finite State Machines (FSM) a set of states and next state function (determined by current state and the input) output function (determined by current state and possibly input) Combinational logic Outputs Next state State register Inputs We ll use a Moore machine (output based only on current state) 16

17 Control Unit: Overview Overview Implements the five execution steps Each step will take 1 cycle Start Instruction fetch/decode and register fetch (Figure 5.37) Memory access instructions (Figure 5.38) R-type instructions (Figure 5.39) Branch instruction (Figure 5.40) Jump instruction (Figure 5.41) 17

18 Control Unit: Fetch and Decode First two steps: Independent of the instruction class Start 0 MemRead ALUSrcA = 0 IorD = 0 IR W rite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 Instruction fetch Instruction decode/ Register fetch 1 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 ( O p = 'L W ') o r ( O p = 'S W ') (O p = R -t y p e ) (O p = 'B E Q ') (Op = 'JM P') M em ory reference FS M (Figure 5.38) R-type FSM (Figure 5.39) Branch FSM (Figure 5.40) Jump FSM (Figure 5.41) 18

19 Control Unit: Memory and R-type Execution Memory Reference 2 3 From state 1 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 (Op = 'LW') MemRead IorD = 1 (Op='LW')or(Op='SW') Memory address computation Memory access (Op = 'SW') 5 MemWrite IorD = 1 Memory access 6 7 R-type From state 1 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0 (Op = R-type) Execution R-type completion 4 Write-back step RegWrite MemtoReg = 1 RegDst = 0 To state 0 (Figure 5.37) To state 0 (Figure 5.37) 19

20 Control Unit: Complete FSM 2 Memory address computation ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Start Instruction fetch 0 MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 6 (Op = 'LW') or (Op = 'SW') Execution ALUSrcA =1 ALUSrcB = 00 ALUOp= 10 8 (Op = R-type) Branch completion ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 Instruction decode/ register fetch 1 (Op = 'BEQ') 9 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 (Op = 'J') Jump completion PCWrite PCSource = 10 3 (Op = 'LW') Memory access (Op = 'SW') 5 Memory access 7 R-type completion MemRead IorD = 1 MemWrite IorD = 1 RegDst = 1 RegWrite MemtoReg = 0 4 Write-back step RegDst=0 RegWrite MemtoReg =1 20

21 Control Unit Implementation Implementation Overview: Control logic Inputs Outputs PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst NS3 NS2 NS1 NS0 Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0 Instruction register opcode field State register 21

22 PLA Implementation Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource1 PCSource0 ALUOp1 ALUOp0 ALUSrcB1 ALUSrcB0 ALUSrcA RegWrite RegDst NS3 NS2 NS1 NS0 22

23 Microprogramming A graphical representation is adequate when There are few instructions What about if we want to implement the full MIPS ISA? The control specification will be very complex Solution: Use some ideas from programming to specify control Microinstruction: Defines the set of control signals that must be asserted We must specify the sequencing of microinstructions Sequential Non-sequential (branches inside the Microprogram) Microprogram: A symbolic representation of the control using microinstructions 23

24 Microinstruction Format Format: Each microinstruction is composed of several fields Each field controls one or several control signals Goal: Simplify the representation Make the Microprogram easy to read We are using 7 fields: Label ALU Control SRC1 SRC2 Regist. Control Memory PCWrite Control Sequen. Can you figure out the purpose of each field? 24

25 Microinstruction Format SRC1 Field name Value Signals active Comment ALU control SRC2 Register control Memory PC write control Sequencing Add ALUOp = 00 Cause the ALU to add. Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for branches. Func code ALUOp = 10 Use the instruction's function code to determine ALU control. PC ALUSrcA = 0 Use the PC as the first ALU input. A ALUSrcA = 1 Register A is the first ALU input. B ALUSrcB = 00 Register B is the second ALU input. 4 ALUSrcB = 01 Use 4 as the second ALU input. Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input. Extshft Read ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input. Read two registers using the rs and rt fields of the IR as the register numbers and putting the data into registers A and B. RegWrite, Write a register using the rd field of the IR as the register number and Write ALU RegDst = 1, the contents of the ALUOut as the data. MemtoReg = 0 RegWrite, Write a register using the rt field of the IR as the register number and Write MDR RegDst = 0, the contents of the MDR as the data. MemtoReg = 1 Read PC Read ALU Write ALU ALU ALUOut-cond jump address MemRead, Read memory using the ALUOut as address; write result into MDR. lord = 1 PCSource = 00 Write the output of the ALU into the PC. PCWrite PCSource = 10, Write the PC with the jump address from the instruction. PCWrite MemRead, MemWrite, PCSource = 01, Read memory using the PC as address; write result into IR (and Write memory using the ALUOut as address, contents of B as the If the Zero output of the ALU is active, write the PC with the contents lord = 0 lord = 1 PCWriteCond the MDR). data. of the register ALUOut. Seq AddrCtl = 11 Choose the next microinstruction sequentially. Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction. Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1. Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2. 25

26 Creating the Microprogram Step 1: Instruction Fetch Step 2: Instruction Decode and Register Fetch Label ALU SRC1 SRC2 Regist. Memory PCWrite Sequen. Control Control Control Fetch Add PC 4 Read PC ALU Seq Add PC Extshift Read Dispatch 1 Remember: how to choose the next instruction Sequencing field = Seq Sequencing field = Fetch Sequencing field = Dispatch i (Access ROM i using the Opcode) 26

27 Creating the Microprogram Memory-Reference Instructions Step 3 (address calculation): LW and SW Step 4 (memory access): LW and SW Step 5 (write-back): only LW Label ALU SRC1 SRC2 Regist. Memory PCWrite Sequen. Control Control Control Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch 27

28 Creating the Microprogram R-type Instructions Step 3: ALU operation Step 4: Write-back Branch and Jump Instructions Step 3: Comparison and write next PC (branches) Step 3: Write next PC (jumps) Label ALU SRC1 SRC2 Regist. Memory PCWrite Sequen. Control Control Control Rformat1 FuncCode A B Seq Write ALU Fetch BEQ1 Subt A B ALUout cond JUMP1 Jump address Fetch Fetch 28

29 Complete Microprogram A symbolic representation of the control using just 10 microinstructions! Label ALU SRC1 SRC2 Regist. Memory PCWrite Sequen. Control Control Control Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1 Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch Rformat1 FuncCode A B Seq Write ALU Fetch BEQ1 Subt A B ALUout Fetch cond JUMP1 Jump address Fetch 29

30 Implementing the Microprogram Translate each Microinstruction to the corresponding bit pattern of control signals (PLAs, ROMs, ) Use a Sequencer and a Microprogram Counter Control unit Microcode memory Input Outputs PCWrite PCWriteCond IorD MemRead MemWrite IRWrite BWrite MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst AddrCtl Datapath 1 Microprogram counter Adder Address select logic Op[5 0] Instruction register opcode field 30

31 Summary We have seen the Multicycle Implementation The execution of an instruction is broken up into multiple steps Each step takes 1 shorter clock cycle Shared Functional Units We have modified the Datapath accordingly We implemented the Main Control Unit using either Finite State Machine Adequate for few instructions Microprogramming Symbolic representation of the control signals Easier to implement Now, let us see how to improve the Multicycle Implementation 31

32 End of Lecture 32