CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

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1 CS COPTER ARCHITECTRE & ORGANIZATION SPRING DE : TA HOEWORK IV READ : i) Related portions of Chapter (except Sections. through.) ii) Related portions of Appendix A iii) Related portions of Appendix iv) Related portions of Appendix D ASSIGNENT : There are five questions. Solve all homework and exam problems as shown in class and past exam solutions. ) Consider Question of Homework where the EY CP high-level state diagram and datapath are modified for the JR instruction. ased on the feedback for your Homework solution, modify the low-level state diagram. If you decide to add new states, start at state 6. Then, modify the Control nit of the EY CP for JR. Assume that the EY CP is hardwired and already executes those nine instructions in the EY CP handout. In order to solve the problem, first show the high-level state diagram obtained in Homework and then modify the low-level state diagram and the Control nit. ) Consider Question of Homework where the EY CP high-level state diagram, datapath and low-level state diagram are modified for the JAL instruction. ased on the feedback for your Homework solution, modify the low-level state diagram. If you decide to add new states, start at state 6. Then, modify the Control nit of the EY CP for JAL. Assume that the EY CP is hardwired and already executes those nine instructions in the EY CP handout. In order to solve the problem, first show the high-level state diagram obtained in Homework and then modify the low-level state diagram and the Control nit. ) Consider the EY instruction SLTI. odify the EY CP completely to run the instruction. NY School of Engineering Page of Handout No: arch,

2 In order to solve this question, you will assume the CP is a multicycle CP. You will use the EY CP handout, by xeroxing it and modifying the necessary pages of the xeroxed copy. If you do not want to copy and modify the handout, you can just show the changes to the datapath as done in past exam questions below. In this question you will modify the EY CP so that it can execute the SLTI instruction. You need to modify the high-level state diagram (not in terms of buses) in parallel with the modification of the datapath. Then, you will modify the low-level state diagram. If you decide to add new states, start at state 6. Then, you will modify the Control nit of the EY CP for SLTI. Assume that the EY CP is hardwired and already executes those nine instructions in the EY CP handout. ) Consider the first program given on the first page of the EY nemonic achine Language Programming Examples Handout. It takes the EY CP 8 clock periods to run these four instructions. If the clock frequency is GHz, it would take the CP 8ns to run the instructions. Not satisfied with this, we decide to have clock quadrupling where the CP clock frequency is now at GHz (the clock period is.5ns), while the memory still takes ns per access. How long does it take to run these four instructions now? 5) Consider the fourth program given on the fifth page of the EY nemonic achine Language Programming Examples Handout. It is a function with seven instructions. It multiplies two numbers. Assume that the numbers multiplied are Y = and Z = 6. Assume also that the JR instruction takes clock periods to run since we trace states, and 6. i) If the clock frequency is GHz, how long will it take to run the function? ii) Not satisfied with this, we decide to have clock doubling where the CP clock frequency is now at GHz (the clock period is.5ns), while the memory still takes ns per access. How long does it take to run the function now? RELEVANT QESTIONS AND ANSWERS Q) We have decided to modify the data and control units of the CP in Handout for a new instruction. Its syntax and architectural operation are as follows : TRADD Rd, (Rs), (Rt) Rd [Rs] + [Rt] The brief description of the new instruction called, emory-to-register Add, is that it adds two memory locations pointed by Rs and Rt and stores the result in register Rd. NY School of Engineering Page of CS Handout No : arch,

3 i) Show the modified portion of the high-level state diagram (not in terms of buses). How long does it take to run the instruction? Later, when we cover Chapter, we will call it CPI i of the instruction. Then, what is the CPI i of the instruction? ii) Show the modified portion of the data unit together with control signals. Note that this is a CISC instruction since an A/L instruction accesses memory for data. A) i) There are multiple solutions. One which is not too slow and not too expensive is given here. The modified high-level state diagram is as follows : LW, SW TRADD A/L R-type Control 6 ALout A DR [ALout] ALout + DR [ALout] DR is a new emory Data Register and is a new organizational register to keep memory location values temporarily. 9 ALout DR + DR Arithmetic Overflow exception State GPR[Rd] ALout to State The CPI i is seven (7) since we trace states,, 6, 7, 8, 9 and. ii) The modified portion of the data unit is as follows : DRWrite D R A PC ALSrcA RS DRWrite D R 5 5 ALSrc NY School of Engineering Page of CS Handout No : arch,

4 Q) Consider the following piece of EY mnemonic machine language program : ADD R8, R9, R SLT R, R9, R 8 C EQ S R, R, R8, R, R9 The above piece of code is completely implemented by the following instruction : AS Rd, Rs # Rd Rs i) Rewrite the above code by using the new instruction which takes the absolute value of Rs. ii) Assume that the high-level state diagram is modified to run the new machine language instruction as follows : States AS 6 GPR[Rd] A 7 ALout A op If ALout == then GPR[Rd] 8 - A Also, the EY CP datapath is modified as follows : ALout[] RegWriteCond RegWrite GPR File A To ALSrcA AS AL From A emtoreg Write Data A ALSrc 5 5 S Obtain the low-level state diagram based on the modifications above. NY School of Engineering Page of CS Handout No : arch,

5 iii) Assume that we run the following instruction : AS R, R5 Show the values of registers and control signals for five clock periodsfor which continue with the following table : Cp State PC IR ALSrcA RegWriteCond ALop A ALout R R5 Initial ---? ???? (-6) NS NS??? NS NS A) i) The new code is as follows : AS R8, R9 # R8 R9 ii) The modified EY low-level state diagram is as follows : except : ALSrcA = ALSrc = LW except : emtoreg = except : ALSrcA = ALSrc = 5 SW LW, SW 6 except : ALSrcA = ALSrc = 7 except : emtoreg = except : ALSrcA = ALSrc = A/L R-format 6 7 AS EQ 8 emtoreg = RegWrite = RegDst = except : ALSrcA = ALSrc = J 9 ALSrcA = ALSrc = ALop = NY School of Engineering Page 5 of CS Handout No : arch, 8 ALSrcA = ALSrc = ALop = RegDst = emtoreg = RegWriteCond =

6 iii) The table with the values is as follows : Cp State PC IR ALSrcA RegWriteCond ALop A ALout R R5 Initial ---? ???? (-6) NS NS??? NS NS AS R, R5??? NS NS 6 NS NS (-6)? NS NS 7 NS NS (-6) FFFFFFFA NS NS 5 8 NS NS (-6) NS NS 6 NS NS (-6) 6 6 NS Q) Assume that the EY CP datapath is modified as follows : PC ALout DR IorD AS PC A DR ALSrcA AS i) Assume that the above modification in the datapath is for a new machine language instruction. The corresponding low-level state diagram is below. except ALSrca = ; IorD = 7 except ALSrcA = LW, SW,? A/L control except ALSrcA = SW R-format LW,? except IorD = LW 6? States - : as before except : State 5 : IorD = emread = ; IorD = State 6 : ALSrcA = State 8 : ALSrcA = ALSrcA = ; ALSrc = ; ALop = 8 emtoreg = ; RegDst = ; RegWrite = NY School of Engineering Page 6 of CS Handout No : arch,

7 Obtain the corresponding high-level state diagram. How many clock periods does it take to run the new instruction? ii) The new datapath allows new microoperations. List at least four () new microoperations that are not shown in the new states. iii) Describe the syntax, semantics, format, etc. of the new machine language instruction. If a new addressing mode or syntax is encountered, indicate so. A) i) The modified EY high-level state diagram (not in terms of buses) is as follows : LW, SW,? SW LW,? A/L R-format control 6? LW states - : as before DR [DR] 7 ALout 8 GPR[Rt] DR + ALout The new instruction takes seven clock periods since we trace states,,,, 6, 7 and 8 ii) The new microoperations not listed in the above high-level state diagram include the following : [DR] ALout DR + ALout DR + ALout DR + DOImm + ALout DR + (DOImm + * ) ALout DR op ALout DR op ALout DR op DOImm + ALout DR op (DOImm + * ) PC DR + PC DR + PC DR + DOImm + PC DR + (DOImm + * ) PC DR op... more... iii) The new instruction adds a memory location (pointed by another memory location) and a register. This instruction can be called ADDIR : Add memory indirect register : The syntax of the new instruction : ADDIR Rt, (Disp(Rs)) The semantics of the new instruction : Rt <--- [[Rs + Disp + ]] + Rt The format is the I format : Opcode Rs Rt DOImm Three arguments are used by the instruction : The second source argument is a register argument : Rt. We use the register addressing mode for it. The destination is implied to be Rt again and so the Implied addressing mode is used NY School of Engineering Page 7 of CS Handout No : arch,

8 for it. The first source argument is a memory argument. It is pointed by another memory location which is a new addressing mode. We use the emory Indirect via -byte signed displacement addressing mode for it. Q) The EY high-level state diagram has been modified as follows : 6 GPR[Rt] + a) Draw the modified portion of the EY CP datapath. b) Show the corresponding low-level state diagram. A) a) We see that the AL has to add which always has Rt and. That is AS and S are added such that they carry values (Rt) and. In the datapath, already number is connected to the S which is 5. Thus, we only need to connect register to the AS which is. Now, has to be larger and receive two ALSrcA control signals. One could connect a to for the addition. However, connecting Register to can handle upgrades better since it is quite possible that and DOImm + and DOImm + << might have to be operated on in the future. In addition, the result of the AL is directly stored on Rt, bypassing the ALout register. Then, we connect the output of the AL directly to the WS which is. has to be larger and receive two emtoreg control signals. The modified datapath is then as follows : ALout DR unused emtoreg WS Read Data Read Data GPR Register file Write Data A PC unused AS ALSrcA OS b) The corresponding low-level state : 6 ALSrcA = ALSrc = ALop = RegDst = emtoreg = RegWrite = NY School of Engineering Page 8 of CS Handout No : arch,

9 Q5) A new machine language instruction is added to the EY architecture. The following table is obtained by observing the CP when it runs this new instruction : clock period State PC IR R9 R [F] Initial --- F? F? YDI NS NS NS NS NS F YDI NS NS NS 6 NS NS NS NS NS 7 NS NS NS FFFFFFC NS The states mentioned above are the EY high-level state diagram states. The letters YDI mean You determine it. a) What is the CPI i of this new instruction? b) Describe the new instruction architecturally, i.e. its instruction format, what it accomplishes,... Also, indicate what YDI is on the table mnemonically (not in HE). c) odify the EY CP data unit to be able to run this new instruction. d) Show the modified low-level state diagram. e) Assume that the Control nit is hardwired. ased on the table above and your answer to parts (c) and (d), modify the hardwired EY Control unit. That is, show the modified portion of the hardware of the control unit A5) a) The CPI of the instruction is since we trace the states,, 6 and 7. b) State 6 is taken after state, therefore, it is an R-type instruction. We see that only two GPR registers are used for data : R9 and R. Also, we see that one must be used as a source and the other as a destination. These imply that a unary operation is performed on the source and stored on the destination by the instruction. We then work on the source-destination relationship and so convert both numbers to binary : F FFFFFFC The two numbers are the complement of each other. Thus, we have a complement instruction with the R-format : COP Rd, Rs Rd Rs opcode Rs nused rd shamt function The instruction run in the question (YDI) is COP R, R9 c) The only Data nit change is in the AL. The AL must now complement the value on its AS input. In order to indicate that it is a complement, an ALcontrol bit combination must be assigned the complement operation. We select combination for it : NY School of Engineering Page 9 of CS Handout No : arch,

10 AL ALop operation ALcontrol Add Sub indicated by function field of IR : Add Sub And Or SLT COP d) The low-level state diagram does not need any change since the high-level state diagram is the, the Data nit is the with the exception that the AL has a new operation to perform and the code to indicate the new operation in the low-level state diagram is the (ALop = ). e) In the hardwired EY control unit, nothing changes except the ALcontrol circuit : ALop ALcontrol 6 function The ALcontrol circuit now outputs a new combination,, if the nd opcode (function) indicates it is a COP instruction. Q6) Consider the following instruction that does not exist in the EY instruction set : SWAPR Rt, Disp(Rs) # Rt [Rs + Disp + ] a) i) odify the EY CP high-level state diagram, as done in class. ii) What is CPI SWAPR? Explain. b) odify the EY CP datapath to be able to run the new instruction, as done in class. c) odify the EY CP low-level state diagram accordingly and as done in class. d) Assume that the EY CP control unit is hardwired. Assume also that the opcode of the instruction is 7. odify the hardwired EY CP control unit accordingly, as done in class and as follows : Show two () signals that are modified or new. Again, just show the circuits for any two modified/new signals. A6) a) i) The modified high-level state diagram of this high-speed implementation is shown below. ii) CPI SWAPR is 6 since we trace states,,,, 5 and b) The changes in the datapath are that DR and ALout are not clocked every clock period : DRWrite DR ALoutWrite ALout NY School of Engineering Page of CS Handout No : arch,

11 States - :... All other LW, SW, SWAPR SW LW, SWAPR LW SWAPR 5 [ALout] SWAPR GPR[Rt] DR c) The modified EY low-level state diagram is as follows : except ALoutWrite =..... States - : except Step 6 : ALoutWrite = All other LW, SW, SWAPR except ALoutWrite = LW, SWAPR except DRWrite = SW LW SWAPR 5 emwrite = ; IorD = emtoreg = ; RegDst = ; RegWrite = d) Two new signals in the control unit, ALoutWrite and DRWrite are shown below : ALoutWrite is when it is state or or 6 ALoutWrite = S + S + S6 S S ALoutWrite S6 DRWrite is when it is state DRWrite = S S DRWrite Two signals are modified : NS and NS Other signals modified : emwrite, IorD, emtoreg, RegWrite NY School of Engineering Page of CS Handout No : arch,

12 Q7) Consider the following piece of EY mnemonic machine language program : LW R, (R8) # R8 points at array A and initially has LW R, (R9) # R9 points at array and initially has 8 C SLT EQ R, R, R R, R, # Compare R and R # Skip next instruction if R is not less than R SW R, (R8) # Store the nd number in the first 8 ADDI ADDI R8, R8, R9, R9, # pdate the array A pointer # pdate the array pointer C ADDI R, R, (-) # The loop-end counter, R, has initially NE R, R, (-9) # If not the end, go back to a) i) If the clock frequency is GHz, determine how long it takes to run the above piece of program as done in class. Note that each memory access takes one clock period. ii) Assume that clock doubling is used to speed up the processor. Calculate the new execution time. b) Assume that a new machine language instruction is created to perform the above program faster, SLT : SLT Rd, (Rs), (Rt) # If [Rs] < [Rt] then Rd, else Rd Rewrite the above piece of code, by using the SLT instruction. Add comments to your program. c) odify the EY high-level state diagram (not in terms of buses) and the datapath to be able to run the new instruction, as done in class. What is CPI SLT? d) i) ased on your answers to part (b) and part (c), determine the new execution time of the program as done in class. Again, assume that the clock frequency is GHz and each memory access takes one clock period. ii) Assume that clock doubling is used to speed up the processor. Calculate the new execution time. A7) a) i) The loop compares arrays A and. If an array A element is less than the corresponding array element, the array A element is replaced with the array element by executing a SW. Out of two comparisons (iterations), only one requires the execution of the SW instruction. Therefore, the following instructions are run : LW, LW, SLT, EQ, SW, ADDI, ADDI, ADDI, NE, LW, LW, SLT, EQ, ADDI, ADDI, ADDI, NE. The execution timings of the six different instructions in the loop are as follows : LW :,,,, => 5 cp SLT :,, 6, 7 => cp EQ :,, 8 => cp SW :,,, 5 => cp ADDI :,,, 6 => cp NE :,, 6 => cp The number of clock periods to run the 7 instructions is = 68 clock periods. The execution time is 68ns which is computed as follows : clock period = = -9 sec = ns The execution time is 68 * = 68ns ii) If clock doubling is used the instruction timings is as follows : LW : *,,, *, => 7 cp SLT : *,, 6, 7 => 5 cp EQ : *,, 8 => cp SW : *,,, 5* => 6 cp ADDI : *,,, 6 => 5 cp NE : *,, 6 => cp NY School of Engineering Page of CS Handout No : arch,

13 The number of clock periods to run the 7 instructions is = 9 clock periods. The execution time is 5ns which is computed as follows : clock period = =.5-9 sec =.5ns The execution time is 9 *.5 = 5ns b) The SLT instruction replaces the first three instructions : SLT R, (R8), (R9) EQ R, R, # Compare array A and elements # Skip next instruction if array A element is not less than array element 8 LW R, (R9) # Read array element C SW ADDI R, (R8) R8, R8, # Store array element in array A # pdate the array A pointer ADDI R9, R9, # pdate the array pointer 8 ADDI R, R, (-) # The loop-end counter, R, has initially C NE R, R, (-8) # If not the end, go back to c) The modified high-level state diagram and the datapath are as follows : SLT 6 DR <-- [A] 7 DR <-- [] 8 ALout <-- DR op DR 9 GPR[Rd] <-- ALout control LW, A/L SW R-format DRWrite PC ALout A DRWrite DR RS IorD DR Note thay DR is not clocked every clock period PC A DR ALSrcA DOImm + DOImm + * DR ALSrc 5 CPI SLT is 6 since we trace states,, 6, 7, 8 and 9 d) i) We execute the following instructions : SLT, EQ, LW, SW, ADDI, ADDI, ADDI, NE, SLT, EQ, ADDI, ADDI, ADDI, NE. The number of clock periods to run the instructions is = 57 clock periods. Then, the execution time is 57 * = 57ns. The speedup is 68/57 =.9 or 9% Compared with the old code, the new code has one less instruction, not two. An extra LW instruction is needed to bring the array element to the CP to write to array A even if the SLT instruction brings the element to the CP. This is because the SLT instruction does not keep the element in an architectural register that can be used by other instructions. In general, if data read from the memory is used again, it must be kept on architectural registers as long as possible. The RISC concept of having only LW and SW to access the memory for data supports that idea. CISC A/L instructions accessing memory for data keep the data in organizational registers, not visible to the machine language programmer. It means if the data element is needed an additional instruction is needed! NY School of Engineering Page of CS Handout No : arch,

14 ii) If clock doubling is used the instruction timings is as follows : LW : *,,, *, => 7 cp SLT : *,, 6*, 7*, 8, 9 => 9 cp EQ : *,, 8 => cp SW : *,,, 5* => 6 cp ADDI : *,, 6, 7 => 5 cp NE : *,, 6 => cp The number of clock periods to run the instructions is = 77 clock periods. The execution time is 8.5ns which is computed as follows : clock period = =.5-9 sec =.5ns The execution time is 77 *.5 = 8.5ns Q8) Consider the following piece of EY mnemonic machine language program : ADDI R8, R, LW R9, (R) # R points at array A 8 ADD R8, R8, R9 C ADDI R, R, # pdate the array A pointer ADDI R, R, (-) # The loop-end counter, R, has initially NE R, R, (-5) # If not the end, go back 8 SW R8, (R) i) If the clock frequency is GHz, determine how long it takes to run the above piece of program as done in class. ii) Assume that a new machine language instruction is created to perform the above program faster, ADDR : ADDR Rd, Rs, (Rt)++ # Rd Rs + [Rt] then Rt Rt + Rewrite the above piece of code, by using the ADDR instruction. Add comments to your program. iii) odify the EY high-level state diagram and the datapath to be able to run the new instruction, as done in class. What is CPI ADDR? iv) ased on your answers to part (ii) and part (iii), determine the new execution time of the program as done in class. Again, assume that the clock frequency is GHz. A8) i) The loop adds elements of array A and stores the result in the location following the array. There are two iterations of the loop indicated by R which is initialized to. Therefore, the following instructions are run : ADDI + (LW + ADD + ADDI + ADDI + NE) + SW. The execution timings of the six different instructions in the code are as follows : LW :,,,, => 5 cp ADD :,, 6, 7 => cp NE :,, 6 => cp SW :,,, 5 => cp ADDI :,, 6, 7 => cp The number of clock periods to run the instructions is + ( ) + = 8 clock periods. clock period = = -9 sec = ns ii) The ADDR instruction replaces three instructions : Exectime = # of clock periods for the code * clock period Exectime = 8 * = 8 ns ADDI R8, R, # Initialize R8 to ADDR R8, R8, (R)++ # Add an array A element pointed by R to R8 then update R 8 ADDI R, R, (-) # The loop-end counter, R, has initially C NE R, R, (-) # If not the end, go back to location SW R8, (R) # Store the result of the addition in the location following array A NY School of Engineering Page of CS Handout No : arch,

15 iii) There are a number of different solutions each with different speed and cost. The below implementation is a high speed one. The modified high-level state diagram and datapath of this high-speed implementation are as follows : 6 ADDR LW, A/L control DR <-- [] SW R-format 7 States - : GPR[Rd] <-- A + DR 8 GPR[Rt] <-- + CPI ADDR is 5 since we trace states,, 6, 7 and 8 PC ALout IorD ALout DR OS emtoreg PC A DOImm + DOImm + * DR ALSrcA ALSrc 5 iv) We execute the following eight instructions : ADDI + (ADDR + ADDI + NE) + SW. The number of clock periods to run the eight instructions is + (5 + + ) + = clock periods. Given that the clock frequency is the, the execution time is * = ns. Q9) Assume that the EY CP low-level state diagram and the datapath are modified to be able to run a new instruction as follows :... All other States - 9 : except : State 5 : wbussel =? 6 ALSrcA = ALSrc = ALop = 7 IorD = emwrite = wbussel = DOImm+ wbussel 7 WS a) odify the EY CP high-level state diagram accordingly and as done in class. If a state is the as the original, just write. What is the CPI i of the new instruction? Explain. b) What is the new instruction? Indicate only the following : The syntax, semantics, format and the memory accesses made. Determine an unused opcode for the instruction. c) Assume that the EY CP control unit is hardwired. NY School of Engineering Page 5 of CS Handout No : arch,

16 odify the hardwired EY CP control unit accordingly, as done in class and as follows : - Show all control signals that are modified or new, and - Show one () next state signal modified or new. A9) a) The modified high-level state diagram is as follows : CPI? is since we trace states,, 6 and 7?... All other ALout A + 6 States - 9 : 7 [ALout] DOImm + b) On the high level state diagram, we see that we add registers A and, meaning we add Rs and Rt. Then, we store the sign extended DOImm to a memory location whose address is Rs + Rt. This means we move a constant to a memory location whose address is the sum of Rs and Rt : VC (ove emory Constant) : Syntax : VC (Rs, Rt), Imm Semantics : [ Rs + Rt] Imm + Format, etc. : The I format is used since an Immediate data element is needed. We use opcode 7 for the new instruction. We make two memory access for the new instruction : One to fetch the instruction (state ) and one to write a data element to the memory (state 7). c) There are three modified control signals (ALSrcA, IorD, emwrite), one new control signal (wbussel), one new next state signal (NS) and one modified next state signal (NS) in the control unit : ALSrcA is when it is state or 6 or 8 or 6 ALSrcA = S + S6 + S8 + S6 S S6 S8 S6 ALSrcA NS is when it is state and Opcode 7 or state 6 NS = SOPCDCD + S6 IorD is when it is state or 5 or 7 IorD = S + S5 + S7 S S5 S7 IorD S OPCDC S6 NS emwrite is when it is state 5 or 7 emwrite = S5 + S7 S5 S7 emwrite wbussel is when it is state 7 wbussel = S7 S7 wbussel NY School of Engineering Page 6 of CS Handout No : arch,

17 Q) Assume that the EY CP high-level state diagram is modified to be able to run a new machine language instruction as follows : States - :... All other? 6 ALout A - 7 GPR[Rs] ALout ALout PC + ([DOImm + ]<<) If A = then PC ALout 8 a) What is the new instruction? That is, determine its syntax, semantics, etc. If there is a new addressing mode that is not discussed in class, indicate so. b) i) odify the EY CP datapath accordingly. ii) How long does it take to run the new instruction? Explain. c) Assume that the Rs register above is R8 and its value is. Assume also that this new instruction is in location C. Finally, assume that the DOImm is (-8) for this instruction. Continue with the following table until the effect of the new instruction is visible on the architecture : Clock period State PC IR A ALout R8 Initial ---- C???? Continue d) odify the EY CP low-level state diagram accordingly and as done in class. e) Assume that the EY CP control unit is hardwired. Assume also that the opcode of the new instruction is 7. odify the hardwired EY CP control unit accordingly, as done in class and as follows : Show two () signals that are modified or new. Again, just show the circuits for any two modified/new signals. A) a) On the high level state diagram, we see that we subtract from register Rs then store to Rs. Afterwards, we check the previous value of Rs to see if it is (the current value of Rs is FFFFFFC). If it is not, we move an address to PC by using the -byte signed PC-relative addressing mode. This is the LP instruction ranch Loop instruction that has the following syntax and semantics : Syntax : LP Rs, Offset Semantics : ) Rs Rs - ) If Rs = FFFFFFC then PC PC + (Offset + * ) Format, etc. : It uses the I format since an offset is used. Rt is not used NY School of Engineering Page 7 of CS Handout No : arch,

18 It has seven arguments. Rs is a destination and source register argument using register addressing mode. Number is an implied data element using the implied addressing mode. Rs is a source argument to be compared using the register addressing mode. FFFFFFC is an implied data element using the implied addressing mode. PC is implied to be the destination using implied addressing mode. The last operand is a memory address calculated by using the -byte PC-relative addressing mode. We make one memory access for the new instruction : One to fetch the instruction (state ) b) i) The new instruction requires a number of changes in the datapath as shown below. The datapath can be modified in other ways though! SE means Sign Extension which sign extends the rightmost 6 bits of IR. SE* means Sign Extension times which is the circuit that multiplies the sign extended rightmost 6 bits of IR by. Rt Rd Rs RegDst SE SE* ALSrc 5 Zero ii) CPI LP is 5 since we trace states,, 6, 7 and 8 c) The table is completed as follows : PCWriteCond Zero PCWriteCond PCWrite PC Clock period State PC IR A ALout R8 Initial ---- C???? NS NS??? NS C LP, R8, (-8)??? NS 6 NS NS E NS 7 NS NS FFFFFFC NS 5 8 NS NS E FFFFFFC 6 E NS FFFFFFC E NS d) The modified EY low-level state diagram is as follows : except ALSrc = except ALSrc = States - : except Step : ALSrc = Step : RegDst = Step 6 : ALSrc = Step 7 : RegDst = Step 8 : ALSrc =..... All other LP 6 ALSrcA = ; ALSrc = ; ALop = 7 RegDst = ; emtoreg = ; RegWrite = ; ALSrcA = ; ALSrc = ; ALop = 8 ALSrcA = ; ALSrc = ; ALop = ; PCSrc = ; PCWriteCond = NY School of Engineering Page 8 of CS Handout No : arch,

19 e) Two new signals in the control unit, ALSrc and PCWriteCond are shown below : ALSrc is when it is state 8 ALSrc = S8 PCWriteCond is when it is state 8 PCWriteCond = S8 S8 ALSrc S8 PCWriteCond Other new signals : RegDst and NS odified signals : ALSrcA,ALSrc, ALSrc, ALop, RegWrite, PCSrc, NS and NS Q) Assume that the EY CP low-level state diagram and the datapath are modified to be able to run a new instruction as shown below. except ALSrcA = ; ALSrc = ALSrcA = ALSrc = ALop = LW,? IorD = emread =? 6 ALSrcA = ALSrc = ALop = 7 RegDst = emtoreg = RegWrite = except ALSrcA = ; ALSrc = LW, SW,? SW LW A/L R-format Control States - 9 : except : State 6 : ALSrcA = ALSrc = State 8 : ALSrcA = ALSrc = A PC DOImm + DOImm + * DR ALSrcA ALSrc 5 a) odify the EY CP high-level state diagram accordingly and as done in class. If a state is the as the original, just write. What is the CPI i of the new instruction? Explain. b) What is the new instruction? Indicate only the following : The syntax, semantics, format and the memory accesses made. c) Assume that the EY CP control unit is hardwired. odify the hardwired EY CP control unit accordingly, as done in class and as follows : Show three () signals that are modified or new. NY School of Engineering Page 9 of CS Handout No : arch,

20 A) a) The modified high-level state diagram is as follows : CPI? is 6 since we trace states,,,, 6 and 7. LW,? LW, SW,? SW A/L R-format Control 6 ALout? LW - DR States - 9 : 7 GPR[Rt] ALout b) On the high level state diagram, we see that we subtract register DR from register. This means we subtract a memory location content from register Rt. This is a subtract between a register and a memory location : S : Syntax : S Rt, Disp(Rs) Semantics : Rt Rt - [Rs + Disp + ] Format, etc. : It uses the I format since a displacement is needed. We make two memory access for the new instruction : One to fetch the instruction (state ) and one to read a data element from the memory (state ). c) Two new signals in the control unit, ALSrc and ALSrcA and one modified control signal, RegWrite, are shown below : ALSrc is when it is state 6 ALSrc = S6 ALSrcA is when it is state 6 ALSrcA = S6 S6 ALSrc S6 ALSrcA RegWrite is when it is state or 7 or 7 RegWrite = S + S7 + S7 S S7 RegWrite S7 Other new signals : SR and NS. odified signals : ALop and NS. Finally, ALSrcA is renamed ALSrcA, NY School of Engineering Page of CS Handout No : arch,

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