CSE 260 Introduction to Digital Logic and Computer Design. Exam 1 Solutions

Transcription

1 CSE 6 Introduction to igital Logic and Computer esign Exam Solutions Jonathan Turner /3/4. ( points) raw a logic diagram that implements the expression (B+C)(C +)(B+ ) directly (do not simplify first), using only simple gates. B C Simplify the expression as much as you can. (B+C)(C +)(B+ ) = (BC +B+C)(B+ ) = (BC +B) = B(C +) How many simple gates of each type are required to implement the simplified expression? The circuit corresponding to this expression requires and gates, or gate and inverter. - -

2 . (5 points) raw a circuit that implements the VHL code fragment shown below. ssume that x and z are two bit signals. ll others are of type std_logic. You may use simple gates, multiplexors and flip flops in your circuit diagram. with z select x <= a & b when, when, when others; process (clk) begin if rising_edge(clk) then if a > b then y <= a and c; elsif a /= c then y <= x(); end process; x() x clk >C y 3 a b c z - -

3 3. ( points) Consider the circuit shown below, which includes four copies of the same basic building block. a(3) b(3) a() b() a() b() a() b() z(4) z(3) z() z() z() x(3) x() x() x() Write a VHL process containing a loop that specifies this circuit. process(a,b,z) begin for i in to 3 loop if b(i) /= z(i) then x(i) <= a(i) or z(i); else x(i) <= b(i); z(i+) <= a(i) and z(i); end loop; end process; - 3 -

4 4. ( points) raw a diagram of an 8-to- multiplexor with data inputs to 7 and a 3 bit control input C, using smaller multiplexors as building blocks. Make sure that the all signals and mux inputs are labeled appropriately. Pay special attention to the control inputs of the mux components in your circuit C() C(..) How many LUT4s does it take to implement this circuit? It takes 3 LUTs to implement each 4: mux, plus one more to implement the : mux, so 7 in all

5 5. (5 points) The VHL module shown below counts the number of odd length pulses that have been observed on the din input since the last reset. What is the smallest number of flip flops needed to implement this VHL spec? We need at least three for the register and eight for the oddcount register. So. entity oddpulsecounter is port( clk, reset, din: in std_logic; oddcount: out std_logic_vector(7 downto )); end oddpulsecounter; architecture a of oddpulsecounter is type Type is (resetstate, start, prev, prevodd, preveven); signal : Type; begin process(clk) begin if rising_edge(clk) then if reset = then <= resetstate; else case is when resetstate => oddcount <= (others => ); if din = then <= prev; else <= start; when start => if din = then <= prev; when prev => if din = then <= prevodd; when prevodd => if din = then <= prev; oddcount <= oddcount + ; else <= preveven; when others => if din = then <= prev; else <= prevodd; end case;... end a; Complete the diagram for this VHL module. Show updates to stored values. resetstate //oddcount<= start //.. //oddcount<= //.. //.. prev din //oddcount<=oddcount+ //.. //.. preveven //.. //.. prevodd - 5 -

6 6. ( points) Consider the diagram shown at left below. Fill in the entries in the table at right. You may abbreviate the names as R, G and B. x/ red / / green B/XY / current B XY next red blue green / / x/ x/ red red green blue / blue red blue green blue blue red green green Consider the table shown below. raw a diagram corresponding to this table. Is this machine a Mealy-mode machine or a Moore-mode machine? It s a Mealy-mode machine. / up current XY next up down up down left right left right / left / / / /XY / right up right up left / / down - 6 -

7 7. (5 points) The VHL module shown below defines a sequential circuit that looks for the minimum value present on the input and counts the number of clock periods when this minimum value is present. It has two outputs, minval and mincount. So for example, if the input sequence on is 57, 85, 3, 34, 36, 3, 46, 3 then the sequences of values on the two two outputs will be 57, 57, 3, 3, 3, 3, 3, 3 and,,,,,,,3. entity minvalcount is port ( clk, reset: in std_logic; : in std_logic_vector(7 downto ); minval, mincount : out std_logic_vector(7 downto )); end minvalcount; architecture a of minvalcount is signal val, count: std_logic_vector(7 downto ); begin process (clk) begin if rising_edge(clk) then if reset = '' then val <= x FF ; count <= x ; else if < val then val <= ; count <= x ; elsif = val then count <= count + ; end process; minval <= val; mincount <= count; end a; Complete the circuit shown below, so that it implements the VHL module above. Use only simple gates and : multiplexors. x compare X Y X=Y compare X Y X<Y x 8 bit reg (count) >C increment + minval reset xff 8 bit reg (val) >C mincount clk - 7 -