Lab 2 Verilog Synthesis & Logic Optimization

Transcription

1 UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 2 Verilog Synthesis & Logic Optimization 1.0 Motivation The goals of this lab are listed below: Provide a gentle introduction to writing Verilog Acquaint you with the Synthesis tool: Synplify Pro Show you professional logic optimization tools in action 2.0 Introduction In order to make circuit design faster circuits are not designed as hand-drawn or even computer based schematics. Instead, modern digital circuits are specified using Hardware Description Languages such as Verilog, which we will use extensively in this class. Though Verilog was originally designed to support simulating large circuits, synthesis tools such as Xilinx s XST and Synplicity s Synplify Pro now allow us to design a large, complicated digital system exclusively in Verilog and use automated CAD tools to implement it, either in an FPGA or even in an ASIC (Application Specific Integrated Circuit, a custom chip). The motivation behind the widespread adoption of Verilog as a method of hardware specification stems from the fact that a very complicated circuit can be described very succinctly in Verilog. For example, an adder can be expressed as assign sum = A + B; thereby hiding all of the complicated bit-width and gate details, in order to free the designer from having to worry about them. In this lab you will use what is referred to as dataflow style Verilog to capture the Boolean equations for a simple circuit. You will then synthesize this circuit to verify its functionality and look at how the tools have optimized your original design. 2.1 Circuit Overview Shown in figure 1, below is the basic block diagram for the test circuit you will be using in this lab. The first stage is simply a 25bit counter, which is used to divide the clock by 2 25 = 32Million reducing it from 27MHz to approximately 1Hz. Notice that we do not use this 1Hz signal as the clock, but merely as an enable. In this course, we will always have clearly defined clock signals, which are considered special. The basic reason for this is that clocks are given special resources and priority on the Xilinx chips, greatly improving our FPGA based designs. In an ASIC you might not always adhere to this. UCB

2 Figure 1: Lab #2 Circuit Block Diagram The second stage is a 4-bit counter, which simply counts 4 h0 to 4 hf and then recycles. This counter is enables approximately once per second using the 25bit counter. The ideas is to create an output that will change at a human visible rate, since your eye is nowhere near fast enough to see something flashing past at 1 / 27MHz = 37ns. The final stage is, of course, your binary to hexadecimal 7-segment LED output module. This module will simply translate the incoming 4-bit number into the 7 correct output signals required to drive the LEDs on the CaLinx2 boards. 3.0 Prelab Please make sure to complete the prelab before you attend your lab section. 1. Read this handout thoroughly. Pay particular attention to section 4.0 Lab Procedure as it describes what you will be doing in detail. 2. Examine the Verilog provided for this weeks lab. a. You should understand the FPGA_TOP2.v file. Reading Verilog is an excellent way to learn it. 3. Write your logic equations ahead of time. a. Refer to section 4.0 Lab Procedure for more information. 4.0 Lab Procedure Remember to manage your Verilog, projects and folders well. Doing a poor job of managing your files can cost you hours of rewriting code, if you accidentally delete your files. 4.1 Bin2HexLED.v Note that while we have given you an implementation of this module in Lab #1, it is in the wrong form: behavioral. You need to rewrite it using dataflow by generating a set of logic equations and then entering them using assign statements. Signal Width Dir Description Bin 4 I A 4-bit input representing a single hexadecimal digit SegLED 7 O The concatenation of the 7 wires required to drive a 7- segment LED. Table 1: Port Specification for Bin2HexLED.v UCB

3 As you can see from the above port list, this is a very simple module. It merely decodes its input to generate the correct patterns of lit and un-lit LEDs. Figure 2: 7-segment LED Shown in Figure 2, above, are the 7 segments of the LEDs. The SegLED output bus is the concatenation of active HIGH wires which will drive those 7 LEDs in the order {g,f,e,d,c,b,a}. For example the pattern for the digit 0, shown in Figure 3 below, would be 7 b Figure 3: The number 0 on a 7-segment LED You job is to write out logic equations of the form: a = func(bin[0], Bin[1], Bin[2], Bin[3]) for each LED a-g on the Checkoff Sheet and then enter these equations into your Bin2HexLED.v file. Be sure to take into account all sixteen digits: 0-9 and a-f as you are working with a binary/hexadecimal input. After you have finished your equations, you may need to synthesize and debug them. Figure 4: The 7-segment LED Patterns UCB

4 4.2 Synthesis & Logic Optimization Once you have a working design, you will need to go back and examine the Technology Schematic generated by Synplify Pro. This step will acquaint you with Synplify Pro, including its ability to generate schematics from your Verilog. 1. In Project Navigator select FPGA_TOP2 from the Sources in Project box a. This will cause a long list of implementation steps to appear in the Processes for Source box. 2. Double-Click the Synthesize Synplify Pro step to start the synthesis a. If there is an X or a! next to the Synthesize Synplify Pro step, this means that there has been an error or warning. b. To see the errors and warnings from Synplify Pro, double-click the Synthesize Synplify Pro -> View Synthesis Report step. 3. To view a schematic of the circuit double-click on the Synthesize Synplify Pro -> View Technology Schematic step a. This will launch Synplify Pro and automatically open the Technology Schematic b. Navigate through the schematic, look inside the Bin2HexLED module. Figure 5: The Synplify RTL Navigation Toolbar c. Since the wires will often have modified names you may need to trace them as explained in the Lab Lecture. d. You must write out the complete logic equations on the checkoff sheet. i. Remember that a 2-to-1 multiplexer where the inputs are a x = s a + s b and b and the select is s can be written: ( ) ( ) UCB

5 5.0 Checkoff Name: Section: SID: I Boolean Logic Equations (20%) 1 Write out your logic equations here: II Dataflow Verilog (Bin2HexLED.v) (20%) III Working synthesized design (20%) IV Optimized Logic Equations (40%) 1 Write out the logic equations based on the Synplify Pro Technology Schematic: V Hours Spent: VI Total: VII TA: RevA 1/17/2005 Greg Gibeling Created a new lab Designed to introduce students to writing Verilog gently while asking them to work with the synthesis tools to optimize a simple piece of logic UCB