COSC 6385 Computer Architecture. Defining Computer Architecture

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1 COSC 6385 Computer rchitecture Defining Computer rchitecture Fall 007 icro-processors in today s world arkets Desktop computing Servers Embedded computers Characteristics Price vailability Reliability Scalability Performance Power consumption

2 Instruction Set rchitecture (IS) Definition on Wikipedia: Part of the Computer rchitecture related to programming Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing Includes a specification of the set of opcodes (machine language) - native commands implemented by a particular CPU design Instruction Set rchitecture (II) IS to be distinguished from the micro-architecture set of processor design techniques used to implement an IS Example: Intel Pentium and D thlon support a nearly identical IS, but have completely different micro-architecture

3 IS Specification Relevant features for distinguishing IS s Internal storage emory addressing Type and size of operands Operations Instructions for Flow Control Encoding of the IS Internal storage Stack architecture: operands are implicitly on the top of the stack ccumulator architecture: one operand is implicitly the accumulator General purpose register architectures: operands have to be made available by explicit load operations Dominant form in today s systems 3

4 Example: C +B Internal storage (II) Stack: Push Push B dd Pop C ccumulator: Load dd B Store C Load-Store: Load R, Load R,B dd R3,R,R Store R3,C Internal storage (III) dvantage of general purpose register architectures vs. stack architectures: Registers are fast Easier and faster to evaluate complex expressions, e.g. (*B)-(B*C)-(*D) Registers can hold temporary variables Reduces memory traffic register can be named with fewer bits than main memory 4

5 ddressing modes How does an IS specify the address an object will access? ddressing mode Register Immediate Register indirect Displacement emory indirect Example instruction dd R4,R3 dd R4,#3 dd R4,(R) dd R4,00(R) dd eaning Regs[R4] Regs[R4]+Regs[R3] Regs[R4] Regs[R4]+3 Regs[R4] Regs[R4]+ em[regs[r]] Regs[R4] Regs[R4]+ em[00+regs[r]] Regs[R4 ] Regs[R4] +em[em[regs[r3]]] ddressing modes (II) ddressing modes must match bility of compilers to use them Hardware characteristics Which modes are most commonly used? Displacement Immediate Register indirect Size of address for displacement mode? Typically -6 bits Size of the immediate field? 8-6 bits 5

6 Internal storage (IV) Two major GPR architectures: or 3 operands for LU instructions 3 operands: source, result operands: operand is both source and result How many operands can be memory addresses? No. of memory addresses 0 3 ax. no. of operands 3 3 rchitecture Register-register (load-store arch.) Register-memory emory-memory emory-memory emory alignment (I) emory is typically aligned on a multiple of word boundaries Best case: accessing misaligned address leads to performance problems since it requires accessing multiple words Worst case: hardware does not allow misaligned access 6

7 emory alignment (II) Width of object byte bytes (half word) bytes (half word) 4 bytes (word) 4 bytes (word) 4 bytes (word) 4 bytes (word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) Type and size of operands (I) How is the type of an operand designated? Encoded in the opcode nnotated by tags Common operand types: Character - 8bits Half word - 6 bits, bytes Word - 3 bits, 4 bytes Single precision floating point - 3 bits, 4 bytes Double precision floating point - 64 bits, 8 bytes 7

8 Type and size of operands (II) Encoding of characters: SCII UNICODE Encoding of integers: Two s complement binary numbers Encoding of floating point numbers: IEEE standard 754 No uniform representation of the data type long double Operations in the Instruction Set Operator type rithmetic and logical Data transfer Control System Floating point Decimal String Graphics Examples Integer arithmetic: add, subtract, and, or, multiple, divide Load, store, move Branch, jump, procedure call, return, traps OS call, virtual memory management Floating point arithmetic: add, multiply, divide, compare Decimal add, multiply String move, string compare, string search Pixel and vertex operations, compression 8

9 Flow Control instructions Four types of different control flow changes Conditional branches Jumps Procedure calls Procedure returns How to specify the destination address of a flow control instruction? PC-relative: Displacement to the program counter (PC) Register indirect: name a register containing the target address Flow Control instructions (II) Register indirect jumps also required for Case/switch statements Virtual functions in C++ Function pointers in C Dynamic shared libraries ( dll in Windows,.so in UNIX) Procedure invocation: global variables could be accessed by multiple routines location of the variable needs to be known Options for saving registers: Caller saving Callee saving due to the possibility of separate compilation, many compilers store any global variable that may be accessed during a call 9

10 Encoding an Instruction Set How are instructions encoded into a binary representation ffects size of compiled program ffects implementation of the processor Decision depends on range of addressing modes supported Variable encoding Individual instructions can vary widely in size and amount of work to be performed Fixed encoding Easy to decode Operation and no. of operands Operation ddress specifier ddress field ddress field ddress field ddress specifier ddress field Example rchitecture: IPS64 (I) Load-store architecture 3 64bit GPR registers (R0,R, R3) R0 contains always bit floating point registers (F0,F, F3) When using 3bit floating point numbers the other 3 bits of the FP registers are not used or Instructions available for operating 3bit FP operations on a single 64bit register Data types: 8 bit bytes, 6bit half-words, 3bit words, 64 bit double words 3bit and 64bit floating point data types 0

11 Example architecture: IPS64 (II) ddressing modes: Immediate Displacement Displacement field and immediate field are both 6bit wide Register indirect addressing accomplished by using 0 in the displacement field bsolute addressing accomplished by using R0 as the base register Example architecture: IPS64(III) ll instructions are 3bit wide (fixed encoding): 6bit opcode ddressing modes are encoded in the opcode LD R,30(R) load double word Regs[R] 64 em[30+regs[r]] with n load n bits LW R,60(R) load word Regs[R] 64 em[60+regs[r] 0 ] 3 ## em[60+regs[r]] with Regs[R] 0 indicating a bit-field selection, e.g. Regs[R] 0 is the sign bit of R e.g. Regs[R] last byte of of R with X n replicate a bit field e.g. Regs[R] set high order three bytes to 0 with ## concatenate two fields

12 Example architecture: IPS64(IV) Thus Regs[R] 64 em[60+regs[r] 0 ] 3 ## em[60+regs[r]] Replicate the sign bit of memory address [60+Regs[R]] on the first 3 bits of Regs[] Dependability odule reliability measures TTF: mean time to failure FIT: failures in time Reciprocal value of TTF Often expressed as failures in,000,000,000 hours TTR: mean time to repair TBF: mean time between failures TBF TTF + TTR odule availability: TTF TTF+ TTR

13 Dependability - example ssume a disk subsystem with the following components and TTFs: 0 disks, TTF,000,000h SCSI controller, TTF500,000h power supply, TTF00,000h fan, TTF 00,000h SCSI cable, TTF,000,000h What is the TTF of the entire system? What is the probability, that the system fails within a week period? Dependability example (II) Determine the sum of the failures in time FIT system ,000, ,000 00,000 00,000,000, ,000,000 TTF FIT 3,000,000 system 43, 500 system h 3,000,000,000,000 Probability that the system fails within a week period: week P system 4*7 43,500 0, ,386% 3

14 Dependability example (III) What happens if we add a second power supply and we assume, that the TTR of a power supply is 4 hours? ssumption: failures are not correlated TTF of the pair of power supplies is the mean time to failure of the overall system divided by the probability, that the redundant unit fails before the primary unit has been replaced TTF of the overall system is TTF power / Probability, that unit fails within TTR: TTR/ TTF power TTF pair TTF TTR TTF power/ power TTF 00,000 TTR 4 830,000,000 mdahl s Law Describes the performance gains by ancing one part of the overall system (code, computer) Speedup Performance of entire task using the ancement Performance of entire task not using the ancement Or Speedup Execution time of the task not using the ancement Execution time of the task using the ancement 4

15 mdahl s Law (II) mdahl s Law depends on two factors: Fraction of the execution time affected by ancement The improvement gained by the ancement for this fraction Thus Fraction Execution _ time Execution_ timeorg(( Fraction) + ) Speedup (:7:) Speedup overall Execution_ time Execution_ time org Fraction ( Fraction) + Speedup (:7:) 6 Speedup mdahl s Law (III) overall Fraction ( Fraction) + Speedup 5 Speedup total 4 3 Fraction anced: 0% Fraction anced: 40% Fraction anced: 60% Fraction anced: 80% Speedup anced 5

16 mdahl s Law (IV) Speedup according to mdahl's Law 0 Speedup total Speedup anced: Speedup anced: 4 Speedup anced: Fraction anced mdahl s Law - example ssume a new web-server with a CPU being 0 times faster on computation than the previous web-server. I/O performance is not improved compared to the old machine. The web-server spends 40% of its time in computation and 60% in I/O. How much faster is the new machine overall? Fraction 0.4 Speedup 0 using formula (:7:) Speedup overall ( Fraction Fraction ) + Speedup 0.4 ( 0.4)

17 mdahl s Law example (II) Example: Consider a graphics card 50% of its total execution time is spent in floating point operations 0% of its total execution time is spent in floating point square root operations (FPSQR). Option : improve the FPSQR operation by a factor of 0. Option : improve all floating point operations by a factor of.6 Speedup FPSQR 0. ( 0.) + ( ) 0 SpeedupFP 0.5 ( 0.5) + ( ) Option slightly faster 7

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