COMP2121: Microprocessors and Interfacing. Instruction Formats and Addressing Modes
|
|
- Sabina Collins
- 6 years ago
- Views:
Transcription
1 COMP2121: Microprocessors and Interfacing Instruction Formats and Addressing Modes Lecturer: Hui Wu Session 2,
2 Overview Instruction format AVR instruction format examples PowerPC instruction format examples Addressing Modes AVR Instruction Examples 2 2
3 Instruction Formats Instructions typically consist of Opcode (Operation code) defines the operation (e.g. addition) Operands what s being operated on (e.g. particular registers or memory address) There are many different formats for instructions 3 3
4 Instruction Formats OpCode OpCode Opd OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3 Instructions typically have 0, 1, 2 or 3 operands Could be memory addresses, constants, register addresses (i.e. register numbers) 4 4
5 AVR Instruction Examples Clear register. Syntax: clr Rd Operand: 0 d 31 Operation: Rd 0 Instruction format d d d d d d d d d d 0 OpCode uses 6 bits (bit 9 to bit 15). The only operand uses the remaining 10 bits (only 5 bits (bit 0 to bit 4) are actually needed). 5 5
6 AVR Instruction Examples Subtraction with carry. Syntax: sbc Rd, Rr Operation: Rd Rd Rr C Rd: Destination register. 0 d 31 Rr: Source register. 0 r 31 C: Carry Instruction format r d d d d d r r r r 0 OpCode uses 6 bits (bit 9 to bit 15). Two operands share the remaining 10 bits. 6 6
7 Instruction Lengths On some machines instructions are all the same length On other machines instructions can have different lengths 7 7
8 AVR Instruction Examples Almost all instructions are 16 bits long. add Rd, Rr sub Rd, Rr mul Rd, Rr brge k Few instructions are 32 bits long. lds Rd, k ( 0 k ) loads 1 byte from the SRAM to a register. 8 8
9 Design Criteria for Instruction Formats 1. Backwards Compatibility e.g. Pentium 4 supports various instruction lengths so as to be compatible with Instruction Length Ideally (if you re starting from scratch) All instructions same length Short instructions are better (less memory needed to store programs and can read instructions in from memory faster) 9 9
10 Instruction Design Criteria (cont.) 3. Room to express operations 2 n operations needs at least n bits Wise to allow room to add additional opcodes for next generation of CPU 4. Number of operand bits in instruction Do you address bytes or words? 10 10
11 OpCode Operand Tradeoffs Instructions can tradeoff number of OpCode bits against number of operand bits Example: 16 bit instructions 16 registers (i.e. 4-bit register addresses) Instructions could be formatted like this: OpCode Operand1 Operand2 Operand3 But what if we need more instructions and some instructions only operate on 0, 1 or 2 registers? 11 11
12 Expanding OpCodes Some OpCodes can mean look elsewhere in the instruction for the real OpCode e.g. if first 4 bits are 1111, OpCode is really contained in next 4 bits (i.e. effectively an 8 bit OpCode), and so on 12 12
13 Expanding OpCodes Other combinations are possible Exercise (two minutes) For a 16 bit instruction machine with 16 registers, design OpCodes that allow for 14 3-operand instructions 30 2-operand instructions 30 1-operand instructions 32 0-operand instructions 13 13
14 PowerPC Examples PowerPC ISA defines OpCode as the first six bits This specifies type of instruction (operation) OpCode specifies format of the rest of the instruction 14 14
15 PowerPC Machine Instruction Example 1 32 bits 6 bits 5 bits 5 bits 16 bits OpCode Destination Register Source Register Value (2 s complement) OpCode ( two or 14) tells us that this instruction is an integer addition: destination-register = source-register + value r5 = r12 + (-1) 15 15
16 PowerPC Machine Instruction Example 2 6 bits 11 bits OpCode Secondary OpCode OpCode ( two or 63) tells us this is a double precision floating point instruction But it does not tell us what it actually does! We need to look at a Secondary OpCode 16 16
17 PowerPC Machine Instruction Example 2 5 bits 5 bits 5 bits Destination Register Source Registers A & B Secondary OpCode Secondary OpCode (42) tells us this is a double precision floating point addition destination-reg = register-a + register-b fr13 = fr26 + fr
18 Operands Instructions need to specify where to get operands from Some possibilities Value is in instruction Value is in a register Register number is in the instruction Value is in memory address is in instruction address is in a register register number is in the instruction address is register value plus some offset register number is in the instruction offset is in the instruction (or in a register) These are called addressing modes 18 18
19 Immediate Addressing Not really an addressing mode since there is no address Instruction doesn t have address of operand it has the value itself i.e. the operand is immediately available Limits to the size of the operand you can fit in an instruction (especially in RISC machines which have instruction word size = data word size) 19 19
20 Immediate Addressing Examples AVR SUBI 0101 KKKK Rd KKKK ADIW KK Rd KKKK mov ebx, KKKK Pentium KKKK KKKK KKKK KKKK KKKK KKKK KKKK KKKK 20 20
21 Direct Addressing Address of the memory operand is in the instruction Useful for global variables (accessible from all subroutines) AVR Datasheet calls this Data Direct Addressing and I/O Direct Addressing
22 AVR Direct Addressing Examples STS Rd 0000 kkkk kkkk kkkk kkkk Pentium mov eax,[kk] kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 22 22
23 Register Direct Addressing Register numbers are contained in the instruction Data in the registers. Fastest mode and most common mode in RISC Example: ADD AVR Pentium r ddddd r r r r r r r ddd Sparc 10 rd rs1 0 - rs
24 Register Indirect Addressing Register number in instruction, as with register addressing However, contents of the register is used to address memory the register is used as a pointer AVR datasheet calls this Data Indirect addressing 24 24
25 Register Indirect Addressing Example AVR LDD Rd, Y ddddd 1000 Operation: Rd (Y) Y: r29: r
26 Indexed Addressing Reference memory at a known offset from a register Two main uses: Register holds address of object; fixed offset indexes into the object (structure, array, etc) Address of object is constant; register has index into the object AVR datasheet calls this Data Indirect with Displacement addressing (fixed offset, not in register) 26 26
27 Indexed Addressing Examples AVR (data indirect with displacement) Only 6 bit displacement (q bits) Only Y or Z index registers determined by this bit LDD Rd, Y+q 10 q 0 qq 0 ddddd 1 qqq Operation: Rd (Y + q) 27 27
28 Auto Increment Some architectures allow modification of the index register as a side effect of the addressing mode Usually add or subtract a small constant, often equal to the operand size Could happen before or after the index register is used in the address calculation Most common are post increment and pre decrement AVR supports these Data Indirect with Pre-decrement Data Indrect with Post-increment 28 28
29 AVR LDD Rd, -Y Auto Increment Examples ddddd 1010 Operation: Y Y 1 Rd (Y) LDD Rd, Y ddddd 1001 Operation: Rd (Y) Y Y
30 Code Memory Constant Addressing AVR has separate data and instruction memories Sometimes need to get data constants out of instruction memory (flash memory) Special instruction provided to do this (LPM) LPM Rd, Z ddddd 0100 Operation: Rd (Z) Load a byte at the address contained in register Z (r30: r29) 30 30
31 Branch Instructions Specify where in the program to go next (i.e. change the program counter rather than just increment) program flow is no longer linear Types of Branch Instructions Unconditional always do it Conditional do it if some condition is satisfied (e.g. check status register) Jumps no return Subroutines (function calls) can return 31 31
32 Branch Instruction Addressing Modes Direct addressing Address to jump to included in the instruction Not every AVR device support this (JMP and CALL instructions) Indirect addressing Address to jump to is in a register AVR examples: IJMP, ICALL Program Counter Relative addressing AVR calls this Relative Program Memory addressing Add a constant value to the Program Counter AVR examples: RJMP, RCALL, conditional branch instructions 32 32
33 Branch Instruction Addressing Modes: AVR Examples JMP k Operation: PC k (0 k 4M) kkkkk 110 k kkkk kkkk kkkk kkkk IJMP Operation: PC Z
34 Branch Instruction Addressing Modes: AVR Examples BRGE k (signed) Operation: If Rd Rr then PC PC+k+1 else PC PC+1 Operand: -64 k kkkkkkk
35 Reading Material 1. Chapter 4 in Microcontrollers and Microcomputers
COMP3221: Microprocessors and Embedded Systems
Embedded Systems Lecture 6: Addressing Modes http://www.cse.unsw.edu.au/~cs3221 Lecturer: Hui Wu Session 2, 2005 Addressing Modes Overview Instruction Examples 1 2 Operands Immediate Addressing Instructions
More informationCOMP2121: Microprocessors and Interfacing
Interfacing Lecture 6: Instruction Format http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 1, 2006 Overview Instruction format AVR instruction format examples PowerPC instruction format examples
More informationAVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo
AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo 1 Lecture Overview AVR ISA AVR Instructions & Programming (I) Basic construct implementation 2 Atmel AVR 8-bit RISC architecture
More informationAVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo
AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo 1 Lecture Overview AVR ISA AVR Instructions & Programming (I) Basic construct implementation 2 Atmel AVR 8-bit RISC architecture
More informationAVR ISA & AVR Programming (I)
AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo Week 1 1 Lecture Overview AVR ISA AVR Instructions & Programming (I) Basic construct implementation Week 1 2 1 Atmel AVR 8-bit
More informationCN310 Microprocessor Systems Design
CN310 Microprocessor Systems Design Instruction Set (AVR) Nawin Somyat Department of Electrical and Computer Engineering Thammasat University Outline Course Contents 1 Introduction 2 Simple Computer 3
More informationCOMP2121: Microprocessors and Interfacing
Interfacing Lecture 9: Program Control Instructions http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 1, 2006 Program control instructions in AVR Stacks Overview Sample AVR assembly programs
More informationBy: Dr. Hamed Saghaei
By: Dr. Hamed Saghaei The AVR RISC Microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM). This section describes the different
More informationECED3204: Microprocessor Part I--Introduction
ECED3204: Microprocessor Part I--Introduction Jason J. Gu Department of 1 Outline i. Computer ii. Processor iii. Embedded System iv. Memory v. Program Execution VI. VII. VIII. IX. AVR AVR Memory AVR CPU
More informationCOMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA)
COMP2121: Microprocessors and Interfacing Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2017 1 Contents Memory models Registers Data types Instructions
More informationChapter 4: Atmel s AVR 8-bit Microcontroller Part 1 Assembly Programming
Chapter 4: Atmel s AVR 8-bit Microcontroller Part 1 Assembly Programming Prof. Ben Lee Oregon State University School of Electrical Engineering and Computer Science Chapter Goals Understand how to program
More informationEE 308: Microcontrollers
EE 308: Microcontrollers Assmbly Language Part I Aly El-Osery Electrical Engineering Department New Mexico Institute of Mining and Technology Socorro, New Mexico, USA January 30, 2018 Aly El-Osery (NMT)
More informationCOMP3221: Microprocessors and. and Embedded Systems. Instruction Set Architecture (ISA) What makes an ISA? #1: Memory Models. What makes an ISA?
COMP3221: Microprocessors and Embedded Systems Lecture 2: Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs3221 Lecturer: Hui Wu Session 2, 2005 Instruction Set Architecture (ISA) ISA is
More informationECE 375 Computer Organization and Assembly Language Programming Winter 2018 Solution Set #2
ECE 375 Computer Organization and Assembly Language Programming Winter 2018 Set #2 1- Consider the internal structure of the pseudo-cpu discussed in class augmented with a single-port register file (i.e.,
More informationAddressing Modes Part II AVR Addressing Indirect READING
1 P a g e Addressing Modes Part II AVR Addressing Indirect READING The AVR Microcontroller and Embedded Systems using Assembly and C) by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi Chapter 6: AVR
More informationก AVR Microcontrollers
ก AVR Microcontrollers. ก ก AVR Microcontrollers Architecture 1 Instruction Execution Timing The Parallel Instruction Fetches and Instruction Executions Single Cycle ALU Operation AVR Microcontrollers
More informationAPPENDIX B AVR INSTRUCTIONS EXPLAINED OVERVIEW
APPENDIX B AVR INSTRUCTIONS EXPLAINED OVERVIEW In this appendix, we describe each intruction of the ATmega328. In many cases, a simple code example is given to clarify the instruction. Instructions are
More information8-bit Instruction Set
Instruction Set Nomenclature Status Register (SREG) SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two s complement overflow indicator S: N V, For signed tests H: Half Carry Flag
More information8-bit Instruction Set
Instruction Set Nomenclature Status Register (SREG) SREG: Status Register C: Carry Flag Z: Zero Flag N: Negative Flag V: Two s complement overflow indicator S: N V, For signed tests H: Half Carry Flag
More informationIntroduction to Computer. Chapter 5 The LC-3. Instruction Set Architecture
Introduction to Computer Engineering ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin Madison Chapter 5 The LC-3 Instruction Set Architecture
More informationAPPENDIX A FOR SKEE3732 LABORATORY 1 SHEET
APPENDIX A FOR SKEE3732 LABORATORY 1 SHEET Other documents that are referred within this document are located at the link https://www.dropbox.com/sh/s16jri4eol3agl5/aaazn_w3p7fodjs-wi-xcenqa?dl=0 The ATmega32/ATmega2A
More informationAVR MICROCONTROLLER ARCHITECTURTE
AVR MICROCONTROLLER ARCHITECTURTE AVR MICROCONTROLLER AVR- Advanced Virtual RISC. The founders are Alf Egil Bogen Vegard Wollan RISC AVR architecture was conceived by two students at Norwegian Institute
More informationMechatronics and Microcomputers. Stipendium Hungaricum 2018/2019 Autumn Semester Szilárd Aradi, PhD
Mechatronics and Microcomputers Stipendium Hungaricum 2018/2019 Autumn Semester Szilárd Aradi, PhD ATmega128 CPU Single-level pipelining Egyciklusú ALU működés Reg. reg., reg. konst. közötti műveletek
More informationModule 8: Atmega32 Stack & Subroutine. Stack Pointer Subroutine Call function
Module 8: Atmega32 Stack & Subroutine Stack Pointer Subroutine Call function Stack Stack o Stack is a section of RAM used by the CPU to store information temporarily (i.e. data or address). o The CPU needs
More informationAVR Instruction Set Encoding
1 P age AVR Instruction Set Encoding READING 1. "AVR Instruction Set" document doc856 "The Program and Data Addressing Modes." 2. In this lecture I will teach you how to translate your assembly code into
More informationAssembly Programming (III) Lecturer: Sri Parameswaran Notes by: Annie Guo Dr. Hui Wu
Assembly Programming (III) Lecturer: Sri Parameswaran Notes by: Annie Guo Dr. Hui Wu 1 Lecture overview Stack and stack operations Functions and function calls Calling conventions 2 Stack What is stack?
More informationGrundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss
Grundlagen Microcontroller Processor Core Günther Gridling Bettina Weiss 1 Processor Core Architecture Instruction Set Lecture Overview 2 Processor Core Architecture Computes things > ALU (Arithmetic Logic
More informationAssembly Programming (III)
Assembly Programming (III) Lecturer: Annie Guo S2, 2006 COMP9032 Week6 1 Lecture Overview Stack and stack operations Functions and function calls Calling conventions S2, 2006 COMP9032 Week6 2 What is stack?
More informationModule 3 Instruction Set Architecture (ISA)
Module 3 Instruction Set Architecture (ISA) I S A L E V E L E L E M E N T S O F I N S T R U C T I O N S I N S T R U C T I O N S T Y P E S N U M B E R O F A D D R E S S E S R E G I S T E R S T Y P E S O
More informationCOS 140: Foundations of Computer Science
COS 140: Foundations of Computer Science CPU Organization and Assembly Language Fall 2018 CPU 3 Components of the CPU..................................................... 4 Registers................................................................
More informationA First Look at Microprocessors
A First Look at Microprocessors using the The General Prototype Computer (GPC) model Part 2 Can you identify an opcode to: Decrement the contents of R1, and store the result in R5? Invert the contents
More informationEXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER
OBJECT: EXPERIMENT NO. 1 THE MKT 8085 MICROPROCESSOR TRAINER To understand the structure and operating instruction of the microprocessor trainer. INTRODUCTION: The MKT 8085 is a single-board microcomputer,
More informationLecture 20: AVR Programming, Continued. AVR Program Visible State (ones we care about for now)
18 100 Lecture 20: AVR Programming, Continued S 15 L20 1 James C. Hoe Dept of ECE, CMU April 2, 2015 Today s Goal: You will all be ace AVR hackers! Announcements: Midterm 2 can be picked up in lab and
More informationCSCE 5610: Computer Architecture
HW #1 1.3, 1.5, 1.9, 1.12 Due: Sept 12, 2018 Review: Execution time of a program Arithmetic Average, Weighted Arithmetic Average Geometric Mean Benchmarks, kernels and synthetic benchmarks Computing CPI
More informationMODULE 4 INSTRUCTIONS: LANGUAGE OF THE MACHINE
MODULE 4 INSTRUCTIONS: LANGUAGE OF THE MACHINE 1 ARCHITECTURE MODEL The basic instruction set of a computer is comprised of sequences of REGISTER TRANSFERS. Example: Add A, B, C Register B # A
More informationISA and RISCV. CASS 2018 Lavanya Ramapantulu
ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program
More informationProgramming. A. Assembly Language Programming. A.1 Machine Code. Machine Code Example: Motorola ADD
A. Assembly Language Programming Programming of a computer system: Machine code direct execution Assembly language tool: assembler High level programming language tool: interpreter tool: compiler Programming
More informationUnderstand the factors involved in instruction set
A Closer Look at Instruction Set Architectures Objectives Understand the factors involved in instruction set architecture design. Look at different instruction formats, operand types, and memory access
More informationInstruction Set II. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 7. Instruction Set. Quiz. What is an Instruction Set?
COMP 212 Computer Organization & Architecture Quiz COMP 212 Fall 2008 Lecture 7 Fill in your student number only, do NOT write down your name Open book, but NO calculator, NO discussions, Relax and have
More informationCSIS1120A. 10. Instruction Set & Addressing Mode. CSIS1120A 10. Instruction Set & Addressing Mode 1
CSIS1120A 10. Instruction Set & Addressing Mode CSIS1120A 10. Instruction Set & Addressing Mode 1 Elements of a Machine Instruction Operation Code specifies the operation to be performed, e.g. ADD, SUB
More informationCS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2018 Lecture 4
CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2018 Lecture 4 LAST TIME Enhanced our processor design in several ways Added branching support Allows programs where work is proportional to the input values
More informationInstruction Sets: Characteristics and Functions Addressing Modes
Instruction Sets: Characteristics and Functions Addressing Modes Chapters 10 and 11, William Stallings Computer Organization and Architecture 7 th Edition What is an Instruction Set? The complete collection
More informationInstruction Set Architecture. "Speaking with the computer"
Instruction Set Architecture "Speaking with the computer" The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture Digital Design
More informationComputer System Architecture
CSC 203 1.5 Computer System Architecture Department of Statistics and Computer Science University of Sri Jayewardenepura Addressing 2 Addressing Subject of specifying where the operands (addresses) are
More informationET2640 Microprocessors
ET2640 Microprocessors Unit -2 Processor Programming Concepts Basic Control Instructor : Stan Kong Email : skong@itt-tech.edu Figure 2 4 Bits of the PSW Register 8051 REGISTER BANKS AND STACK 80 BYTES
More informationWe briefly explain an instruction cycle now, before proceeding with the details of addressing modes.
Addressing Modes This is an important feature of computers. We start with the known fact that many instructions have to include addresses; the instructions should be short, but addresses tend to be long.
More informationChapter 04: Instruction Sets and the Processor organizations. Lesson 11: Generation of Memory Addresses and Addressing Modes
Chapter 04: Instruction Sets and the Processor organizations Lesson 11: Generation of Memory Addresses and Addressing Modes 1 Objective Learn how a memory address generates in different addressing modes
More informationMemory organization Programming model - Program status word - register banks - Addressing modes - instruction set Programming examples.
MICROCONTROLLERS AND APPLICATIONS 1 Module 2 Module-2 Contents: Memory organization Programming model - Program status word - register banks - Addressing modes - instruction set Programming examples. MEMORY
More informationECE 486/586. Computer Architecture. Lecture # 7
ECE 486/586 Computer Architecture Lecture # 7 Spring 2015 Portland State University Lecture Topics Instruction Set Principles Instruction Encoding Role of Compilers The MIPS Architecture Reference: Appendix
More informationInstruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...
Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,
More informationMicrocontroller Intel [Instruction Set]
Microcontroller Intel 8051 [Instruction Set] Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2 8051 Assembly Language Registers
More informationCOSC 6385 Computer Architecture. Instruction Set Architectures
COSC 6385 Computer Architecture Instruction Set Architectures Spring 2012 Instruction Set Architecture (ISA) Definition on Wikipedia: Part of the Computer Architecture related to programming Defines set
More informationCOMP3221: Microprocessors and Embedded Systems
Embedded ystems Overview Arithmetic and Logic nstructions in AR ample AR Assembly Programs Using AL instructions Lecture 7: Arithmetic and logic nstructions http://www.cse.unsw.edu.au/~cs3221 Lecturer:
More informationForecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer
Instructions (354 Review) Forecast Instructions are the words of a computer Instruction set architecture (ISA) is its vocabulary With a few other things, this defines the interface of computers But implementations
More information8051 Microcontrollers
8051 Microcontrollers Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu March 15, 2016 8051 INSTRUCTIONS JUMP, LOOP AND CALL INSTRUCTIONS 8051 INSTRUCTIONS Repeating a sequence of instructions
More informationInstruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...
Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands
More informationLecture 3 Machine Language. Instructions: Instruction Execution cycle. Speaking computer before voice recognition interfaces
Lecture 3 Machine Language Speaking computer before voice recognition interfaces 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very
More informationLecture 04: Machine Instructions
CSCI2510 Computer Organization Lecture 04: Machine Instructions Ming-Chang YANG mcyang@cse.cuhk.edu.hk Reading: Chap. 2.3~2.4, 2.10~2.11 Recall: Instructions & Program A computer is governed by instructions.
More informationEC-801 Advanced Computer Architecture
EC-801 Advanced Computer Architecture Lecture 5 Instruction Set Architecture I Dr Hashim Ali Fall 2018 Department of Computer Science and Engineering HITEC University Taxila!1 Instruction Set Architecture
More informationReminder: tutorials start next week!
Previous lecture recap! Metrics of computer architecture! Fundamental ways of improving performance: parallelism, locality, focus on the common case! Amdahl s Law: speedup proportional only to the affected
More informationCourse Administration
Fall 2018 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture Introduction 4/4 Avinash Karanth Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701
More informationComputer Organization CS 206 T Lec# 2: Instruction Sets
Computer Organization CS 206 T Lec# 2: Instruction Sets Topics What is an instruction set Elements of instruction Instruction Format Instruction types Types of operations Types of operand Addressing mode
More informationMicroprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman
Microprocessors 1 The 8051 Instruction Set Microprocessors 1 1 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into
More informationInstruction Set Design
Instruction Set Design software instruction set hardware CPE442 Lec 3 ISA.1 Instruction Set Architecture Programmer's View ADD SUBTRACT AND OR COMPARE... 01010 01110 10011 10001 11010... CPU Memory I/O
More informationCOMP2121: Microprocessors and Interfacing
nterfacing Overview Arithmetic and Logic nstructions in AR ample AR Assembly Programs Using AL instructions Lecture 8: Arithmetic and logic nstructions http://www.cse.unsw.edu.au/~cs2121 Lecturer: ui Wu
More informationEE 361 University of Hawaii Fall
C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and
More informationORG ; TWO. Assembly Language Programming
Dec 2 Hex 2 Bin 00000010 ORG ; TWO Assembly Language Programming OBJECTIVES this chapter enables the student to: Explain the difference between Assembly language instructions and pseudo-instructions. Identify
More informationEE 308: Microcontrollers
EE 308: Microcontrollers Review Part I Aly El-Osery Electrical Engineering Department New Mexico Institute of Mining and Technology Socorro, New Mexico, USA February 15, 2018 Aly El-Osery (NMT) EE 308:
More informationMIPS Assembly Programming
COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2
More informationAVR Control Transfer -AVR Branching
1 P a g e AVR Control Transfer -AVR Branching Reading The AVR Microcontroller and Embedded Systems using Assembly and C) by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi Chapter 3: Branch, Call,
More informationCHAPTER ASSEMBLY LANGUAGE PROGRAMMING
CHAPTER 2 8051 ASSEMBLY LANGUAGE PROGRAMMING Registers Register are used to store information temporarily: A byte of data to be processed An address pointing to the data to be fetched The vast majority
More informationISA: The Hardware Software Interface
ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important
More informationChapter 2. lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1
Chapter 2 1 MIPS Instructions Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 $s3 addi $s1,$s2,4 $s1 = $s2 + 4 ori $s1,$s2,4 $s2 = $s2 4 lw $s1,100($s2) $s1 = Memory[$s2+100]
More informationAssembly Language Programming of 8085
Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085
More informationCOMPUTER ORGANIZATION & ARCHITECTURE
COMPUTER ORGANIZATION & ARCHITECTURE Instructions Sets Architecture Lesson 5a 1 What are Instruction Sets The complete collection of instructions that are understood by a CPU Can be considered as a functional
More informationLecture 4: Instruction Set Architecture
Lecture 4: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation Reading: Textbook (5 th edition) Appendix A Appendix B (4 th edition)
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More information8051 Overview and Instruction Set
8051 Overview and Instruction Set Curtis A. Nelson Engr 355 1 Microprocessors vs. Microcontrollers Microprocessors are single-chip CPUs used in microcomputers Microcontrollers and microprocessors are different
More informationDigital Systems - Mini AVR 3
Digital Systems - Mini AVR 3 Pere Palà - Alexis López itic http://itic.cat April 2016 Enhancing the processor Up to now, we have a linear program flow Suitable for a pre-planned task Unable to react to
More informationInstruction Set Architecture (ISA)
Instruction Set Architecture (ISA)... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data
More informationSlides for Lecture 6
Slides for Lecture 6 ENCM 501: Principles of Computer Architecture Winter 2014 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 28 January,
More informationTransfer of Control. Lecture 10 JMP. JMP Formats. Jump Loop Homework 3 Outputting prompts Reading single characters
Lecture 10 Jump Loop Homework 3 Outputting prompts Reading single characters Transfer of Control The CPU loads and executes programs sequentially. You d like to be able to implement if statements, gotos,
More informationToday s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
More informationTopic 10: Instruction Representation
Topic 10: Instruction Representation CSE 30: Computer Organization and Systems Programming Summer Session II Dr. Ali Irturk Dept. of Computer Science and Engineering University of California, San Diego
More informationEvolution of ISAs. Instruction set architectures have changed over computer generations with changes in the
Evolution of ISAs Instruction set architectures have changed over computer generations with changes in the cost of the hardware density of the hardware design philosophy potential performance gains One
More informationCOMP2121: Microprocessors and Interfacing. AVR Assembly Programming (I) Basic AVR Instructions
COMP2121: Microprocessors and Interfacing AVR Assembly Programming (I) Basic AVR Instructions http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2017 1 1 Contents Arithmetic and Logic Instructions
More informationMIPS History. ISA MIPS Registers
MIPS History MIPS is a computer family R2000/R3000 (32-bit) R4000/4400 (64-bit) R10000 (64-bit) and others MIPS originated as a Stanford research project under the direction of John Hennessy Microprocessor
More informationCHAPTER 5 A Closer Look at Instruction Set Architectures
CHAPTER 5 A Closer Look at Instruction Set Architectures 5.1 Introduction 293 5.2 Instruction Formats 293 5.2.1 Design Decisions for Instruction Sets 294 5.2.2 Little versus Big Endian 295 5.2.3 Internal
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP DB805C-FSM 805 Microcontroller FSM Finite State Machine General Description The Digital Blocks DB805C-FSM IP Core contains Digital Blocks compact DB805C CPU Core & GPIO
More informationAVR Subroutine Basics
1 P a g e AVR Subroutine Basics READING The AVR Microcontroller and Embedded Systems using Assembly and C) by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi Chapter 3: Branch, Call, and Time Delay
More informationProgramming of 8085 microprocessor and 8051 micro controller Study material
8085 Demo Programs Now, let us take a look at some program demonstrations using the above instructions Adding Two 8-bit Numbers Write a program to add data at 3005H & 3006H memory location and store the
More informationCHAPTER 5 A Closer Look at Instruction Set Architectures
CHAPTER 5 A Closer Look at Instruction Set Architectures 5.1 Introduction 199 5.2 Instruction Formats 199 5.2.1 Design Decisions for Instruction Sets 200 5.2.2 Little versus Big Endian 201 5.2.3 Internal
More informationChapter 5. A Closer Look at Instruction Set Architectures
Chapter 5 A Closer Look at Instruction Set Architectures Chapter 5 Objectives Understand the factors involved in instruction set architecture design. Gain familiarity with memory addressing modes. Understand
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
More informationComputer Organization & Assembly Language Programming. CSE 2312 Lecture 15 Addressing and Subroutine
Computer Organization & Assembly Language Programming CSE 2312 Lecture 15 Addressing and Subroutine 1 Sections in 8088 Code TEXT section, for the processor instructions. DATA section for the initialization
More informationBasic Processor Design
Basic Processor Design Design Instruction Set Design Datapath Design Control Unit This lecture deals with Instruction Set Design. 1001 Instruction Set Terminology Mnemonic (Instruction Name) SUBI Syntax
More informationGates and flip-flops: glue logic, simple FSMs, registers Two-level PLDs: FSMs, muxes, decoders. Programmable logic devices (CSE370, CSE467)
Computational hardware Digital logic (CSE370) Gates and flip-flops: glue logic, simple FSMs, registers Two-level PLDs: FSMs, muxes, decoders Programmable logic devices (CSE370, CSE467) Field-programmable
More informationRui Wang, Assistant professor Dept. of Information and Communication Tongji University.
Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood
More information