COSC 6385 Computer Architecture - Instruction Set Principles

Transcription

1 COSC 6385 Computer rchitecture - Instruction Set Principles Fall 2006

2 Organizational Issues September 4th: no class (labor day holiday) Classes of onday Sept. 11 th and Wednesday Sept. 13 th have to be rescheduled: 1 st lecture on Friday, Sept. 15 th? How many people have classes directly after the Computer rchitecture class? New online book about computer architecture: Please handle with caution Hennessy/Patterson still considered more reliable.

3 mdahl s Law revisited (I) 6 Speedup overall = (1 Fraction enh 1 ) + Fraction Speedup enh enh 5 Speedup total Fraction enhanced: 20% Fraction enhanced: 40% Fraction enhanced: 60% Fraction enhanced: 80% Speedup enhanced

4 mdahl s Law revisited (II) Speedup according to mdahl's Law Speedup total Speedup enhanced: 2 Speedup enhanced: 4 Speedup enhanced: Fraction enhanced

5 Instruction Set rchitecture (IS) Definition on Wikipedia: Part of the Computer rchitecture related to programming Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing Includes a specification of the set of opcodes (machine language) - native commands implemented by a particular CPU design

6 Instruction Set rchitecture (II) IS to be distinguished from the micro-architecture set of processor design techniques used to implement an IS Example: Intel Pentium and D thlon support a nearly identical IS, but have completely different microarchitecture

7 IS Specification Relevant features for distinguishing IS s Internal storage emory addressing Type and size of operands Operations Instructions for Flow Control Encoding of the IS

8 Internal storage Stack architecture: operands are implicitly on the top of the stack ccumulator architecture: one operand is implicitly the accumulator General purpose register architectures: operands have to be made available by explicit load operations Dominant form in today s systems

9 Internal storage (II) Example: C= +B Stack: Push Push B dd Pop C ccumulator: Load dd B Store C Load-Store: Load R1, Load R2,B dd R3,R1,R2 Store R3,C

10 Internal storage (III) dvantage of general purpose register architectures vs. stack architectures: Registers are fast Easier and faster to evaluate complex expressions, e.g. (*B)-(B*C)-(*D) Registers can hold temporary variables Reduces memory traffic register can be named with fewer bits than main memory

11 ddressing modes How does an IS specify the address an object will access? ddressing mode Register Immediate Register indirect Displacement emory indirect Example instruction dd R4,R3 dd R4,#3 dd R4,(R1) dd R4,100(R1) dd eaning Regs[R4] Regs[R4]+Regs[R3] Regs[R4] Regs[R4]+3 Regs[R4] Regs[R4]+ em[regs[r1]] Regs[R4] Regs[R4]+ em[100+regs[r1]] Regs[R4 ] em[em[regs[r3]]]

12 ddressing modes (II) ddressing modes must match bility of compilers to use them Hardware characteristics Which modes are most commonly used? Displacement Immediate Register indirect Size of address for displacement mode? Typically bits Size of the immediate field? 8-16 bits

13 Internal storage (IV) Two major GPR architectures: 2 or 3 operands for LU instructions 3 operands: 2 source, 1 result 2 operands: 1 operand is both source and result How many operands can be memory addresses? No. of memory addresses ax. no. of operands rchitecture Register-register (load-store arch.) Register-memory emory-memory 3 3 emory-memory

14 Byte order (I) 2 different conventions for ordering bytes within an integer/floating point number Big endian (IB Power PC, SUN Sparc, SGI IPS, etc.) Little endian (Intel Pentium, D thlon, etc.) Example: representation of the number 1 : Big endian Little endian little end big end

15 Byte order (II) For communication between unknown architectures over the internet: Internet Protocol (IP) defines a network byte order: big endian #include <netinet/in.h> uint16_t htons (uint16_t val); uint32_t htonl (uint32_t val); uint16_t ntohs (uint16_t val); uint32_t ntohl (uin32_t val); htons/htonl (host to net short/long) converts a 16bit /32bit integer from the host byte order into network byte order ntohs/ntohl (net to host short/long) converts a 16bit /32bit integer from network byte order into host byte order No such functions exist for floating point numbers

16 Byte order (III) Implementation for byte-swapping operations manually void convert_32_big_little(uint32_t *data, int cnt) { uint32_t value; int i; } for(i=0; i<cnt; i++) { value = data[i]; data[i] = 0; data[i] = ( value & 0xff ) >> 24; data[i] = ( value & 0x00ff0000 ) >> 8; data[i] = ( value & 0x0000ff00 ) << 8; data[i] = ( value & 0x000000ff ) << 24; }

17 emory alignment (I) emory is typically aligned on a multiple of word boundaries Best case: accessing misaligned address leads to performance problems since it requires accessing multiple words Worst case: hardware does not allow misaligned access

18 emory alignment (II) Width of object byte 2 bytes (half word) 2 bytes (half word) 4 bytes (word) 4 bytes (word) 4 bytes (word) 4 bytes (word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word) 8 bytes ( double word)

19 Type and size of operands (I) How is the type of an operand designated? Encoded in the opcode nnotated by tags Common operand types: Character - 8bits Half word - 16 bits, 2 bytes Word - 32 bits, 4 bytes Single precision floating point - 32 bits, 4 bytes Double precision floating point - 64 bits, 8 bytes

20 Type and size of operands (II) Encoding of characters: SCII UNICODE Encoding of integers: Two s complement binary numbers Encoding of floating point numbers: IEEE standard 754 No uniform representation of the data type long double

21 Operations in the Instruction Set Operator type rithmetic and logical Data transfer Control System Floating point Decimal String Graphics Examples Integer arithmetic: add, subtract, and, or, multiple, divide Load, store, move Branch, jump, procedure call, return, traps OS call, virtual memory management Floating point arithmetic: add, multiply, divide, compare Decimal add, multiply String move, string compare, string search Pixel and vertex operations, compression

22 Flow Control instructions Four types of different control flow changes Conditional branches Jumps Procedure calls Procedure returns How to specify the destination address of a flow control instruction? PC-relative: Displacement to the program counter (PC) Register indirect: name a register containing the target address

23 Flow Control instructions (II) Register indirect jumps also required for Case/switch statements Virtual functions in C++ Function pointers in C Dynamic shared libraries ( dll in Windows,.so in UNIX) Procedure invocation: global variables could be accessed by multiple routines location of the variable needs to be known Options for saving registers: Caller saving Callee saving due to the possibility of separate compilation, many compilers store any global variable that may be accessed during a call

24 Encoding an Instruction Set How are instructions encoded into a binary representation ffects size of compiled program ffects implementation of the processor Decision depends on range of addressing modes supported Operation and ddress ddress Variable encoding no. of operands specifier 1 field 1 Individual instructions can vary widely in size and amount of work to be performed Operation ddress ddress Fixed encoding field 1 field 2 Easy to decode ddress specifier 2 ddress field 2

25 Example rchitecture: IPS64 (I) Load-store architecture 32 64bit GPR registers (R0,R1, R31) R0 contains always bit floating point registers (F0,F1, F31) When using 32bit floating point numbers the other 32 bits of the FP registers are not used or Instructions available for operating 2 32bit FP operations on a single 64bit register Data types: 8 bit bytes, 16bit half-words, 32bit words, 64 bit double words 32bit and 64bit floating point data types

26 Example architecture: IPS64 (II) ddressing modes: Immediate Displacement Displacement field and immediate field are both 16bit wide Register indirect addressing accomplished by using 0 in the displacement field bsolute addressing accomplished by using R0 as the base register

27 Example architecture: IPS64(III) ll instructions are 32bit wide (fixed encoding): 6bit opcode ddressing modes are encoded in the opcode LD R1,30(R2) load double word Regs[R1] 64 em[30+regs[r2]] with n load n bits LW R1,60(R2) load word Regs[R1] 64 em[60+regs[r2] 0 ] 32 ## em[60+regs[r2]] with Regs[R2] 0 indicating a bit-field selection, e.g. Regs[R2] 0 is the sign bit of R2 e.g. Regs[R2] last byte of of R2 with X n replicate a bit field e.g. Regs[R2] set high order three bytes to 0 with ## concatenate two fields

28 Example architecture: IPS64(IV) Thus Regs[R1] 64 em[60+regs[r2] 0 ] 32 ## em[60+regs[r2]] Replicate the sign bit of memory address [60+Regs[R2]] on the first 32 bits of Regs[1]