# Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

Save this PDF as:

Size: px
Start display at page:

Download "Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21"

## Transcription

1 2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig : space 33:! 34: 35: #... 48: 0 49: : A 66: B... 97: a 98: b : DEL What others? 0~31: control characters (NUL) 1: ^A 2: ^B... 7: ^G (BEL) 8: ^H (BS)... 13: ^M (CR)... 31: ^- (US, cursor up) 128~255: graphic characters String A sequence of characters In C language, it is null-terminated : Cab = Byte Data & Constants How to load/store characters from/to memory? (not integers ) Example: Copy of the four characters from [160] to [200] Assume \$s0=160, \$s1=200 lw \$t0, 0(\$s0) & sw \$t0,0(\$s1): OK What if it is Caba = ? lw \$t0, 0(\$s0) & sw \$t0, 0(\$s1) lw \$t1, 4(\$s0) & sw \$t1, 4(\$s1) => we also copied 3 un-wanted bytes in => we want load/store inst. in byte quantity => lb & sb => the second inst must be lb \$t1, 4(\$s0) & sb \$t1, 4(\$s1) (C) (a) (b) byte Must be word boundary? 17

2 Byte Data & Constants Exercise : strcpy(a[ ], b[ ]) Assume a[ ] starts at 160 (\$s0), b[ ] starts at 200 (\$s1) We don t know the string size, but it is null-terminated \$zero register can be used byte (C) (a) (b) MIPS data transfer instructions Instruction SW R3, 500(R4) SH R3, 502(R2) SB R2, 41(R3) Comment Store word Store half Store byte Sign-extended (affect the entire word) LW R1, 30(R2) LH R1, 40(R3) LHU R1, 40(R3) LB R1, 40(R3) LBU R1, 40(R3) Not sign-extended (affect the entire word) Load word (i.e., fill with 0 s in upper 2 or 3 bytes) Load halfword Load halfword unsigned Load byte Load byte unsigned LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16) (later in this lecture) 19

### Chapter 2. Instruction Set Architecture (ISA)

Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:

### CS3350B Computer Architecture

CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,

### MIPS (SPIM) Assembler Syntax

MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin

### ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

### A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

### Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

### All instructions have 3 operands Operand order is fixed (destination first)

Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/

### MIPS Reference Guide

MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

### ECE 154A Introduction to. Fall 2012

ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi

### Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic

### MIPS%Assembly% E155%

MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage \$0 0 the constant value 0 \$at 1 assembler temporary

### MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

### ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer

### Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

### CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

### MIPS Assembly Programming

COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

### Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register \$2 then

### Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction

### Architecture II. Computer Systems Laboratory Sungkyunkwan University

MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a

### ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 \$zero all bits are zero 16 \$s0 local variable 1 \$at assembler temporary 17 \$s1 local

### Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor

### MIPS Instruction Format

MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

### EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

### ISA: The Hardware Software Interface

ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Are you P2P sharing fans? Two

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

### CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

### Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

### Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers \$0 \$31 Multiply divide Coprocessor 1 (FPU) Registers

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II 2004-02-23 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia In the US, who is

### Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

### A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

### Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

### ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### CS61C L10 MIPS Instruction Representation II, Floating Point I (6)

CS61C L1 MIPS Instruction Representation II, Floating Point I (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #1 Instruction Representation II, Floating Point I 25-1-3 There is one

### Review of the Machine Cycle

MIPS Branch and Jump Instructions Cptr280 Dr Curtis Nelson Review of the Machine Cycle When a program is executing, its instructions are located in main memory. The address of an instruction is the address

### Lecture 3: The Instruction Set Architecture (cont.)

Lecture 3: The Instruction Set Architecture (cont.) COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Review: Instructions Computers process information

### Five classic components

CS/COE0447: Computer Organization and Assembly Language Chapter 2 modified by Bruce Childers original slides by Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower

### Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi \$s2, \$s2, -1 beq \$s0, \$s1, loop or \$s2, \$s1, \$zero

Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi \$s2, \$s2, -1 beq \$s0, \$s1, loop or \$s2, \$s1, \$zero 25 Comparisons Set on less than (slt) compares its source registers

### EN164: Design of Computing Systems Lecture 09: Processor / ISA 2

EN164: Design of Computing Systems Lecture 09: Processor / ISA 2 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University

### ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

### We will study the MIPS assembly language as an exemplar of the concept.

MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #10 Instruction Representation II, Floating Point I 2005-10-03 Lecturer PSOE, new dad Dan Garcia www.cs.berkeley.edu/~ddgarcia #9 bears

### Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood

### MIPS Instruction Reference

Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

### Architecture I. Computer Systems Laboratory Sungkyunkwan University

MIPS Instruction ti Set Architecture I Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Architecture (1) the attributes of a system as seen by the

### COMP MIPS instructions 2 Feb. 8, f = g + h i;

Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers (\$0,..., \$31) in any instruction. This is not so, however.

EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

### Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C

Lab 4 Report Single Cycle Design BAOTUNG C. TRAN EEL4713C Added Hardware : Andi and Ori : For this instruction, I had to add a zero extender into my design. Which therefore required me to add a mux that

### Lecture 6: Assembly Programs

Lecture 6: Assembly Programs Today s topics: Procedures Examples Large constants The compilation process A full example 1 Procedures Local variables, AR, \$fp, \$sp Scratchpad and saves/restores, \$fp Arguments

### Math 230 Assembly Programming (AKA Computer Organization) Spring 2008

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1

### EE 109 Unit 8 MIPS Instruction Set

1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

### Midterm. CS64 Spring Midterm Exam

Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

### The Program Counter. QtSPIM Register Display (Fixed-Point Registers) Erik Jonsson School of Engineering and Computer Science

The Program Counter PC = 400064 EPC = 0 Cause = 0 BadVAddr = 0 Status = 3000ff10 1 The program counter is a register that always contains the memory address of the next instruction (i.e., the instruction

### Lecture 6 Decision + Shift + I/O

Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw \$t0,12(\$s0) sw \$t0, 12(\$s0) beq \$s0, \$s1, L1 bne \$s0, \$s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3

### Computer Architecture. Lecture 2 : Instructions

Computer Architecture Lecture 2 : Instructions 1 Components of a Computer Hierarchical Layers of Program Code 3 Instruction Set The repertoire of instructions of a computer 2.1 Intr roduction Different

### MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies

Stephen Blott Review of MIPS Instruction Set Table of Contents 1 2 Registers Memory Instructions r0 ; always 0 r1, r2,..., r31 ; general-purpose integer registers f0, f1, f2,...,

### Chapter 4. The Processor. Computer Architecture and IC Design Lab

Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS

### CS3350B Computer Architecture MIPS Procedures and Compilation

CS3350B Computer Architecture MIPS Procedures and Compilation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada

### Digital System Design II

Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4

### COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access

### Chapter 2. Instructions: Language of the Computer

Chapter 2 Instructions: Language g of the Computer Outlines Introduction to MIPS machine Operations of the Computer HW Operands of the Computer HW Representing instructions in the Computer Logical Operations

### CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

### MIPS PROJECT INSTRUCTION SET and FORMAT

ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction

### Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.

Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations

### SPIM Instruction Set

SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures \$2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

### Chapter 4. The Processor

Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

### CS232 Final Exam May 5, 2001

CS232 Final Exam May 5, 2 Name: This exam has 4 pages, including this cover. There are six questions, worth a total of 5 points. You have 3 hours. Budget your time! Write clearly and show your work. State

### Outline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath

Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates

### Lecture Topics. Branch Condition Options. Branch Conditions ECE 486/586. Computer Architecture. Lecture # 8. Instruction Set Principles.

ECE 486/586 Computer Architecture Lecture # 8 Spring 2015 Portland State University Instruction Set Principles MIPS Control flow instructions Dealing with constants IA-32 Fallacies and Pitfalls Reference:

### Inf2C - Computer Systems Lecture Processor Design Single Cycle

Inf2C - Computer Systems Lecture 10-11 Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh Previous lectures Combinational circuits Combinations of gates (INV, AND, OR,

### Compiling Techniques

Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

### CS 61C: Great Ideas in Computer Architecture Strings and Func.ons. Anything can be represented as a number, i.e., data or instruc\ons

CS 61C: Great Ideas in Computer Architecture Strings and Func.ons Instructor: Krste Asanovic, Randy H. Katz hdp://inst.eecs.berkeley.edu/~cs61c/sp12 Fall 2012 - - Lecture #7 1 New- School Machine Structures

### ECE Exam I February 19 th, :00 pm 4:25pm

ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

### The Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined

### Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions

Part Part Part What if we need to call a function inside of a function? Will this work? int twofun(int a, int b) { int res; res = addfun(a, b) a / ; return res; } twofun: addi \$sp, \$sp, -4 sw \$s0, 0(\$sp)

### Instruction Set Architecture (ISA)

Instruction Set Architecture (ISA)... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data

### Lecture 2: RISC V Instruction Set Architecture. James C. Hoe Department of ECE Carnegie Mellon University

18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L02 S1, James C. Hoe, CMU/ECE/CALCM, 2018 Your goal today Housekeeping get bootstrapped

### Systems Architecture

Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software

### Solutions for Chapter 2 Exercises

Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642

### Assembly Programming

Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

### Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators

### UCB CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 10 Introduction to MIPS Procedures I Sr Lecturer SOE Dan Garcia 2014-02-14 If cars broadcast their speeds to other vehicles (and the

### Chapter 4. The Processor

Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations

### Chapter 4. The Processor Designing the datapath

Chapter 4 The Processor Designing the datapath Introduction CPU performance determined by Instruction Count Clock Cycles per Instruction (CPI) and Cycle time Determined by Instruction Set Architecure (ISA)

### CS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats

CS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats Instructors: Krste Asanović and Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/fa17 9/14/17 Fall 2017 - Lecture #7 1 Levels of

### Orange Coast College. Business Division. Computer Science Department CS 116- Computer Architecture. The Instructions

Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Instructions 1 1 Topics: Assembly language, assemblers MIPS R2000 Assembly language Instruction set

### Computer Hardware Engineering

Computer Hardware Engineering IS2, spring 27 Lecture 9: LU and s ssociate Professor, KTH Royal Institute of Technology Slides version. 2 Course Structure Module : C and ssembly Programming LE LE2 LE EX

### Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework

### 361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath

361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative

### Lecture 2: RISC V Instruction Set Architecture. Housekeeping

S 17 L2 1 18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University Housekeeping S 17 L2 2 Your goal today get bootstrapped on RISC V RV32I to start

### CS 61c: Great Ideas in Computer Architecture

MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: \$s0-\$s7,\$t0-\$t9, \$0

### Single Cycle Datapath

Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.-4.4 Appendices B.7, B.8, B.,.2 Practice Problems:, 4, 6, 9 ing (2) Introduction We will examine two MIPS implementations

### The Single Cycle Processor

EECS 322 Computer Architecture The Single Cycle Processor Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow CWRU

### The Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath

The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:

### Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures

Review (1/2) CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ IEEE 754 Floating Point Standard: Kahan pack as much in

### COMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined

### Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations

Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations