CA226 Advanced Computer Architecture

Transcription

1 Stephen Blott Review of MIPS Instruction Set Table of Contents 1 2 Registers Memory Instructions r0 ; always 0 r1, r2,..., r31 ; general-purpose integer registers f0, f1, f2,..., f31 ; general-purpose floating-point registers The only instructions which access memory are: load instructions, and store instructions. All other instructions operate: register to register. 3 4

2 Load Instructions Memory Objects Examples: All registers are: ld r4,n(r0) ; load 8-byte word from address N into r4 ld r2,0(r1) ; load 8-byte word from address in r1 into r2 ld r3,8(r1) ; load 8-byte word from address in r1 plus 8 into r3 The first register is always the target, the source is memory. Addressing is always by displacement: ld r5,x(r1) ; load from memory address "X plus the contents of r1" 64 bits, or 8 bytes Memory objects may be: bytes (1 byte) half words (2 bytes) words (4 bytes) double words (8 bytes) 5 6 Aside Load Objects It is unfortunate: that the directive ".word" in fact reserves a double word of memory. lb r2,n(r0) ; load a single byte from address N lh r2,n(r0) ; load a two-byte value from address N lw r2,n(r0) ; load a four-byte value from address N ld r2,n(r0) ; load an eight-byte value from address N The computed memory address: must be appropriately aligned meaning: ` N%"size" = 0 ` 7 8

3 Load: Floating Point Stores l.d f1,n(r0) ; load a floating-point value ; into a floating-point register Addressing: is the same as for integer loads. Stores are the same: sb r2,n(r0) ; store a single byte to address N sh r2,n(r0) ; store a two-byte value to address N sw r2,n(r0) ; store a four-byte value to address N sd r2,n(r0) ; store an eight-byte value to address N s.d f1,n(r0) ; store a floating-point value to address N 9 10 Loads again, Loads and Signs For bytes, half words and words: there are also unsigned load instructions. lbu r2,n(r0) ; load a single byte from address N, unsigned lhu r2,n(r0) ; load a two-byte value from address N, unsigned lwu r2,n(r0) ; load a four-byte value from address N, unsigned Why? And why only in these three cases? Signed loads: are sign extended: the most significant bit is duplicated into the unloaded bits For unsigned loads: this is not done. And for double-word loads: this is unnecessary

4 Arithmetic Instructions Integer Arithmetic dadd r3,r1,r2 ; r3 = r1 + r2 dsub r3,r1,r2 ; r3 = r1 - r2 dmul r3,r1,r2 ; r3 = r1 * r2 ddiv r3,r1,r2 ; r3 = r1 / r2 (any remainder is discarded) Floating-Point Arithmetic Immediates add.d f3,f1,f2 ; f3 = f1 + f2 sub.d f3,f1,f2 ; f3 = f1 - f2 mul.d f3,f1,f2 ; f3 = f1 * f2 div.d f3,f1,f2 ; f3 = f1 / f2 ; Note: These require floating point registers. An immediate value is: a constant the argument value is included in the instruction itself Examples: daddi r3,r1,1 ; r3 = r1 + 1 daddi r3,r0,addr ; load immediate ADDR into r3 Contrast with: dadd r3,r1,r2 ; r3 = r1 + r

5 Logical Operations Set Instructions Register-register: and r3,r2,r1 or r3,r2,r1 xor r3,r2,r1 Register-immediate: ; r3 = r2 bitwise-and r1 ; r3 = r2 bitwise-or r1 ; r3 = r2 bitwise-xor r1 slt r3,r1,r2 ; set r3 if r1 < r2, otherwise r3 = 0 slti r3,r1,value ; set r3 if r1 < VALUE, otherwise r3 = 0 A register is "set": if it is not zero. andi r3,r2,value ; r3 = r2 bitwise-and VALUE ori r3,r2,value ; r3 = r2 bitwise-or VALUE xori r3,r2,value ; r3 = r2 bitwise-xor VALUE Shift Instructions Branches and Jumps dsll r2,r1,bits dsrl r2,r1,bits dsra r2,r1,bits ; logical shift left by BITS bits ; logical shift right by BITS bits ; arithmetic shift right by BITS bits ; sign extended 19 20

6 Jumps Branches Jumps are unconditional: Branches are conditional: j ADDR ; jump to immediate ADDR jal ADDR ; jump to immediate ADDR ; leaving return address in r31 jr r1 Note ; jump to address in r1 The instruction following a jump is in the branch delay slot, if enabled. beq r1,r2,addr bne r1,r2,addr ; branch to ADDR if r1 == r2 ; branch to ADDR if r1!= r2 beqz r1,addr ; branch to ADDR if r1 == 0 bnez r1,addr ; branch to ADDR if r1!= 0 Note The instruction following a branch is in the branch delay slot, if enabled Assembler Directives Data and Code Segments Directives are not instructions: rather, they instruct the assembler in its operation.data.text ; start of data (memory) segment ; memory directives go here ; start of code segment ; instructions go here 23 24

7 This is correct too Data Segment.text.data ; start of code segment ; instructions go here ; start of data (memory) segment ; memory directives go here B:.byte 1 ; allocate a byte, 1 byte H:.word16 1 ; allocate a half word, 2 bytes W:.word32 1 ; allocate a word, 4 bytes D:.word 1 ; allocate a double, 8 bytes F:.double 1.0 ; allocate a floating-point value Note In each case, the memory allocated is suitably aligned Data Segment A:.space 1024 ; leave 1024 bytes unallocated ; for example, space for an array S:.asciiz "Hello" ; allocate a null-terminated string Done <script> (function() { var mathjax = 'mathjax/mathjax.js?config=asciimath'; var element; element = document.createelement('script'); element.async = false; element.src = mathjax; element.type = 'text/javascript'; (document.getelementsbytagname('head')[0] document.body).appendchild(element); })(); </script> 27 28