Chapter 3. Gate-Level Minimization. Outlines

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1 Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 2

2 3. Introduction Why do we need logic minimization? Minimize the number of gates used (gate count) Minimize the total delay (critical path delay) in order to improve speed Satisfy design constrains such as max fanins and fanouts Remove undesired circuit behavior such as hazard and race 3 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 4

3 THE MAP METHOD The map method is also known as the Karnaugh map or K-map The map method provides a simple straightforward procedure for minimizing Boolean function. The simplified expressions produced by the map are always in one of the two standard forms: Sum of Products (SOP) Product of Sums (POS) 5 Two Variable Map 6

4 Two Variable Map 7 K-map three variable (/3) 8

5 K-map three variable (2/3) Example 3- F (x, y, z) = Σ(2,3,4,5) F = x y + xy m3 + m2 = x yz + x yz = x y (z + z) = x y m4 + m5 = xy z + xy z = xy (z + z) = xy 9 K-map three variable (3/3) Example 3-3 Example 3-2 F( x, y, z) = (,2,4,5,6) = z' + xy' F( x, y, z) = (3,4,6,7) = yz + xz'

6 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) K-map four variable 2

7 K-map four variable Example 3-6 F( A, B, C, D) = (,,2,6,8,9,) = B' C' + A' CD' + B' D' 3 K-map five variable 4

8 K-map five variable F = A' B' E' + BD' E + ACE 5 Implicates (cubes) Terminologies A group of minterms that form cube Prime implicates (cubes) a term obtained by combining the maximum possible number of adjacent squares in the map Essential Implicates (cubes) Implicates contains minterms that are not included by other implicates Cover All the s are included by the selected implicates 6

9 Prime Implicates-Procedure Circle all prime implicates on the k-map Identify and select all essential prime implicates Select a minimum subset of the remaining prime Implicates to complete the cover 7 F( A, B, C, D) Prime Implicates = (,2,3,5,7,8,9,,,3,5) CD + AD CD + AB' F = BD + B' D' + B' C + AD B' C + AB' 8

10 Five Variable Map Variable A distinguishes between the two maps 9 Five Variable Map F( A, B, C, D, E) = (,2,4,6,9,3,2,23,25,29,3) F=A B E +BD E+ACE 2

11 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 2 Product of Sums Simplification (/2) The complement of a function is represented in the map by the squares not marked by s We obtain a simplified expression of the complement of the function Example 3-8 F( A, B, C, D) = (,,2,5,8,9,) =B D +B C +A C D (sum of products) =(A +B )(C +D )(B +D) (product of sums) 22

12 Product of Sums Simplification (2/2) 23 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 24

13 Don t Care Conditions An X inside a square in the map indicates that we don't care whether the value of or is assigned to F for the particular minterm Example 3-9 F( w, x, y, z) = d( w, x, y, z) = (,3,7,,5) (,2,5) 25 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 26

14 NAND and NOR Implementation Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gate NAND gate NOT operation (Inverter) AND operation (AND gate) OR operation (OR gate) NOR operation (NOR gate) NOR gate NOT operation (Inverter) AND operation (AND gate) OR operation (OR gate) NAND operation (NAND gate) 27 NAND Circuits Logic operations with NAND gate 28

15 NAND Circuits 29 Two level implementation It implements can be easily converted to a sum of products form by using DeMorgan s theorem F=((AB) (CD) ) =AB+CD 3

NAND Implementation (/2) Example 3- F (x, y, z) = Σ(,2,3,4,5,7) F = xy + x y + z 3 NAND Implementation (2/2) The procedure for obtaining the logic diagram from a Boolean function is as follows:.

16 NAND Implementation (/2) Example 3- F (x, y, z) = Σ(,2,3,4,5,7) F = xy + x y + z 3 NAND Implementation (2/2) The procedure for obtaining the logic diagram from a Boolean function is as follows:. Simplify the function and express it in sum of products. 2. Draw a NAND gate for each product term of the expression that has at least two literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates. 3. Draw a single gate using the AND-inverter or the inverter- OR graphic symbol in the second level, with inputs coming from outputs of first level gates. 4. A term with a single literal requires an inverter in the first level. However, if the single literal is complemented, it can be connected directly to an input of the second level NAND gate. 32

17 Multilevel NAND Circuits The general procedure for converting a multilevel AND-OR diagram into an all-nand diagram using mixed notation is as follows: Convert all AND gates to NAND gates with ANDinvert graphic symbols Convert all OR gates to NAND gates with invert- OR graphic symbols Check all the bubbles in the diagram 33 Multilevel NAND Circuits EXAMPLE:F=A(CD + B) + BC 34

18 NOR Circuit Logic Operations with NOR Gates 35 NOR Circuit 36

19 NOR Implementation Example:F=(A+B)(C+D)E 37 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 38

20 Other Two-Level Implementations Some NAND or NOR gates (but not all) allow the possibility of a wire connection between the outputs of two gates to provide a specific logic function. This type of logic is called wired logic. 39 Nondegenerate forms The eight nondegenerate forms are as follows: AND-OR NAND-NAND NOR-OR OR-NAND OR-AND NOR-NOR NAND-AND AND-NOR 4

21 AND-OR-INVERT Implementation 4 OR-AND-INVERT Implementation 42

22 OR-AND-INVERT Implementation 43 Other Two-level Implementations Ex. Example 3- F = x y + xy + z F = (x y + xy + z) 44

23 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 45 Exclusive-OR Function The exclusive-or (XOR), denoted by the symbol Logic operation X Y = XY + X Y It is equal to if only x is equal to or if only y is equal to, but not when both are equal to Truth table & K-map: 46

24 Exclusive-OR Function Truth table & K-map: A B C F 47 Exclusive-OR Implementations 48

25 Exclusive-NOR Function The exclusive-nor (XNOR), denoted by the symbol Logic operation X y = xy + x y It is equal to if both x and y are equal to or if both are equal to 49 Exclusive-NOR Function Truth table & K-map: A B C F 5

26 Odd Function The multiple-variable exclusive-or operation is defined as an odd function A B C F 5 Parity Generation and Checking Exclusive-OR functions are very useful in system requiring error-detection and correction codes The circuit that generates the parity bit in the transmitter is called a parity generator The circuit that checks the parity in the receiver is called a parity checker 52

27 Parity Generation and Checking Example: 3-bit message to be transmitted together with an even parity bit P=x y z 53 Parity Generation and Checking Example: 3-bit message to be transmitted together with an even parity bit P=x y z 54

28 Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level Implementations Exclusive-OR Function Hardware Description Language (HDL) 55 Hardware Description Language (HDL) A Hardware Description Language (HDL) is a high-level programming language with special constructs used to model the function of hardware logic circuits The special language constructs provide you the ability to : Describe The Connectivity Of The Circuit Describe The Functionality Of A Circuit Describe A Circuit At Various Levels Of Abstraction Describe The Timing Of A Circuit Express Concurrency 56

29 Hardware Description Language (HDL) HDLs share several features in common: Typically, an HDL contains some high-level programming language constructs, along with constructs to describe the connectivity of the hardware design An HDL allows you to describe the design at various levels of abstraction using structural or behavioral constructs An HDL allows you to describe the functionality of the hardware, along with its timing constraints Concurrency, which is the ability to perform multiple tasks at the same time. Typically, programming languages are not concurrent, but in hardware a number of operations happen at the same time. Thus, an HDL must be concurrent. 57 HDL Example HDL Example 3- //Description of simple circuit Fig module smpl_circuit (A, B, C, x, y); input A, B, C; output x, y; wire e; and g (e, A, B); not g2 (y, C); or g3 (x, e, y); endmodule 58

Gate Level Minimization Map Method

Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically