EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design
|
|
- Lee Lawson
- 10 months ago
- Views:
Transcription
1 EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda Electrical Sciences and Computer Engineering School of Engineering Brown University Spring
2 ISA is the HW/SW interface ISA SW HW ISA choice determines: program size (& memory size) complexity of hardware (CPI and f) execution time for different applications and domains power consumption die area (cost) 2
3 Stored program concept (von Neumann model) The BIG Picture n Instructions represented in binary numbers, just like data n Instructions and data stored in memory n Programs can operate on programs n e.g., compilers, linkers, n Binary compatibility allows compiled programs to work on different computers n Standardized ISAs 3
4 Steps in execution of a program Fetch PC Decode instruction Fetch Operands Execute instruction Store result What is instruction format / size? how is it decoded? Where are the operands located? What are their sizes? What are supported operations? How to determine the successor instruction? Update PC 4
5 Example of an instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 assembly language special $s1 $s2 $t0 0 add = machine language 5
6 ISA design choices Number, size (fixed/variable) and format of instructions Operations supported (arithmetic, logical, string, floating point, jump, etc) Operands supported (bytes, words, signed, unsigned, floating, etc) Operand storage (accumulator, stack, registers, memory) Addressing modes 6
7 Typical operations Data Movement Arithmetic Shift Logical Control (Jump/Branch) Subroutine Linkage Interrupt Synchronization Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) integer (binary + decimal) or FP Add, Subtract, Multiply, Divide shift left/right, rotate left/right not, and, or, set, clear unconditional, conditional call, return trap, return test & set (atomic r-m-w) search, translate [slide from M. Martin] 7
8 Classification of ISAs [Figure from D. Brooks -- Harvard] These ISAs give different characteristics in terms of size of programs, number of instructions and CPI. 8
9 Examples of ISA Instruction sequence for C = A + B for the four ISAs Stack Accumulator Register (registermemory) Register (load-store) Push A Push B Add Pop C Load A Add B Store C Load R1, A Add R1, B Store C, R1 Load R1, A Load R2, B Add R3, R1, R2 Store C, R3 Some architectures (e.g. x86) support hybrid ISAs for different classes of instructions and/or for backward compatibility. 9
10 What makes a good ISA? Efficiency of hardware implementation Convenience of programming / compiling Matches target applications (or generality) Compatibility and portability Four design principles for ISA 1. Simplicity favors regularity 2. Smaller is faster 3. Make the common case fast 4. Good design demands good compromises ISA design is an art! 10
11 Popular ISAs x86 from Intel (laptops, servers) ARM (mobile devices) MIPS (embedded devices) Power and PowerPC from IBM (servers, old Macs) and many others still spoken and dead ISAs 11
12 MIPS architecture: Example of Reduced Instruction Set Computer (RISC) architecture Used as the example throughout the course Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs 32 bit and 64 bit available Will implement and boot a subset MIPS processor in lab 12
13 Arithmetic operations High-level code a = b + c; a = b - c; MIPS assembly code # $s0 = a, $s1 = b, $s2 = c add $s0, $s1, $s2 sub $s0, $s1, $s2 add: mnemonic indicates what operation to perform $s1, $s1: source operands on which the operation is performed $s0: destination operand to which the result is written n Design Principle 1: Simplicity favors regularity n n Regularity makes implementation simpler Simplicity enables higher performance at lower cost 13
14 Register operands Memory is slow. Most architectures have a small set of (fast) registers MIPS has a bit register file n n n Use for frequently accessed data n Numbered 0 to 31 n 32-bit data called a word n Written with a $ before their name Assembler names n $0 always hold value 0 n $t0, $t1,, $t9 for temporary values n $s0, $s1,, $s7 for saved variables Design Principle 2: Smaller is faster n c.f. main memory: millions of locations 14
15 MIPS registers Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary $v0-$v1 2-3 procedure return values $a0-$a3 4-7 procedure arguments $t0-$t temporaries $s0-$s saved variables $t8-$t more temporaries $k0-$k OS temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 procedure return address 15
16 Format of R-type instructions R-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Register-type 3 register operands: rs, rt: source registers rd: destination register Other fields: op: the operation code or opcode (0 for R-type instructions) funct: the function together, the opcode and function tell the computer what operation to perform shamt: the shift amount for shift instructions, otherwise it s 0 16
17 R-Type examples Assembly Code add $s0, $s1, $s2 sub $t0, $t3, $t5 Field Values op rs rt rd shamt funct bits 5 bits 5 bits 5 bits 5 bits 6 bits Machine Code op rs rt rd shamt funct (0x ) (0x016D4022) 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Note the order of registers in the assembly code: add rd, rs, rt 17
18 Memory operands Too much data to fit in only 32 registers Memory is large, but slow Commonly used variables kept in registers Using a combination of registers and memory, a program can access a large amount of data fairly quickly To apply arithmetic operations n n Load values from memory into registers Store result from register to memory 18
19 Word-addressable memory Each 32-bit data word has a unique address Word Address Data F E E F 2 F 1 A C A B C D E F 7 8 Word 3 Word 2 Word 1 Word 0 19
20 Reading word-addressable memory Memory reads are called loads Mnemonic: load word (lw) Example: read a word of data at memory address 1 into $s3 Memory address calculation: add the base address ($0) to the offset (1) address = ($0 + 1) = 1 Any register may be used to store the base address. $s3 holds the value 0xF2F1AC07 after the instruction completes. Assembly code lw $s3, 1($0) # read memory word 1 into $s3 Word Address Data F E E F 2 F 1 A C A B C D E F 7 8 Word 3 Word 2 Word 1 Word 0 20
21 Writing word-addressable memory Memory writes are called stores Mnemonic: store word (sw) Example: Write (store) the value held in $t4 into memory address 7 Offset can be written in decimal (default) or hexadecimal Memory address calculation: add the base address ($0) to the offset (0x7) address: ($0 + 0x7) = 7 Any register may be used to store the base address Assembly code sw $t4, 0x7($0) # write the value in $t4 # to memory word 7 Word Address Data F E E F 2 F 1 A C A B C D E F 7 8 Word 3 Word 2 Word 1 Word 0 21
22 Byte-addressable memory Each data byte has a unique address Load/store words or single bytes: load byte (lb) and store byte (sb) Each 32-bit words has 4 bytes, so the word address increments by 4 Word Address Data C F E E F 2 F 1 A C 0 7 A B C D E F 7 8 width = 4 bytes Word 3 Word 2 Word 1 Word 0 22
23 Reading byte-addressable memory The address of a memory word must now be multiplied by 4. For example, the address of memory word 2 is 2 4 = 8 the address of memory word 10 is 10 4 = 40 (0x28) Load a word of data at memory address 4 into $s3. $s3 holds the value 0xF2F1AC07 after the instruction completes. MIPS is byte-addressed, not word-addressed. MIPS assembly code lw $s3, 4($0) # read word at address 4 into $s3 Word Address Data C F E E F 2 F 1 A C 0 7 A B C D E F 7 8 Word 3 Word 2 Word 1 Word 0 width = 4 bytes 23
24 Writing byte-addressed memory Example: stores the value held in $t7 into memory address 0x2C (44) MIPS assembly code sw $t7, 44($0) # write $t7 into address 44 Word Address Data C F E E F 2 F 1 A C 0 7 A B C D E F 7 8 width = 4 bytes Word 3 Word 2 Word 1 Word 0 24
25 Big-Endian and little-endian How to number bytes within a word? Word address is the same for big- or little-endian Little-endian: byte numbers start at the little (least significant) end Big-endian: byte numbers start at the big (most significant) end Big-Endian Little-Endian Byte Address Word Address Byte Address C D E F 8 9 A B MSB LSB C F E D C B A MSB LSB 25
26 Big- and little- Endian example Suppose $t0 initially contains 0x After the following program is run on a big-endian system, what value does $s0 contain? In a little-endian system? sw $t0, 0($0) lb $s0, 1($0) Big-endian: 0x Little-endian: 0x Byte Address Data Value Big-Endian Word Address 0 Little-Endian MSB LSB MSB LSB Byte Address Data Value 26
27 Design principle 4 in action Good design demands good compromises - Multiple instruction formats allow flexibility - add, sub: use 3 register operands - lw, sw: use 2 register operands and a constant - Number of instruction formats kept small - to adhere to design principles 1 and 3 (simplicity favors regularity and smaller is faster). 27
28 Constant/Immediate operands lw and sw illustrate the use of constants or immediates Called immediates because they are immediately available from the instruction Immediates don t require a register or memory access. The add immediate (addi) instruction adds an immediate to a variable (held in a register). An immediate is a 16-bit two s complement number. Is subtract immediate (subi) necessary? High-level code a = a + 4; b = a 12; MIPS assembly code # $s0 = a, $s1 = b addi $s0, $s0, 4 addi $s1, $s0,
29 I-Type format instructions Immediate-type 3 operands: rs, rt: register operands imm: 16-bit two s complement immediate Other fields: op: the opcode Simplicity favors regularity: all instructions have opcode Operation is completely determined by the opcode I-Type op rs rt imm 6 bits 5 bits 5 bits 16 bits 29
30 I-Type examples Assembly Code addi $s0, $s1, 5 addi $t0, $s3, -12 lw $t2, 32($0) Field Values op rs rt imm sw $s1, 4($t1) bits 5 bits 5 bits 16 bits Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw sw rt, imm(rs) rt, imm(rs) Machine Code op rs rt imm bits 5 bits 5 bits 16 bits (0x ) (0x2268FFF4) (0x8C0A0020) (0xAD310004) 30
31 Logical operations n Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor n Useful for extracting and inserting groups of bits in a word 31
32 Shift operations op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits n shamt: how many positions to shift n Shift left logical n Shift left and fill with 0 bits n sll by i bits multiplies by 2 i n Shift right logical n Shift right and fill with 0 bits n srl by i bits divides by 2 i (unsigned only) 32
33 AND operations n Useful to mask bits in a word n Select some bits, clear others to 0 and $t0, $t1, $t2 $t2 $t1 $t
34 OR operations n Useful to include bits in a word n Set some bits to 1, leave others unchanged or $t0, $t1, $t2 $t2 $t1 $t
35 NOT operations n Useful to invert bits in a word n Change 0 to 1, and 1 to 0 n MIPS has NOR 3-operand instruction n a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero Register 0: always read as zero $t1 $t
36 Conditional operators n Branch to a labeled instruction if a condition is true n Otherwise, continue sequentially n beq rs, rt, L1 n if (rs == rt) branch to instruction labeled L1; n bne rs, rt, L1 n if (rs!= rt) branch to instruction labeled L1; n j L1 n unconditional jump to instruction labeled L1 36
37 Compiling if statement n C code: if (i==j) f = g+h; else f = g-h; n f, g, in $s0, $s1, n Compiled MIPS code: bne $s3, $s4, Else add $s0, $s1, $s2 j Exit Else: sub $s0, $s1, $s2 Exit: 37
38 Compiling loop statements n C code: while (save[i] == k) i += 1; n i in $s3, k in $s5, address of save in $s6 n Compiled MIPS code: Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, 1 j Loop Exit: 38
39 More conditional operations n Set result to 1 if a condition is true n Otherwise, set to 0 n slt rd, rs, rt n if (rs < rt) rd = 1; else rd = 0; n slti rt, rs, constant n if (rs < constant) rt = 1; else rt = 0; n Use in combination with beq, bne slt $t0, $s1, $s2 # if ($s1 < $s2) bne $t0, $zero, L # branch to L 39
40 Branch instruction design n Why not blt, bge, etc? n Hardware for <,, slower than =, n Combining with branch involves more work per instruction, requiring a slower clock n All instructions penalized! n beq and bne are the common case n This is a good design compromise 40
41 Summary of instruction formats R-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-Type op rs rt imm 6 bits 5 bits 5 bits 16 bits J-Type op addr 6 bits 26 bits 41
42 Procedure calls Procedure calling conventions: Caller: passes arguments to callee. jumps to the callee Callee: performs the procedure returns the result to caller returns to the point of call must not overwrite registers or memory needed by the caller MIPS conventions: Call procedure: jump and link (jal) Return from procedure: jump register (jr) Argument values: $a0 - $a3 Return value: $v0 -$v1 42
43 Procedure calls High-level code int main() { simple(); a = b + c; } void simple() { return; } MIPS assembly code 0x main: jal simple 0x add $s0, $s1, $s2... 0x simple: jr $ra void means that simple doesn t return a value. jal: jumps to simple and saves PC+4 in the return address register ($ra). In this case, $ra = 0x after jal executes. jr $ra: jumps to address in $ra, in this case 0x
44 Input arguments and return values High-level code int main() { } int y;... y = diffofsums(2, 3, 4, 5); // 4 arguments... int diffofsums(int f, int g, int h, int i) { } int result; result = (f + g) - (h + i); return result; // return value 44
45 Input arguments and return values MIPS assembly code MIPS conventions: Argument values: $a0 - $a3 Return value: $v0 main:... addi $a0, $0, 2 # argument 0 = 2 addi $a1, $0, 3 # argument 1 = 3 addi $a2, $0, 4 # argument 2 = 4 addi $a3, $0, 5 # argument 3 = 5 jal diffofsums # call procedure add $s0, $v0, $0 # y = returned value... # $s0 = result diffofsums: add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller 45
46 Potential problems in procedural calling MIPS assembly code # $s0 = result diffofsums: add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller diffofsums overwrote 3 registers: $t0, $t1, and $s0 diffofsums can use the stack to temporarily store registers 46
47 The stack Memory used to temporarily save variables Like a stack of dishes, last-in-first-out (LIFO) queue Expands: uses more memory by growing down (from higher to lower memory addresses) when more space is needed Contracts: uses less memory when the space is no longer needed Stack pointer: $sp, points to top of the stack Address Data Address Data 7FFFFFFC $sp 7FFFFFFC FFFFFF8 7FFFFFF8 AABBCCDD 7FFFFFF4 7FFFFFF $sp 7FFFFFF0 7FFFFFF0 47
48 How procedures use the stack Called procedures must have no other unintended side effects. But diffofsums overwrites 3 registers: $t0, $t1, $s0 # MIPS assembly # $s0 = result diffofsums: add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller 48
49 Storing register values on the stack # $s0 = result diffofsums: addi $sp, $sp, -12 # make space on stack # to store 3 registers sw $s0, 8($sp) # save $s0 on stack sw $t0, 4($sp) # save $t0 on stack sw $t1, 0($sp) # save $t1 on stack add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 lw $t1, 0($sp) # restore $t1 from stack lw $t0, 4($sp) # restore $t0 from stack lw $s0, 8($sp) # restore $s0 from stack addi $sp, $sp, 12 # deallocate stack space jr $ra # return to caller Address Data Address Data Address Data FC? $sp FC? FC? $sp F8 F4 F0 stack frame F8 F4 F0 $s0 $t0 $t1 $sp F8 F4 F0 (a) (b) (c) 49
50 Protocol for preserving registers Preserved Nonpreserved Callee-Saved Caller-Saved $s0 - $s7 $t0 - $t9 $ra $a0 - $a3 $sp $v0 - $v1 stack above $sp stack below $sp 50
51 Multiple procedure calls proc1: addi $sp, $sp, -4 # make space on stack sw $ra, 0($sp) # save $ra on stack jal proc2... lw $ra, 0($sp) # restore $s0 from stack addi $sp, $sp, 4 # deallocate stack space jr $ra # return to caller 51
52 Storing saved registers on the stack # $s0 = result diffofsums: addi $sp, $sp, -4 # make space on stack to sw $s0, 0($sp) # store one register # save $s0 on stack add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i # no need to save $t0 or $t1 sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra # restore $s0 from stack # deallocate stack space # return to caller 52
53 Recursive procedure calls High-level code int factorial(int n) { } if (n <= 1) else return 1; return (n * factorial(n-1)); 53
54 Recursive procedure calls MIPS assembly code 0x90 factorial: addi $sp, $sp, -8 # make room 0x94 sw $a0, 4($sp) # store $a0 0x98 sw $ra, 0($sp) # store $ra 0x9C addi $t0, $0, 2 0xA0 slt $t0, $a0, $t0 # a <= 1? 0xA4 beq $t0, $0, else # no: go to else 0xA8 addi $v0, $0, 1 # yes: return 1 0xAC addi $sp, $sp, 8 # restore $sp 0xB0 jr $ra # return 0xB4 else: addi $a0, $a0, -1 # n = n - 1 0xB8 jal factorial # recursive call 0xBC lw $ra, 0($sp) # restore $ra 0xC0 lw $a0, 4($sp) # restore $a0 0xC4 addi $sp, $sp, 8 # restore $sp 0xC8 mul $v0, $a0, $v0 # n * factorial(n-1) 0xCC jr $ra # return 54
55 Stack during recursive calls Address Data Address Data Address Data FC $sp FC $sp FC $sp $v0 = 6 F8 F4 F0 F8 F4 F0 $a0 (0x3) $ra $a0 (0x2) $sp F8 F4 F0 $a0 (0x3) $ra $a0 (0x2) $sp $a0 = 3 $v0 = 3 x 2 EC E8 E4 E0 EC E8 E4 E0 $ra (0xBC) $a0 (0x1) $ra (0xBC) $sp $sp EC E8 E4 E0 $ra (0xBC) $a0 (0x1) $ra (0xBC) $sp $sp $a0 = 2 $v0 = 2 x 1 $a0 = 1 $v0 = 1 x 1 DC DC DC 55
56 Procedural call summary Caller Put arguments in $a0-$a3 Save any registers that are needed ($ra, maybe $t0-t9) jal callee Restore registers Look for result in $v0 Callee Save registers that might be disturbed ($s0-$s7) Perform procedure Put result in $v0 Restore registers jr $ra 56
57 x86 ISA: Example of Complex Instruction Set Computer (CISC) architecture n Backward compatibility instruction set doesn t change n But they do accumulate more instructions Rank instruction Integer Average Percent total executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move register-register 4% 9 call 1% 10 return 1% Total 96% Simple instructions dominate instruction frequency x86 instruction set 57
58 x86 registers 58
59 x86 assembly language examples # move the 4 bytes in memory at the address contained in EBX into EAX mov eax, [ebx] # move the 4 bytes of data at address ESI+4*EBX into EDX mov edx, [esi+4*ebx] # eax = eax + ebx add eax, ebx # add ebx to memory content at address memory_location add memory_location, ebx # add 10 the data at address EAX add [eax], 10 # push content of eax into top of stack push eax # compare two registers, register memory or memory memory cmp eax, ebx cmp [eax], [ebx] # conditional jumps jl, jeq, jg, jge, jle, jne 59
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
EN164: Design of Computing Systems Lecture 09: Processor / ISA 2
EN164: Design of Computing Systems Lecture 09: Processor / ISA 2 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
EN164: Design of Computing Systems Lecture 11: Processor / ISA 4
EN164: Design of Computing Systems Lecture 11: Processor / ISA 4 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
MIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
CS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
Architecture I. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture I Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Architecture (1) the attributes of a system as seen by the
Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.
Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood
Computer Architecture. Lecture 2 : Instructions
Computer Architecture Lecture 2 : Instructions 1 Components of a Computer Hierarchical Layers of Program Code 3 Instruction Set The repertoire of instructions of a computer 2.1 Intr roduction Different
Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
Architecture. Digital Computer Design
Architecture Digital Computer Design Architecture The architecture is the programmer s view of a computer. It is defined by the instruction set (language) and operand locations (registers and memory).
ECE 154A Introduction to. Fall 2012
ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi
Chapter 2. Instruction Set Architecture (ISA)
Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:
All instructions have 3 operands Operand order is fixed (destination first)
Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/
Chapter 2. Instruction Set. RISC vs. CISC Instruction set. The University of Adelaide, School of Computer Science 18 September 2017
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface RISC-V Edition Chapter 2 Instructions: Language of the Computer These slides are based on the slides by the authors. The slides doesn t
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
ECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero
Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
Forecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer
Instructions (354 Review) Forecast Instructions are the words of a computer Instruction set architecture (ISA) is its vocabulary With a few other things, this defines the interface of computers But implementations
Architecture II. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a
Typical Processor Execution Cycle
Typical Processor Execution Cycle Instruction Fetch Obtain instruction from program storage Instruction Decode Determine required actions and instruction size Operand Fetch Locate and obtain operand data
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
MIPS ISA and MIPS Assembly. CS301 Prof. Szajda
MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done
ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H. Lipasti. University of Wisconsin-Madison. Basics Registers and ALU ops
ECE/CS 552: Instruction Sets Instructor:Mikko H. Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill. Instructions (354 Review) Instructions are
A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture
COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access
CSE Lecture In Class Example Handout
CSE 30321 Lecture 07-08 In Class Example Handout Part A: J-Type Example: If you look in your book at the syntax for j (an unconditional jump instruction), you see something like: e.g. j addr would seemingly
We will study the MIPS assembly language as an exemplar of the concept.
MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and
Concocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von
Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College
Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor
Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:
Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators
Chapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language g of the Computer Outlines Introduction to MIPS machine Operations of the Computer HW Operands of the Computer HW Representing instructions in the Computer Logical Operations
Lecture 2: RISC V Instruction Set Architecture. Housekeeping
S 17 L2 1 18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University Housekeeping S 17 L2 2 Your goal today get bootstrapped on RISC V RV32I to start
Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology
Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.
MIPS (SPIM) Assembler Syntax
MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin
CS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
Lecture 2: RISC V Instruction Set Architecture. James C. Hoe Department of ECE Carnegie Mellon University
18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L02 S1, James C. Hoe, CMU/ECE/CALCM, 2018 Your goal today Housekeeping get bootstrapped
Lecture 3: The Instruction Set Architecture (cont.)
Lecture 3: The Instruction Set Architecture (cont.) COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Review: Instructions Computers process information
CS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: October 1, 2014 at 12:03 CS429 Slideset 6: 1 Topics
Shift and Rotate Instructions
Shift and Rotate Instructions Shift and rotate instructions facilitate manipulations of data (that is, modifying part of a 32-bit data word). Such operations might include: Re-arrangement of bytes in a
CS3350B Computer Architecture MIPS Procedures and Compilation
CS3350B Computer Architecture MIPS Procedures and Compilation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
CSE Lecture In Class Example Handout
CSE 30321 Lecture 07-09 In Class Example Handout Part A: A Simple, MIPS-based Procedure: Swap Procedure Example: Let s write the MIPS code for the following statement (and function call): if (A[i] > A
Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21
2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...
Chapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
COMP MIPS instructions 2 Feb. 8, f = g + h i;
Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers ($0,..., $31) in any instruction. This is not so, however.
A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction
page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches
EE108B Lecture 3. MIPS Assembly Language II
EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework
CPS311 - COMPUTER ORGANIZATION. A bit of history
CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer
EN164: Design of Computing Systems Topic 06.b: Superscalar Processor Design
EN164: Design of Computing Systems Topic 06.b: Superscalar Processor Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
ISA: The Hardware Software Interface
ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important
Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats
Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:
Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations
Real instruction set architectures. Part 2: a representative sample
Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local
Lecture Topics. Branch Condition Options. Branch Conditions ECE 486/586. Computer Architecture. Lecture # 8. Instruction Set Principles.
ECE 486/586 Computer Architecture Lecture # 8 Spring 2015 Portland State University Instruction Set Principles MIPS Control flow instructions Dealing with constants IA-32 Fallacies and Pitfalls Reference:
Midterm. CS64 Spring Midterm Exam
Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every
Five classic components
CS/COE0447: Computer Organization and Assembly Language Chapter 2 modified by Bruce Childers original slides by Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or
Patterson PII. Solutions
Patterson-1610874 978-0-12-407726-3 PII 2 Solutions Chapter 2 Solutions S-3 2.1 addi f, h, -5 (note, no subi) add f, f, g 2.2 f = g + h + i 2.3 sub $t0, $s3, $s4 add $t0, $s6, $t0 lw $t1, 16($t0) sw $t1,
Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary
Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework
Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA
EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed
Mips Code Examples Peter Rounce
Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then
MIPS PROJECT INSTRUCTION SET and FORMAT
ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction
Instruction Set Architecture (ISA)
Instruction Set Architecture (ISA)... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data
SPIM Instruction Set
SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large
Lecture 6: Assembly Programs
Lecture 6: Assembly Programs Today s topics: Procedures Examples Large constants The compilation process A full example 1 Procedures Local variables, AR, $fp, $sp Scratchpad and saves/restores, $fp Arguments
ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points)
ECE 473 Computer Architecture and Organization Lab 4: MIPS Assembly Programming Due: Wednesday, Oct. 19, 2011 (30 points) Objectives: Get familiar with MIPS instructions Assemble, execute and debug MIPS
CS 61c: Great Ideas in Computer Architecture
MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0
Field 6-Bit Op Code rs Field rt Field 16-bit Immediate field
Introduction to MIPS Instruction Set Architecture The MIPS used by SPIM is a 32-bit reduced instruction set architecture with 32 integer and 32 floating point registers. Other characteristics are as follows:
Concocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Lab is posted. Do your prelab! Stay tuned for the first problem set. L04 Instruction
The Single Cycle Processor
EECS 322 Computer Architecture The Single Cycle Processor Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow CWRU
Procedures and Stacks
Procedures and Stacks Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. March 15, 2018 L10-1 Announcements Schedule has shifted due to snow day Quiz 2 is now on Thu 4/12 (one week later)
MIPS Assembly Programming
COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2
Code Generation. The Main Idea of Today s Lecture. We can emit stack-machine-style code for expressions via recursion. Lecture Outline.
The Main Idea of Today s Lecture Code Generation We can emit stack-machine-style code for expressions via recursion (We will use MIPS assembly as our target language) 2 Lecture Outline What are stack machines?
Assembly Programming
Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming
Compiling Techniques
Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically
Chapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14
CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but
Practical Malware Analysis
Practical Malware Analysis Ch 4: A Crash Course in x86 Disassembly Revised 1-16-7 Basic Techniques Basic static analysis Looks at malware from the outside Basic dynamic analysis Only shows you how the
EE 109 Unit 8 MIPS Instruction Set
1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system
The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.
IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture 00 01 02 03 PC IR Control Unit Command Memory ALU 96 97 98 99 Notice: This session
MIPS Processor Overview
MIPS Processor Cptr280 Dr Curtis Nelson MIPS Processor Overview Hardware Design philosophy Architecture Software Assembly language program structure QTSpim simulator Example programs 1 MIPS Processor Power
Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
The Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
Chapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
MIPS Reference Guide
MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming
Procedure Call Instructions
Procedure Calling Steps required 1. Place parameters in registers x10 to x17 2. Transfer control to procedure 3. Acquire storage for procedure 4. Perform procedure s operations 5. Place result in register
Solutions for Chapter 2 Exercises
Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642
Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
Orange Coast College. Business Division. Computer Science Department CS 116- Computer Architecture. The Instructions
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Instructions 1 1 Topics: Assembly language, assemblers MIPS R2000 Assembly language Instruction set
CMSC Computer Architecture Lecture 2: ISA. Prof. Yanjing Li Department of Computer Science University of Chicago
CMSC 22200 Computer Architecture Lecture 2: ISA Prof. Yanjing Li Department of Computer Science University of Chicago Administrative Stuff! Lab1 is out! " Due next Thursday (10/6)! Lab2 " Out next Thursday
Computer Organization CS 206 T Lec# 2: Instruction Sets
Computer Organization CS 206 T Lec# 2: Instruction Sets Topics What is an instruction set Elements of instruction Instruction Format Instruction types Types of operations Types of operand Addressing mode
Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...
Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,
Processor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
Programming at different levels
CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 EMY MNEMONIC MACHINE LANGUAGE PROGRAMMING EXAMPLES Programming at different levels CS1114 Mathematical Problem : a = b + c CS2214 CS2214 The C-like
CSE A215 Assembly Language Programming for Engineers
CSE A215 Assembly Language Programming for Engineers Lecture 7 MIPS vs. ARM (COD Chapter 2 and Exam #1 Review) October 12, 2012 Sam Siewert Comparison of MIPS32 and ARM Instruction Formats and Addressing
Virtual Machines and Dynamic Translation: Implementing ISAs in Software
Virtual Machines and Dynamic Translation: Implementing ISAs in Software Krste Asanovic Laboratory for Computer Science Massachusetts Institute of Technology Software Applications How is a software application
The Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)