INSTRUCTION SET ARCHITECTURE

Transcription

1 INSTRUCTION SET ARCHITECTURE Slides by: Pedro Tomás Additional reading: Computer Architecture: A Quantitative Approach, 5th edition, Appendix A, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2011 ADVANCED COMPUTER ARCHITECTURES ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)

2 Outline 2 Instruction Set Architecture (ISA) Classes of ISA RISC vs CISC architectures Memory addressing modes and data organization Typical set of instructions

3 Instruction Set Architecture (ISA) Machine vs Assembly code 3 An instruction in machine code generally corresponds to a set of bits that can be generally structured as: OPCODE Identification of the operation OPERANDS Set of source and/or destination operands MODE (optional) Addressing mode of the operation CONDITION (optional) Instruction execution condition OPCODE MODE CONDITION OPERANDS The same operation can be represented in assembly code as: <Mnemonic> <operand listing>

4 Instruction Set Architecture (ISA) CLASSES 4 Instructions can be divided into the following classes: 1. Stack 2. Accumulator 3. Register-Memory 4. Register-Register / Load-Store Modern architectures typically support multiple classes of ISAs Further details

5 Instruction Set Architecture (ISA) Classes STACK 5 A B Stack architectures typically have no explicit operands, since operation on the stack is implicit SP Stack Pointer SP Stack Pointer A SP Stack Pointer A B There are two basic operations: PUSH into the stack POP out of the stack (1) Empty Stack (2) After pushing a value into the stack PUSH (3) After pushing another value into the stack PUSH A+B Operations on the stack require: 1. POP operands 2. Compute operation 3. PUSH result SP Stack Pointer A+B (4) After an addition operation ADD ALU SP Stack Pointer (5) After taking a value from the stack POP

6 Instruction Set Architecture (ISA) Classes ACCUMULATOR 6 Memory Memory Architectures based on an accumulator typically have: Operation Select X 1 ALU X 2 A B C 13-5 LOAD X 1 ALU X 2 An implicit operand, the accumulator (ACC) An explicit operand, which can be an immediate (constant value) or a memory address The destination operand is typically the accumulator A B C Memory 13-5 ACC (1) Acummulator-based architecture ADD ACC X 1 ALU 8 X 2 A B C ACC 13 (2) After loading a value to the accumulator LOAD A Memory ACC X 1 ALU 8 X 2 (3) After adding a value with the accumulator ADD B (4) Storing the result back into memory STORE C

7 Instruction Set Architecture (ISA) Classes REGISTER-MEMORY 7 Register-memory ISAs: Memory Registers Typically have two operands, where one is a register and the other a memory address May allow multiple addressing modes: Immediate Register Direct Register indirect Indexed Implicit (next slides ) Example: Operation Select X 1 ALU MOV Ra,A ; Ra M[A] ADD Ra,B ; Ra Ra + M[B] MOV C,Ra ; M[C] Ra X 2 Register memory architecture

8 Instruction Set Architecture (ISA) Classes REGISTER-REGISTER / LOAD-STORE 8 Register-register (also known as load/store) ISAs: Typically have one destination operand plus two source operands All operands are registers Access to the memory is available only through LOAD or STORE instructions Require additional general-use registers Leads to longer programs and larger memory sizes Memory Example: Operation Select LOAD STORE X 1 ALU Register-register / Load-Store architecture LD Ra,A ; Ra M[A] LD Rb,B ; Rb M[B] ADD Rc,Ra,Rb ; Rc Ra + Rb ST C,Rc ; M[C] Rc X 2 Registers

9 Instruction Set Architecture (ISA) RISC vs CISC 9 Based on a register-register / load store class of ISA Lower number of instructions and addressing modes Fixed-size (#bits) instructions Instructions can be executed in a single clock cycle Higher instruction throughput Can support multiple classes of ISAs, including stack, registermemory and register-register Higher number of instructions and addressing modes Variable-size (#bits) instructions Reduces the required length of Assembly code Modern CISC processors (e.g., Intel) operate as RISC by performing real-time translation from CISC to a reduced set of micro-operations

10 Instruction addressing modes 10 Mode Example Meaning REGISTER ADD R4,R3 r[4] r[4] + r[3] IMMEDIATE ADD R4,#3 r[4] r[4] + 3 DIRECT ADD R4,(1001) r[4] r[4] + M[ 1001 ] REGISTER INDIRECT ADD R4,(R3) r[4] r[4] + M[ r[3] ] DISPLACEMENT ADD R4,100(R3) r[4] r[4] + M[ r[3] ] INDEXED ADD R4,(R1+R3) r[4] r[4] + M[ r[1] + r[3] ] MEMORY INDIRECT ADD R4,@(R3) r[4] r[4] + M[ M[ r[3] ] ] AUTO-INCREMENT ADD R4,(R3)+ r[4] r[4] + M[ r[3] ] r[3] r[3] + d AUTO-DECREMENT ADD R4,-(R3) r[3] r[3] - d r[4] r[4] + M[ r[3] ] SCALED ADD R4,100(R2)[R3] R[4] R[4] + M[ r[2] + r[3]*d] Depending on the architecture implementation, some addressing modes may required the use of additional special-purpose register. In this example, the auto-increment, auto-decrement and scaled addressing modes require the use of an additional register to store the value d.

11 Miss-alignments in memory access 11 When the addressed object is longer (in #bits) than the memory width miss-alignments can occur Memory Consider the typical memory organization where each memory address stores an 8-bit object Accessing a single byte never generates a miss-alignment 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 8-bits Aligned 8-bits Aligned

12 Miss-alignments in memory access 12 When the addressed object is longer (in #bits) than the memory width miss-alignments can occur Memory Consider the typical memory organization where each memory address stores an 8-bit object Accessing a half-word (2 bytes) generates a miss-alignment whenever the address is not even (i.e., multiple of 2) 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 16-bits Miss-aligned Aligned 16-bits A miss-aligned memory access may require two clock cycles to complete (depends on the processor word width)

13 Miss-alignments in memory access 13 When the addressed object is longer (in #bits) than the memory width miss-alignments can occur Memory Consider the typical memory organization where each memory address stores an 8-bit object Accessing a word (4 bytes) generates a miss-alignment whenever the address is not multiple of h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 32-bits Miss-aligned Aligned 32-bits A miss-aligned memory access may require two clock cycles to complete (depends on the processor word width)

14 Miss-alignments in memory access 14 To simplify memory access some processors do not allow missaligned memory addressing. In such cases the processor may use more than the required memory space to store the variable. E.g., for an 32-bit architecture (i.e., with 32-bit registers) storing one char (byte) in memory may use 32 bits (depends on the compiler). Some compilers also avoid using miss-aligned memory addresses to increase processing speed.

15 Data organization in memory 15 Consider storing a 32-bit hexadecimal number in memory: 06AB434Ch The word the number can be divided into the 4 bytes: 06h ABh 43h 4Ch Memory Memory Storing the value in memory organized can be done as follows: 8000h 8001h 06h ABh 8000h 8001h 4Ch 43h Little Endian: Store less significant byte in the lower address Big Endian: Store most significant byte in the 8002h 8003h 8004h 8005h 8006h 8007h 8008h 43h 4Ch 8002h 8003h 8004h 8005h 8006h 8007h 8008h ABh 06h lower address Big Endian style Little Endian style

16 Data organization in memory 16 Consider storing a 32-bit hexadecimal number in memory: 06AB434Ch The word the number can be divided into the 4 bytes: 06h ABh 43h 4Ch Storing the value in memory organized can be done Little as follows: Little Endian: Store less significant byte in the Address h1 0 lower address 8005h Big Endian: Big Endian Store most significant byte in the lower address 8000h 8001h 8002h 8003h 8006h 8007h 8008h Memory 06h ABh 06h ABh 43h 4Ch 43h 4Ch 4Ch 43h ABh 06h Big Endian style 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h Memory 4Ch 43h ABh 06h Little Endian style

17 Data organization in memory 17 Example of Endian-ness in computer architectures: MIPS and Microblaze are big endian Intel x86, x86_64 are little endian ARM is bi-endian (i.e., supports both modes) (in ARM architectures endian-ness is defined by the interconnection network to the main memory) IMPORTANT NOTICE: Endian-ness is just the translating of data from memory to registers; in registers endian-ness has no meaning

18 Instruction Set Architecture (ISA) Example data transfer operations 18 Description Assembly Operation Register/Memory Memory/Register Move MOV opa,opb opa opb Exchange ou SWAP XCH opa,opb opa opb, opb opa Register Memory Load LD opa,opb opa M[opB] Store ST opa,opb M[opA] opb Stack Register/Memory Push PUSH opa (defined in following slides) Pop POP opa (defined in following slides) I/O Register/Memory Input IN opa,porto opa peripheral Output OUT Porto,opB peripheral opb

19 Instruction Set Architecture (ISA) Example arithmetic operations 19 Description Assembly Operation Increment INC opa,opb opa opb + 1 Decrement DEC opa,opb opa opb 1 Add ADD opa,opb,opc opa opb + opc Subtract SUB opa,opb,opc opa opb opc Multiply MUL opa,opb,opc opa opb x opc Divide DIV opa,opb,opc opa opb / opc Negate NEG opa,opb opa - opb Some processors define operations conditioned to state bits. Example: ADD.NZ opa,opb,opc ; se S(Z)=0 opa opb + opc ; se S(Z)=1 NOP

20 Status register 20 The status register stores information regarding the previously executed instructions Example: STATUS REGISTER: Previous result gave an overflow Previous result had carry out Previous result was negative Previous result was zero Not all instructions change the status register, e.g., logic instructions do not update the overflow bit

21 Instruction Set Architecture (ISA) Example logic operations 21 Description Assembly Operation Clear CLR opa opa 0 Complement NOT opa,opb opa! opb And AND opa,opb opa opa opb Or OR opa,opb opa opa opb Exclusive-or XOR opa,opb opa opa opb Clear Carry CLC S(C) 0 Set Carry STC S(C) 1 Complement Carry CMC S(C)! S(C)

22 Instruction Set Architecture (ISA) Example shift operations 22 Description Assembly Operation Logic shift left (LSL) SHL opa opa LSL opa Logic shift right (LSR) SHR opa opa LSR opb Arithmetic shift left (ASL) SHLA opa opa ASL opa Arithmetic shift right (ASR) SHRA opa opa ASR opb Rotate left (ROL) ROL opa opa ROL opa Rotate Right (ROR) ROR opa opa ROR opb Rotate left with Carry (ROLC) ROLC opa opa ROLC opa Rotate Right with Carry (RORC) RORC opa opa RORC opb

23 Instruction Set Architecture (ISA) Example control operations 23 Description Assembly Operation Branch BR.cond opa Relative jump (PC PC + OpA) Jump JMP.cond opa Absolute jump (PC OpA) Test & Branch TB.cond... Test and relative jump Test & Jump TJ.cond... Test and absolute jump Skip next instruction SKP.cond... Skip instruction Jump and Link JMPL.cond opa Function call in RISC processors Call procedure CALL.cond opa Function call in CISC processors Return RET.cond Return from function call (CISC) Test instruction to be used before a condicional Jump or Branch instruction Compare (Escrita dos bits de estado) Test (Escrita dos bits de estado) CMP opa,opb TEST opa,opb Operand compare through subtraction (updates status register bits Z,N,C,V) Operand compare through logic AND (updates status register bit Z) All control instructions can be conditional or inconditional; some processors also implement conditional data insctructions.

24 Instruction Set Architecture (ISA) Example status-based conditions 24 Description Assembly Example If zero, S(Z)=1.Z ADD.Z If not zero, S(Z)=0.NZ BR.NZ If Negative, S(N)=1.N BR.Z If not Negative, S(N)=0.NN JMP.NZ If Carry, S(C)=1.C CALL.C If not Carry, S(C)=0.NC CALL.NC If Overflow, S(V)=1.V RET.V If not Overflow, S(V)=0.NV SKP.NV

25 Instruction Set Architecture (ISA) Example test conditions 25 Description Assembly Condition If higher.h opa > opb If higher or equal.he opa opb If Lower.L opa < opb If Lower or equal.le opa opb If equal.e opa = opb If not equal.ne opa opb CONDITIONS FOR SIGNED NUMBERS Description Assembly Condition If greater.g opa > opb If greater or equal.ge opa opb If Less.L opa < opb If Less or equal.le opa opb

26 26 Next lesson Hardware implementation of a RISC processor MIPS ISA Designing a simple MIPS-like processor