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1 pm3 12 Specifications Part 1 Embedded System Design Kluwer Academic Publisher by Peter Marwedel TU Dortmund 2008/11/15 ine Marwedel, 2003 Graphics: Alexandra Nolte, Ges Introduction 12,

2 Specification of embedded systems: Requirements for specification techniques (1) Hierarchy Humans not capable to understand systems containing more than ~5 objects. Most actual systems require more objects Hierarchy Behavioral hierarchy proc proc Examples: states, processes, procedures. proc Structural hierarchy Examples: processors, racks, printed circuit boards Compositional behavior Must be easy to derive behavior from behavior of subsystems Concurrency, Synchronization and communication 12, Requirements for specification techniques (2) Timing Timing behavior: timing requirements must be captured into specifications Essential for connecting to physical environment Additional information (periods, dependences, scenarios, use cases) welcome Also, the speed of the underlying platform must be known Four types of timing specs required, according to [Burns 1990]: 1. Measure elapsed time Check, how much time has elapsed since last call? execute t 12,

3 Requirements for specification techniques (3) Timing (2) 2. Means for delaying processes t 3. Possibility to specify timeouts Stay in a certain state a maximum time. 4. Methods for specifying deadlines Not available or in separate control file. execute t 12, Requirements for specification techniques (4): Support for designing reactive systems State-oriented behavior Required for reactive systems; classical automata insufficient to model timing and hierarchy Event-handling (external events or internal events) Exception-oriented oriented behavior Not acceptable to describe exceptions for every state We will see, how all the arrows labeled k can be replaced by a single one. 12,

4 Requirements for specification techniques (5): Support for designing reactive systems Support for the design of dependable systems Unambiguous semantics capable to describe in a formal way non-functional requirements such as fault tolerance, disposability, EMC properties, weight, size, user friendliness, extendibility, expected life time, power consumption Concurrency real life systems are intrinsically concurrent Synchronization and communication Components have to communicate! Presence of programming elements Such as loops and function calls should be available Executability (no algebraic specification) to verify the system at the early stages of the design 12, Requirements for specification techniques (6) Support for the design of large systems ( OO) Domain-specific support Readability Portability on several HW platforms Flexibility Small changes of the system features should require small changes to the specifications Termination It should be clear at which time all computations are completed Support for non-standard I/O devices direct access to switches, displays, etc. Adequate model of computation 12,

5 Models of computation - Definition - What does it mean, to compute? Models of computation define: Components and an execution model for computations for each component Communication model for exchange of information between components. Shared memory Message passing C-1 C-2 12, Components (1) Von Neumann model of sequential computing Sequential execution, program memory etc. Discrete event model: ordered sequence of events a 56 b 7 c 8 queue a:=5 b:=7 c:=8 a:=6 a:=9 time action 12,

6 Components (2) Finite state machines Differential equations 2 x = b 2 t 12, Communication Shared memory Variables accessible to several tasks. Suitable for local (non-distributed) systems Comp-1 Memory Comp-2 Message passing Transmission of messages over channels Suitable for distributed systems Asynchronous message passing Synchronous message passing 12,

7 Shared memory Potential race conditions ( inconsistent results possible) Critical sections = sections at which exclusive access to resource r (e.g. shared memory) must be guaranteed. process a {.. P(S) //obtain lock process b {.. P(S) //obtain lock.. // critical section.. // critical section V(S) //release lock V(S) //release lock } } Race-free access to shared memory protected by S possible This model may be supported by: mutual exclusion for critical sections cache coherency protocols 12, Non-blocking/Asynchronous message passing Processes communicate by sending messages through channels that can buffer the messages Sender does not have to wait until message has arrived Potential problem: buffer overflow send () receive () 12,

8 Blocking/Synchronous message passing rendez-vous Processes communicate in atomic actions called rendez-vous Sender will wait until receiver has received message send () receive () 12, Extended rendez-vous Explicit acknowledge from receiver required. Receiver can do checking before sending acknowledgement. send () receive () ack 12,

9 Facing reality No single language that meets all language requirements using compromises The choice of specification language/formalism depends on the application domain language/formalism established by specific application domain Need of unified system-level model composition format 12, Ptolemy Ptolemy (UC Berkeley) is an environment for simulating multiple models of computation. 12, 2008 Ptolemy simulations

10 Models of computation Communication/ Computations Shared memory Message passing Synchronous Asynchronous Communicating StateCharts SDL Finite State Machines Data flow model Computational graphs Not useful Simulink Kahn process networks SDF Sequence diagram Petri nets Von Neumann model C, C++, Java C, C++, Java with libraries CSP, ADA Discrete event (DE) model VHDL, Verilog Only experimental systems, e.g. distributed DE in Ptolemy 12, StateCharts 12,

11 StateCharts Used here as a (prominent) example of a model of computation based on shared memory communication. appropriate only for local (nondistributed) systems 12, StateCharts: recap of classical automata (FSMs) Classical automata (Finite State Machines) input X Internal state t Z output t Y clock Next state Z + computed by function δ Output computed by function λ Moore- + Mealy automata=finite state machines (FSMs) Moore-automata: Y = λ (Z); Z + = δ (X, Z) Mealy-automata Y = λ (X, Z); Z + = δ (X, Z) Z0 e=1 Z1 0 1 e=1 e=1 Z3 Z2 3 e=1 2 12,

12 StateCharts Classical automata not useful for complex systems (complex graphs cannot be understood by humans). Introduction of hierarchy StateCharts [Harel, 1987] StateChart = the only unused combination of flow or state with diagram or chart 12, StateCharts Used for modeling state-oriented behavior To describe extended FSMs Processes described as state machines The key extension is HIERARCHY introduced by means of the concept of super-states StateCharts = Hierarchical FSMs + Concurrency + Actions 12,

13 Introducing hierarchy FSM will be in exactly one of the substates of S if S is active (either in A or in B or..) Suitable for compact representation of exceptions (such as k) 12, Definitions Current states of FSMs are also called active states. States which are not composed of other states are called basic states. States containing other states are called super-states. For each basic state si, the super-state S containing si is called ancestor state. Super-states S are called OR-super-states, if exactly one of the sub-states of S is active whenever S is active. superstate ancestor state of E substates 12,

14 Default state mechanism Try to hide internal structure from outside world! Default state Filled circle indicates sub-state entered whenever super-state is entered. Not a state by itself! 12, History mechanism km (behavior different from last slide) For input m, S enters the state it was in before S was left (can be A, B, C, D, or E). If S is entered for the first time, the default mechanism applies. History and default mechanisms can be used hierarchically. 12,

15 Combining history and default state mechanism same meaning 12, Concurrency Convenient ways of describing concurrency are required. AND-super-states: FSM is in all (immediate) sub-states of a super-state; Example: 12,

16 Types of states In StateCharts, states are either basic states, or AND-super-states, or OR-super-states. 12, Timers Since time needs to be modeled in embedded systems, timers need to be modeled. In StateCharts, special edges can be used for timeouts. If event a does not happen while the system is in the left state for 20 ms, a timeout will take place. 12,

17 Example: using timers in an answering machine. 12, General form of edge labels event [condition] / reaction Events: Exist only until the next evaluation of the model Can be either internally or externally generated Conditions: Refer to values of variables that keep their value until they are reassigned Reactions: Can either be assignments for variables or creation of events Example: service-off [not in Lproc] / service:=0 12,

18 The StateCharts simulation phases (StateMate Semantics) How are edge labels evaluated? Three phases: 1. Effect of external changes on events and conditions is evaluated, 2. The set of transitions to be made in the current step and right hand sides of assignments are computed, 3. Transitions become effective, variables obtain new values. Separation into phases 2 and 3 guarantees deterministic and reproducible behavior. 12, Example In phase 2, variables a and b are assigned to temporary variables (a :=b; b :=a). In phase 3, these are assigned to a and b (a:=a ; b:=b ). As a result, variables a and b are swapped. In a single phase environment, executing the left state first would assign the old value of b (=0) to a and b. Executing the right state first would assign the old value of a (=1) to a and b. The execution would be non-deterministic. 12,

19 Reflects model of clocked hardware In an actual clocked (synchronous) hardware system, both registers would be swapped as well. Same separation into phases found in other languages as well, especially those that are intended to model hardware. 12, Steps Execution of a StateMate model consists of a sequence of (status, step) pairs Status= values of all variables + set of events + current time Step = execution of the three phases (StateMate semantics) Status phase 2 Other implementations of StateCharts do not have these 3 phases (and hence are nondeterministic)! 12,

20 Broadcast mechanism Values of variables are visible to all parts of the StateChart model New values become effective in phase 3 of the current step and are obtained by all parts of the model in the following step.! StateCharts implicitly assumes a broadcast mechanism for variables ( implicit shared memory communication other implementations would be very inefficient -). StateCharts is appropriate for local control systems ( ), but not for modeling distributed applications for which updating variables might take some time ( ). 12, Evaluation of StateCharts (1) Pros: Hierarchy allows arbitrary nesting of AND- and OR-super states. Suitable for control-dominated systems. Large number of commercial simulation tools available (StateMate, StateFlow by MathWorks, BetterState,...) Available back-ends automatically translate StateCharts into equivalent descriptions in C or VHDL, thus enabling SW and/or HW implementations. 12,

21 Evaluation of StateCharts (2) Cons: Generated C programs frequently inefficient, Not useful for distributed applications, No program constructs, No description of non-functional behavior, No object-orientation, No description of structural hierarchy. Extensions: Module charts for description of structural hierarchy C-code used to represent program constructs 12, Synchronous vs. asynchronous languages (2) Synchronous models of computation implicitly assume the presence of a (global) clock. Each clock tick, all inputs are considered, new outputs and states are calculated and then the transitions are made. This requires a broadcast mechanism for all parts of the model 12,

22 Abstraction of delays Let f(x): some function computed from input x, (f(x)): the delay for this computation δ: some abstraction of the real delay (e.g. a safe upper bound) Consider compositionality: f(x)=g(h(x)) Then, the sum of the delays of g and h would be a safe upper bound on the delay of f. Two solutions: 1. δ =0, always synchrony 2. δ =? (hopefully bounded) asynchrony Based p. on marwedel, slide 15 of N. Halbwachs: Synchronous Programming of Reactive Systems, ARTIST2 12, Summer 2008 School on Embedded Systems, Florianopolis, Compositionality At the abstract level, a single FSM reacts immediately At the abstract level, reaction of connected other automata is immediate Based on slide 16 of N. Halbwachs: Synchronous Programming of Reactive Systems, ARTIST2 Summer School on Embedded Systems, Florianopolis, ,

23 Concrete Behavior The abstraction of synchronous languages is valid, as long as real delays are always shorter than the clock period. Reference: slide 17 of N. Halbwachs: Synchronous Programming of Reactive Systems, ARTIST2 Summer School on Embedded Systems, Florianopolis, , Synchronous languages The synchronous semantic requires a broadcast mechanism for all parts of the model. Idealistic view of concurrency. Have the advantage of guaranteeing deterministic behavior. StateCharts (using StateMate semantics) is an almost synchronous language [Halbwachs]. Immediate communication is the lacking feature which would make StateCharts a fully synchronous language. 12,

24 Synchronous languages: several implementation and specification models For synchronous languages, the implementation model is that of finite state machines (FSMs). The specification may use different notational styles Imperative : Esterel (textual) SyncCharts: graphical version of Esterel Data-flow : Lustre (textual) SCADE (graphical) is a mix containing elements from multiple styles Nevertheless, specifications always include a close link to the generated FSMs (i.e., imperative does not have semantics close to von-neumann languages) 12, Applications SCADE Suite, including the SCADE KCG Qualified Code Generator, is used by AIRBUS and many of its main suppliers for the development of most of the A380 and A400M critical on board software, and for the A /600 Secondary Flying Command System, aircraft in operational use since August François Pilarski, Systems Engineering Framework - Senior Manager Engineering,Systems & Integration Tests; Airbus France. Instance of model-based design Source: 12,

25 Summary on StateCharts StateCharts as an example of Communicating FSM based on shared memory communication AND-states OR-states Timer Broadcast Semantics multi-phase models single-phase models Synchronous languages Based on clocked finite state machine view Based on 0-delay (valid as long as real delays are small enough) 12, Models of computation Communication/ Computations Shared memory Message passing Synchronous Asynchronous Communicating StateCharts SDL Finite State Machines Data flow model Computational graphs Not useful Simulink Kahn process networks SDF Sequence diagram Petri nets Von Neumann model C, C++, Java C, C++, Java with libraries CSP, ADA Discrete event (DE) model VHDL, Verilog Only experimental systems, e.g. distributed DE in Ptolemy 12,

26 SDL 12, SDL Used here as a (prominent) example of a Communicating FSM model of computation based on asynchronous message passing communication. appropriate also for distributed systems 12,

27 SDL Language designed for specification of distributed systems. Dates back to early 70s, Formal semantics defined in the late 80s, Defined by ITU (International Telecommunication Union): Z.100 recommendation in 1980 Updates in 1984, 1988, 1992, 1996 and 1999 See also 12, SDL Provides textual and graphical formats Just like StateCharts, it is based on the Communicating FSM model of computation; each FSM is called a process, However, it uses asynchronous message passing communication instead of shared memory for communications, SDL supports operations on data. 12,

28 A process in SDL is an extended FSM, that can use and manipulate data stored in local variables SDL-representation of FSMs state input output 12, Operations on data Variables can be declared locally for processes. Their type can be predefined or defined in SDL itself. SDL supports abstract data types (ADTs). Examples: Sequential statements and/or variables assignments locally into a process 12,

29 Communication among SDL-FSMs Communication between FSMs (or processes ) is based on message-passing, assuming a potentially indefinitely large FIFO-queue. Each process fetches next entry from FIFO, checks if input enables transition, if yes: transition takes place, if no: input is ignored (exception: SAVEmechanism). Concurrent FSMs (processes) 12, Deterministic? Let tokens be arriving at FIFO at the same time: Order in which they are stored, is unknown: All orders are legal: simulators can show different behaviors for the same input, all of which are correct. 12,

30 Basic system structure A system definition is structured into a hierarchy of block definitions and process definitions The root block is called system. A system contains one or more blocks interconnected with each other and with the boundary by channels 12, Hierarchy in SDL A block can be partitioned into (sub)blocks interconnected with channels Repeated block partitioning results in a block tree structure (with the system as a root block) A block can contains processes interconnected by signals Processes cannot contain other processes, unlike in StateCharts 12,

31 Hierarchy in SDL: an example 12, Process interaction diagrams Interaction between processes can be described in process interaction diagrams (block diagrams). In addition to processes, these diagrams contain channels and declarations of local signals. Example: B, 12,

32 Timers Timers can be declared locally. Elapsed timers put signal into queue (not necessarily processed immediately). RESET removes timer (also from FIFO-queue). 12, Additional language elements SDL includes a number of additional language elements, like procedures creation and termination of processes advanced description of data More features added for SDL-2000 (not well accepted) 12,

33 Evaluation Suitable for distributed applications (used for ISDN), Commercial tools available from SINTEF, Telelogic, Cinderella (// dk) Not necessarily deterministic (order, in which FSMs are reading input is unknown) no synchronous language, Implementation requires bound for the maximum length of FIFOs; may be very difficult to compute, Timer concept adequate just for soft deadlines, Limited way of using hierarchies, Limited programming language support, No description of non-functional properties, Becoming less popular 12, Summary SDL Model of Computation: finite state machine components + non-blocking message passing communication Representation of processes Communication & block diagrams Timers and other language elements Example: Vending machine Evaluation 12,

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