ECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions

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1 ECE332, Week 8 October 15, Topics Exceptions Hardware Interrupts Software exceptions Unimplemented instructions Software traps Other exceptions 2 1

2 Exception An exception is a transfer of control away from a program s normal flow of execution Caused by an event, either internal or external to the processor Requires immediate attention 3 Reference Textbook Section 6.4 Nios II Software Developer s Handbook Chapter 7 - Exception Handling Nios II Processor Reference Handbook Page 2-6 to 2-7, and Page 3-5 to 3-10 Quartus II Version 7.1 Handbook Volume 5: Embedded Peripherals Chapters 7, 8, 13, and

$typedef unsigned int REGISTER; struct PIO_REGS { REGISTER data; // data read/write REGISTER direction; // set port direction REGISTER interruptmask; // enable/disable$

3 Review: Questions on this? typedef unsigned int REGISTER; struct PIO_REGS { REGISTER data; // data read/write REGISTER direction; // set port direction REGISTER interruptmask; // enable/disable interrupt REGISTER edgecapture; // edge detection }; struct PIO_REGS *KEY1 = (struct PIO_REGS *) (BUTTON1_BASE 0x ); 5 Hardware Interrupt 6 3

4 Polling versus Interrupt Context: Processor and peripheral Polling Interleave the processor s other tasks with a routine that checks for new data in the peripheral This repeated checking by processor is called polling Pro: simple to implement Con: repeated checking wastes clock cycles Interrupt Hardware support Interrupt pin (int) During normal instruction execution, the processor check whether int has been asserted The checking doesn t incur any overhead, as this is done in hardware If int has been asserted, interrupt services routine (ISR) will7 take over the servicing Is Interrupt a free lunch? Not exactly, there is still overhead involve There are three key metrics Interrupt latency The time from when an interrupt is first generated to when the processor runs the first instruction at the exception address Interrupt response time The time from when an interrupt is first generated to when the processor runs the first instruction in the ISR. Interrupt recovery time The time taken from the last instruction in the ISR to return to normal processing Basically, the amount of time spent servicing the interrupt 8 4

5 Interrupt One type of exception The goal of microprocessor is interfacing and controlling peripherals This means that these peripherals requires servicing If peripheral produces data in predictable interval, polling will work just fine What about unpredictable interval? How to avoid the processor busy for nothing? i.e. check whether data is available Goal: Keep the processor doing useful work Peripheral interrupts the processor when service is required 9 Interrupt Different processors have different methods to determine where the ISR resides (address). Basically, there are two methods: Fixed interrupt Vectored interrupt Fixed interrupt Address built into microprocessor, cannot be changed Either ISR stored at address or a jump to actual ISR stored if not enough bytes available Vectored interrupt Peripheral must provide the address Common when microprocessor has multiple peripherals connected by a system bus Compromise: interrupt address table 10 5

6 Fixed ISR Address Time 1(a): µp is executing its main program. 1(b): P1 receives input data in a register with address 0x : After completing instruction at 100, µp sees Int asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of 16. 2: P1 asserts Int to request servicing by the microprocessor. 4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x (b): After being read, P1 deasserts Int. 5: The ISR returns, thus restoring PC to 100+1=101, where µp resumes executing. 11 Vectored ISR Address Time 1(a): µp is executing its main program. 1(b): P1 receives input data in a register with address 0x : After completing instruction at 100, µp sees Int asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of 16. 2: P1 asserts Int to request servicing by the microprocessor. 4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x (b): After being read, P1 deasserts Int. 5: The ISR returns, thus restoring PC to 100+1=101, where µp resumes executing. 12 6

7 Interrupt Address Table Compromise between fixed and vectored interrupts One interrupt pin Table in memory holding ISR addresses (maybe 256 words) Peripheral doesn t provide ISR address, but rather index into table Fewer bits are sent by the peripheral Can move ISR location without changing peripheral 13 Additional Interrupt Issues Maskable vs. non-maskable interrupts Maskable: programmer can set bit that causes processor to ignore interrupt Important when in the middle of time-critical code Non-maskable: a separate interrupt pin that can t be masked Typically reserved for drastic situations, like power failure requiring immediate backup of data to non-volatile memory Jump to ISR Some microprocessors treat jump same as call of any subroutine Complete state saved (PC, registers) may take hundreds of cycles Others only save partial state, like PC only Thus, ISR must not modify registers, or else must save them first Assembly-language programmer must be aware of which 14 registers stored 7

An overview of Interrupts ECE3534

An overview of Interrupts ECE3534 An overview of errupts ECE3534 Microprocessor erfacing: errupts Suppose a peripheral intermittently receives data, which must be serviced by the processor The processor can poll the peripheral regularly