CENG 3420 Lecture 05: Arithmetic and Logic Unit

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1 CENG 3420 Lecture 05: Arithmetic and Logic Unit Bei Yu CENG3420 L05.1 Spring 2017
2 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.2 Spring 2017
3 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.3 Spring 2017
4 Abstract Implementation View PC Address Instruction Memory Instruction Write Data Register Write Addr File Read Addr Read Addr Read Data Read Data ALU Address Data Memory Write Data Read Data CENG3420 L05.4 Spring 2017
5 Arithmetic q Where we've been Abstractions  Instruction Set Architecture (ISA)  Assembly and machine language q What's up ahead Implementing the ALU architecture zero ovf A ALU 32 result B 32 4 m (operation) CENG3420 L05.5 Spring 2017
6 Review: VHDL q Supports design, documentation, simulation & verification, and synthesis of hardware q Allows integrated design at behavioral & structural levels CENG3420 L05.6 Spring 2017
7 Review: VHDL q Basic structure Design entityarchitecture descriptions Timebased execution (discrete event simulation) model Design EntityArchitecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure CENG3420 L05.7 Spring 2017
8 Review: EntityArchitecture Features q Entity defines externally visible characteristics Ports: channels of communication  signal names for inputs, outputs, clocks, control Generic parameters: define class of components  timing characteristics, size (fanin), fanout q Architecture defines the internal behavior or structure of the circuit Declaration of internal signals Description of behavior  collection of Concurrent Signal Assignment (CSA) statements (indicated by <=); can also model temporal behavior with the delay annotation  one or more processes containing CSAs and (sequential) variable assignment statements (indicated by :=) Description of structure  interconnections of components; underlying behavioral models of each component must be specified CENG3420 L05.8 Spring 2017
9 ALU VHDL Representation entity ALU is port(a, B: in std_logic_vector (31 downto 0); m: in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero: out std_logic; ovf: out std_logic) end ALU; architecture process_behavior of ALU is... begin ALU: process(a, B, m) begin... result := A + B;... end process ALU; end process_behavior; CENG3420 L05.9 Spring 2017
10 Machine Number Representation q Bits are just bits (have no inherent meaning) conventions define the relationships between bits and numbers q Binary numbers (base 2)  integers > > > > > >... in decimal from 0 to 2 n 1 for n bits q Of course, it gets more complicated storage locations (e.g., register file words) are finite, so have to worry about overflow (i.e., when the number is too big to fit into 32 bits) have to be able to represent negative numbers, e.g., how do we specify 8 in addi $sp, $sp, 8 #$sp = $sp  8 in real systems have to provide for more than just integers, e.g., fractions and real numbers (and floating point) and alphanumeric (characters) CENG3420 L05.10 Spring 2017
11 MIPS Representations q 32bit signed numbers (2 s complement): two = 0 ten two = + 1 ten two = + 2 ten... maxint two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = 2,147,483,648 ten two = 2,147,483,647 ten two = 2,147,483,646 ten... minint two = 3 ten two = 2 ten two = 1 ten q What if the bit string represented addresses? need operations that also deal with only positive (unsigned) integers CENG3420 L05.11 Spring 2017
12 Two's Complement Operations q Negating a two's complement number complement all the bits and then add a 1 remember: negate and invert are quite different! q Converting nbit numbers into numbers with more than n bits: MIPS 16bit immediate gets converted to 32 bits for arithmetic sign extend  copy the most significant bit (the sign bit) into the other bits > > sign extension versus zero extend (lb vs. lbu) CENG3420 L05.12 Spring 2017
13 Design the MIPS Arithmetic Logic Unit (ALU) q Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 ALU m (operation) result q With special handling for sign extend addi, addiu, slti, sltiu zero extend andi, ori, xori Overflow detected add, addi, sub CENG3420 L05.13 Spring 2017
14 MIPS Arithmetic and Logic Instructions Rtype: op Rs Rt Rd funct IType: op Rs Rt Immed 16 Type op funct ADDI xx ADDIU xx SLTI xx SLTIU xx ANDI xx ORI xx XORI xx LUI xx Type op funct ADD ADDU SUB SUBU AND OR XOR NOR Type op funct SLT SLTU CENG3420 L05.14 Spring 2017
15 Design Trick: Divide & Conquer q Break the problem into simpler problems, solve them and glue together the solution q Example: assume the immediates have been taken care of before the ALU A B now down to 10 operations can encode in 4 bits zero ovf 1 ALU m (operation) result 0 add 1 addu 2 sub 3 subu 4 and 5 or 6 xor 7 nor CENG3420 L05.15 Spring 2017 a b slt sltu
16 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.16 Spring 2017
17 Addition & Subtraction q Just like in grade school (carry/borrow 1s) q Two's complement operations are easy do subtraction by negating and then adding > > q Overflow (result too large for finite computer word) e.g., adding two nbit numbers does not yield an nbit number CENG3420 L05.17 Spring 2017
18 Building a 1bit Binary Adder carry_in A B carry_in carry_out S A B 1 bit Full Adder S carry_out S = A xor B xor carry_in carry_out = A&B A&carry_in B&carry_in (majority function) q How can we use it to build a 32bit adder? q How can we modify it easily to build an adder/subtractor? CENG3420 L05.18 Spring 2017
19 Building 32bit Adder c 0 =carry_in A 0 1bit B FA S 0 0 c 1 A 1 1bit B FA S 1 1 c 2 A 2 1bit FA S B 2 2 c 3... c 31 A 31 1bit B FA S c 32 =carry_out q Just connect the carryout of the least significant bit FA to the carryin of the next least significant bit and connect... q Ripple Carry Adder (RCA) l advantage: simple logic, so small (low cost) l disadvantage: slow and lots of glitching (so lots of energy consumption) CENG3420 L05.19 Spring 2017
20 Glitch q Glitch: invalid and unpredicted output that can be read by the next stage and result in a wrong action q Example: Draw the propagation delay CENG3420 L05.20 Spring 2017
21 Glitch in RCA c 0 =carry_in A 0 1bit B FA S 0 0 c 1 A 1 1bit B FA S 1 1 c 2 A 2 1bit FA S B 2 2 c 3 A B carry_in carry_out S c 31 A 31 1bit FA S B c 32 =carry_out CENG3420 L05.21 Spring 2017
22 But What about Performance? q Critical path of nbit ripplecarry adder is n*cp A0 B0 A1 B1 A2 B2 A3 B3 CarryIn0 1bit Result0 ALU CarryOut0 CarryIn1 1bit Result1 ALU CarryOut1 CarryIn2 1bit Result2 ALU CarryOut2 CarryIn3 1bit ALU Result3 CarryOut3 q Design trick throw hardware at it (Carry Lookahead) CENG3420 L05.22 Spring 2017
23 A 32bit Ripple Carry Adder/Subtractor q Remember 2 s complement is just l complement all the bits add/sub B 0 A 0 c 0 =carry_in 1bit FA S 0 c 1 control (0=add,1=sub) B 0 if control = 0!B 0 if control = 1 B 0 B 1 A 1 1bit FA S 1 c 2 l add a 1 in the least significant bit B 2 A 2 1bit FA S 2 c 3 A > 0111 B > B 31 A c 31 1bit FA S 31 c 32 =carry_out CENG3420 L05.23 Spring 2017
24 Minimal Implementation of a Full Adder q Gate library: inverters, 2input nands, orandinverters architecture concurrent_behavior of full_adder is begin signal t1, t2, t3, t4, t5: std_logic; t1 <= not A after 1 ns; t2 <= not cin after 1 ns; t4 <= not((a or cin) and B) after 2 ns; t3 <= not((t1 or t2) and (A or cin)) after 2 ns; t5 <= t3 nand B after 2 ns; S <= not((b or t3) and t5) after 2 ns; cout <= not((t1 or t2) and t4) after 2 ns; end concurrent_behavior; q [Optional] Can you create the equivalent schematic? Can you determine worst case delay (the worst case timing path through the circuit)? CENG3420 L05.24 Spring 2017
25 Tailoring the ALU to the MIPS ISA q Also need to support the logic operations (and,nor,or,xor) Bit wise operations (no carry operation involved) Need a logic gate for each function and a mux to choose the output q Also need to support the setonlessthan instruction (slt) Uses subtraction to determine if (a b) < 0 (implies a < b) q Also need to support test for equality (bne, beq) Again use subtraction: (a  b) = 0 implies a = b q Also need to add overflow detection hardware overflow detection enabled only for add, addi, sub q Immediates are sign extended outside the ALU with wiring (i.e., no logic needed) CENG3420 L05.25 Spring 2017
26 A Simple ALU Cell with Logic Op Support add/subt carry_in op A result B 1bit FA add/subt carry_out CENG3420 L05.26 Spring 2017
27 Modifying the ALU Cell for slt add/subt carry_in op A result B less 1bit FA 6 7 add/subt carry_out CENG3420 L05.27 Spring 2017
28 Modifying the ALU for slt A 0 q First perform a subtraction q Make the result 1 if the subtraction yields a negative result B 0 A 1 less + result 0 q Make the result 0 if the subtraction yields a positive result l tie the most significant sum bit (sign bit) to the low order less input B 1 0 A 31 less +... result 1 result 31 0 set B + 31 CENG3420 L05.28 Spring 2017 less
29 Overflow Detection q Overflow occurs when the result is too large to represent in the number of bits allocated adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive gives a negative or, subtract a positive from a negative gives a positive q On your own: Prove you can detect overflow by: Carry into MSB xor Carry out of MSB CENG3420 L05.29 Spring 2017
30 add/subt A 0 B 0 less + op Modifying the ALU for Overflow result 0 q Modify the most significant cell to determine overflow output setting A 1 result 1 set B 1 0 A 31 less + result 31 + B 31 0 less zero q Enable overflow bit setting for signed arithmetic (add, addi, sub) overflow CENG3420 L05.30 Spring 2017
31 Overflow Detection and Effects q On overflow, an exception (interrupt) occurs Control jumps to predefined address for exception Interrupted address (address of instruction causing the overflow) is saved for possible resumption q Don't always want to detect (interrupt on) overflow CENG3420 L05.31 Spring 2017
32 New MIPS Instructions Category Instr Op Code Example Meaning Arithmetic (R & I format) Data Transfer Cond. Branch (I & R format) add unsigned 0 and 21 addu $s1, $s2, $s3 $s1 = $s2 + $s3 sub unsigned 0 and 23 subu $s1, $s2, $s3 $s1 = $s2  $s3 add imm.unsigned ld byte unsigned 9 addiu $s1, $s2, 6 $s1 = $s lbu $s1, 20($s2) $s1 = Mem($s2+20) ld half unsigned 25 lhu $s1, 20($s2) $s1 = Mem($s2+20) set on less than unsigned set on less than imm unsigned 0 and 2b sltu $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 b sltiu $s1, $s2, 6 if ($s2<6) $s1=1 q Sign extend addi, addiu, slti q Zero extend andi, ori, xori q Overflow detected add, addi, sub else $s1=0 CENG3420 L05.32 Spring 2017
33 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.33 Spring 2017
34 Multiplication q More complicated than addition Can be accomplished via shifting and adding 0010 (multiplicand) x_1011 (multiplier) (partial product 0000 array) (product) q Double precision product produced q More time and more area to compute CENG3420 L05.34 Spring 2017
35 First Version of Multiplication Hardware CENG3420 L05.35 Spring 2017
36 Add and Right Shift Multiplier Hardware multiplicand 32bit ALU product multiplier shift right add Control CENG3420 L05.36 Spring 2017
37 Add and Right Shift Multiplier Hardware = 6 multiplicand 32bit ALU product multiplier shift right = 5 add add add add = 30 add Control CENG3420 L05.37 Spring 2017
38 MIPS Multiply Instruction q Multiply (mult and multu) produces a double precision product mult $s0, $s1 # hi lo = $s0 * $s x18 Loworder word of the product is left in processor register lo and the highorder word is left in register hi Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file q Multiplies are usually done by fast, dedicated hardware and are much more complex (and slower) than adders CENG3420 L05.38 Spring 2017
39 Division q Division is just a bunch of quotient digit guesses and left shifts and subtracts divisor n n quotient dividend partial remainder array n remainder CENG3420 L05.39 Spring 2017
40 Example: Division q Dividing by 1000 CENG3420 L05.40 Spring 2017
41 MIPS Divide Instruction q Divide generates the reminder in hi and the quotient in lo div $s0, $s1 # lo = $s0 / $s1 # hi = $s0 mod $s1 op rs rt rd shamt funct Instructions mflo rd and mfhi rd are provided to move the quotient and reminder to (user accessible) registers in the register file q As with multiply, divide ignores overflow so software must determine if the quotient is too large. Software must also check the divisor to avoid division by 0. CENG3420 L05.41 Spring 2017
42 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.42 Spring 2017
43 Shift Operations q Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits op rs rt rd shamt funct q Notice that a 5bit shamt field is enough to shift a 32bit value or 31 bit positions q Logical shifts fill with zeros, arithmetic left shifts fill with the sign bit q The shift operation is implemented by hardware separate from the ALU using a barrel shifter (which would takes lots of gates in discrete logic, but is pretty easy to implement in VLSI) CENG3420 L05.43 Spring 2017
44 A Simple Shifter Right nop Left A i B i A i1 B i1 BitSlice i... CENG3420 L05.44 Spring 2017
45 Parallel Programmable Shifters Control = Shift amount (Sh 4 Sh 3 Sh 2 Sh 1 Sh 0 ) Shift direction (left, right) Shift type (logical, arithmetic) CENG3420 L05.45 Spring 2017
46 Logarithmic Shifter Structure Sh 0!Sh 0 Sh 1!Sh 1 Sh 2!Sh 2 Sh 3!Sh 3 Sh 4!Sh 4 Sh 01 & right shifts of 0 or 1 bits shifts of 0 or 2 bits shifts datain i+1 i+2 of 0!Sh 0 or datain 4 i bits datain i1 i2 shifts of 0 or 8 bits shifts of 0 dataout or 16 i bits Sh 01 & left 0,1 shifts 0,1,2,3 shifts 0,1,2,3,4, 5,6,7 shifts 0,1,2 15 shifts 0,1,2 31 shifts CENG3420 L05.46 Spring 2017
47 Logarithmic Shifter Structure Sh1 Sh1 Sh2 Sh2 Sh4 Sh4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 CENG3420 L05.47 Spring 2017
48 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number CENG3420 L05.48 Spring 2017
49 Floating Point Number q Scientific notation: A normalized number of certain accuracy e.g is called the mantissa Scale factors to determine the position of the decimal point e.g indicates position of decimal point and is called the exponent (the base is implied) Sign bit CENG3420 L05.49 Spring 2017
50 Normalized Form q Floating Point Numbers can have multiple forms, e.g x 10 4 = = 2.32 x x 10 2 = = x x 102 q It is desirable for each number to have a unique representation => Normalized Form q We normalize Mantissa's in the Range [ 1.. R ) where R is the Base, e.g.: [ ) for BINARY [ ) for DECIMAL CENG3420 L05.50 Spring 2017
51 IEEE Standard 754 Single Precision (32bit, float in C/ C++/ Java) 32 bits S E M Sign of number : 0 signifies + 1 signifies 8bit signed exponent in excess127 representation 23bit mantissa fraction Value represented = 1. M x 2 E 127 (a) Single precision à 40 Value represented = x = 87 (b) Example of a singleprecision number CENG3420 L05.51 Spring 2017
52 IEEE Standard 754 Double Precision (64bit, double in C/ C++/ Java) 64 bits S E M Sign 11bit excess1023 exponent 52bit mantissa fraction E 1023 Value represented = 1. M x 2 (c) Double precision CENG3420 L05.52 Spring 2017
53 Example q What is the IEEE single precision number 40C in decimal? Binary: Sign: + Exponent: = +2 Mantissa: à x 2 +2 à Decimal Answer = CENG3420 L05.53 Spring 2017
54 Class Exercise q What is in IEEE single precision binary floating point format? 0.5 = (in binary) Exponent bit= ( 1) = Sign bit = 1 Mantissa = binary representation = CENG3420 L05.54 Spring 2017
55 Ref: IEEE Standard 754 Numbers l Normalized +/ 1.d d x 2 exp l Denormalized +/ 0.d d x 2 min_exp à to represent nearzero numbers e.g x for Single Precision Format # bits # significant bits macheps # exponent bits exponent range Single (~107 ) (~10 38 ) Double (~1016 ) (~ ) Double Extended >=80 >=64 <=264 (~1019 ) >= (~ ) (Double Extended is 80 bits on all Intel machines) macheps = Machine Epsilon = = 2 (# significand bits) mach CENG3420 L05.55 Spring 2017
56 Other Features q +,, x, /, sqrt, remainder, as well as conversion to and from integer are correctly rounded As if computed with infinite precision and then rounded Transcendental functions (that cannot be computed in a finite number of steps e.g., sine, cosine, logarithmic, p, e, etc. ) may not be correctly rounded q Exceptions and Status Flags Invalid Operation, Overflow, Division by zero, Underflow, Inexact q Floating point numbers can be treated as "integer bitpatterns" for comparisons If Exponent is all zeroes, it represents a denormalized, very small and near (or equal to) zero number If Exponent is all ones, it represents a very large number and is considered infinity (see next slide.) CENG3420 L05.56 Spring 2017
57 Special Values q Exponents of all 0's and all 1's have special meaning E=0, M=0 represents 0 (sign bit still used so there is +/ 0) E=0, M<>0 is a denormalized number ±0.M x (smaller than the smallest normalized number) E=All 1's, M=0 represents ±Infinity, depending on Sign E=All 1's, M<>0 represents NaN CENG3420 L05.57 Spring 2017
58 Other Features q q q q Dual Zeroes: +0 (0x ) and 0 (0x ) (they are treated as the same) Infinity is like the mathematical one Finite / Infinity à 0 Infinity x Infinity à Infinity Nonzero / 0 à Infinity Infinity ^ (Finite or Infinity) à Infinity NaN (NotaNumber) is produced whenever a limiting value cannot be determined: Infinity Infinity à NaN Infinity / Infinity à NaN 0 / 0 à NaN Infinity x 0 à NaN Many systems just store the result quietly as a NaN (all 1's in exponent) some systems will signal or raise an exception If x is a NaN, x!= x CENG3420 L05.58 Spring 2017
59 Inaccurate Floating Point Operations q E.g. Find 1 st root of a quadratic equation r = ( b + sqrt(b*b 4*a*c)) / (2*a) Sparc processor, Solaris, gcc 3.3 (ANSI C), Expected Answer double float q Problem is that if c is near zero, sqrt(b*b 4*a*c)» b q Rule of thumb: use the highest precision which does not give up too much speed CENG3420 L05.59 Spring 2017
60 Catastrophic Cancellation l (a b) is inaccurate when a» b l Decimal Examples Using 2 significant digits to compute mean of 5.1 and 5.2 using the formula (a+b) / 2: a + b = 10 (with 2 sig. digits, 10.3 can only be stored as 10) 10 / 2 = 5.0 (the computed mean is less than both numbers!!!) Using 8 significant digits to compute sum of three numbers: ( ( ) ) = ( ( ) ) = l Catastrophic cancellation occurs when CENG3420 L05.60 Spring 2017
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