CS222: MIPS Instruction Set

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1 CS222: MIPS Instruction Set Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1

2 Outline Previous Introduction to MIPS Instruction Set MIPS Arithmetic's Register Vs Memory, Registers Name Byte Ordering Instruction types and format Control instructions Constant t in MIPS ISA MIPS ALP

3 Example: Instruction Set Architecture MIPS Representative of architectures developed since the 1980's Used by NEC, Nintendo, Silicon Graphics, Sony Real architecture but easy to understand MIPS: Microprocessor without Interlocked p Pipeline Stages : ISA MIPS: Millions Instructions Per Sec: Measure

4 MIPS Arithmetic All instructions have 3 operands Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add $s0, $s1, $s2 (associated with variables by compiler)

5 MIPS Arithmetic Simplicity favors regularity Operands must be registers, only 32 registers provided (smaller is faster) Expressions need to be broken C code MIPS code A = B + C + D; add $t0, $s1, $s2 E = F A; add $s0, $t0, $s3 sub $s4,,$ $s5,,$ $s0

6 Registers vs. Memory Scalars mapped to registers Structures, arrays etc in memory Control Input Datapath Memory Output Processor I/O

7 Memory Organization Viewed as a large, singledimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory bits of data bits of data 8 bits of data 3 8 bits of data bits of data 8 bits of data 6 8 bits of data

8 Register Names and Purpose Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s7 $ saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address R1: reserved for Architecture, R26 27:reserved for OS

9 Words and Bytes 2 32 bytes : byte addresses from 0 to words : byte addresses 0, 4, 8, Big endian byte order Little endian byte order d Non aligned word

10 Instructions to access memory Load and store instructions Example: C code: A[8] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3)

11 A simple example What does this code do? swap(int v[ ],int k){ int temp; temp = v[k] swap: v[k] = v[k+1]; muli $2, $5,4 v[k+1] = temp; add $2, $4,$2 } lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

12 Instruction Format R Type : instructions use opcode This group Contains all instructions that do not require an immediate value, target offset, memory addressdisplacement displacement, or memory address to specify an operand. Includes arithmetic and logic with all operands in registers, shift instructions, and register direct jump instructions (jalr and jr). I Type : Opcodes except , 00001x, and 0100xx This group includes instructions with an immediate operand, branch instructions, and load and store instructions. In the MIPS architecture, all memory accesses are handled by the main processor, so coprocessor load and store instructions are included in this group. J Type : instructions ti use opcode 00001x. This group consists of the two direct jump instructions (j and jal). These instructions ti require a memory address to specify their operand. 12

13 Machine Language Instructions are 32 bits long Registers have numbers , e.g., $t0=8, $t1=9,,$ $s0=16,,$ $s1=17 etc. Instruction Format: Example: add $t0, $s1, $s op rs rt rd shamt funct Shamt: Shift amount, funct: function

14 Machine Language lw / sw and the regularity principle? New principle: Good design demands a compromise new format (I type), other format was R Example: lw $t0, 32($s2) op rs rt 16 bit number Lw $dst imm($src) : $dst M [$src+imm] Refers from M location, it a type of Addressing

15 Control Intruction Decision making instructions alter the control flow MIPS conditional branch instructions: bne and beq Example: if (i == j) bne $s0, $s1, Label h = i + j; add $3$0$1 $s3, $s0, $s1 Label:...

16 Control Intruction MIPS unconditional branch instructions: j label Example: if (i!= j) beq $s4, $s5, Lab1 h = i + j; add $s3, $s4, $s5 else j Lab2 h = i j; Lab1: sub $s3, $s4, $s5 Lab2:...

17 Comparison less or greater slt: set if less than than slt $t0, $s1, $s2 if $s1 < $s2 then $t0 = 1 else $t0 = 0 Can use this instruction to build blt $s1 $s2 Can use this instruction to build blt $s1, $s2, Label, ble $s1, $s2, Label

18 Format of Instructions for Control beq, bne j I format op rs rt 16 bit number J format (new) op 26 bit number slt R format :set if less than op rs rt rd shamt funct

19 Constants Used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C 18; Solutions? data in memory, initialized at load time put constants within ihi instructionsi

20 Constants in MIPS instructions addi $29, $29, 4 i is for immediate slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 I Format is used op rs rt 16 bit number

21 A special constant 0 is a special constant, hard wired into register $0 (also called $zero) add $s2, $s4, $zero means move from $s4 to $s2

22 How about larger constants? To load a 32 bit constant into a register, we use two instructions one instruction fills this one instruction fills this

23 Loading larger constants new "load upper immediate" instruction lui $t0, then get the lower order bits right, ie i.e., ori $t0, $t0,

24 Summary of Instructions learnt Instructions Format add, sub, addi, subi R, I and, or, andi, ori R, I slt, slti R, I beq, bne I j J lw, sw I lui I

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