ADD R Operation : ACC = ACC + R SIZE : 1 byte, 8 bit Time : 3 T Cycle Work : Read R, Read ACC, Add, Write Result to ACC

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1 CISC to RISC and MIPS Instruction Set A. Sahu CSE, IIT Guwahati Please be updated with Outline Prev Class Understanding an existing architecture CISC : 8085 Example Analyze and Identify the difficulty or problem with CISC Works division of some 8085 instruction Listing of works done in executing instructions Simplifying instruction to make it RISC Simpler hardware : Data Path + Control Low power consumption MIPS ISA and Assembly Language Programming ACC 8085 Microprocessor Architecture tmp R Flag ALU Timing and Control Bus 8 Bit IR I Decode & M/C Encodin g MUX W Z B C D E H L SP PC Inc/Dec. ter Add latch Add Buff Data/Add Buff ADD R Operation : ACC = ACC + R Time : 3 T Cycle Work : Read R, Read ACC, Add, Write Result to ACC ADD M Operation : ACC = ACC + M[HL] Time : 7 T Cycle Work : Read H, Read L, Put HL to Add Buff, Read M, Put Buff to Temp A, Read ACC, Add, Write Result to ACC Operation : M[HL] = M[HL]+1 INC M Time : 10 T Cycle Work : Read H, Read L, Put HL to Add Buff, Read M, Put Buff to Temp A, Put 1 to TempB, Add, Write M 1

2 MVI A 34H Operation : ACC = ACC+37 SIZE : 2 byte 16 bit Time : 7 T Cycle Work : Read I from IR, Read ACC, Add, Write Result to ACC LDA A 2000H Operation : ACC = ACC+M[2000] SIZE : 3 byte, 24 bit Time : 13 T Cycle Work : Read NextPC, Put to Add Buff, Read Next PC, add to Add Buff, Read ACC, Add, Write Result to ACC PUSH D Operation : M[SP] = D, SP, M[SP]=E, SP Time : 12 T Cycle Work : Read dsph, Put to Add Buff, Read dspl, add to Add Buff, Read D, Put to Data Buff, Write to Mem, Read SP,Put Temp1 1, ALU Sub, Write to SP, Read SPH, Put to Add Buff, Read SPL, add to Add Buff, Read D, Put to Data Buff, Write to Mem, Read SP,Put Temp1 1, ALU Sub, Write to SP JMP 5000H Operation : PC = 5000 SIZE : 3 byte, 24 bit Time : 12 T Cycle Work : Read NextPC, Put to PCH, Read Next PC, Put to PCL Comparison Table INS Size Work TCycle ADD R 1 Byte A=A+R 3 ADD M 1 Byte A = A+M[HL] 7 INC M 1 Byte M[HL]=M[HL]+1 10 MVI A 34H 2 Byte A=34 7 LDA 2000H 3 Byte A=M[2000] 13 PUSHD 1 Byte M[SP ]=D,M[SP ]=E 12 JMP 5000H 3 Byte PC= Instruction Set Design 2

3 Instruction Set Design Keep all the instruction simple Number of work is upto 1 to 4 Size of instruction are almost same Load store are separated from arithmetic INS, no combination of load and store No complex instruction Controller and Data path simpler Instructions are: mixed of complex and simple instruction Number of work is upto 1 to 20 CISC Instruction Set How many different types instruction Example RISC : Around 80 CISC : Around 3000 OISC : 1 ASIP : 100, N/W processor, DSP OISC RISC ASIP CISC X86 Instruction Set Size Cost of Hardware, Power, Area Design time (of Hardware) Code Size (CISC smaller, OISC bigger) Compile time CISC : Huge, may not take advantage of all the hardware Execution time (Performance) Instructions Language of the Machine Primitive compared to HLLs Easily interpreted by hardware Instruction set design goals Maximize performance Minimize cost, Reduce design time Type of Instructions Instructions for arithmetic Instructions to move data Instructions for decision i making Handling constant operands Example: Instruction Set Architecture MIPS Representative of architectures developed since the 1980's Used by NEC, Nintendo, Silicon Graphics, Sony Real architecture but easy to understand MIPS: Microprocessor without Interlocked Pipeline Stages : ISA MIPS: Millions Instructions Per Sec: Measure 3

4 MIPS Arithmetic All instructions have 3 operands Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add $s0, $s1, $s2 (associated with variables by compiler) A mapped to $s0, B mapped to $s1 and C mapped to $s2 MIPS Arithmetic Simplicity favors regularity Operands must be registers, only 32 registers provided (smaller is faster) Expressions need to be broken C code MIPS code A = B + C + D; add $t0, $s1, $s2 E = F A; add $s0, $t0, $s3 sub $s4, $s5, $s0 A mapped to $s0, B mapped to $s1, C mapped to $s2 D mapped to $s3, E mapped to $s4, F mapped to $s5 Registers vs. Memory Scalars mapped to registers Structures, arrays etc in memory Control Datapath Processor Memory Input Output I/O Memory Organization Viewed as a large, singledimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory Register Names and Purpose Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address Words and Bytes 2 32 bytes : byte addresses from 0 to words : byte addresses 0, 4, 8, Big endian bt byte order Little endian byte order Non aligned word

5 Instructions to access memory Load and store instructions Example: C code: A[8] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) &A mapped to $s3 and h mapped to $s2 5

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