A Guide. DSP Library

Transcription

1 DSP A Guide To The DSP Library

2 SystemView by ELANIX Copyright , Eagleware Corporation All rights reserved. Eagleware-Elanix Corporation 3585 Engineering Drive, Suite 150 Norcross, GA USA Phone: +1 (678) , Fax: +1 (678) Support Web: Unpublished work. All rights reserved under the U.S. Copyright Act. Restricted Rights Apply. This document may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without the prior written consent of Eagleware Corporation. This document and the associated software are proprietary to Eagleware Corporation. SystemView by ELANIX, and ELANIX are registered trademarks of Eagleware Corporation. MetaSystem is a trademark of Eagleware Corporation. Windows is a trademark of Microsoft Corporation. Other trademarks or registered trademarks used in this document are the property of their respective owners. Document Number SVU-DSP0902 Printed in the United States of America 2

3 DSP Table of Contents Introduction... 7 General Information... 9 Tokens Listed by Group Arithmetic Models Token Name: Abbreviation: Adder... Adder Adder (2 Port)... Adder Constant Multiply... Cnst Mltply Divider... Divide Multiplier... Multiplier Multiplier (2 Port)... Multiplier Negate... Negate Reciprocal... Reciprcl Subtract... Subtract Bit Logic Models Token Name: Abbreviation: Bit Extract... Xtract Bits Bit To Symbol... Bit->Sym Bitwise AND... AND Bitwise Exclusive OR... XOR Bitwise NOT... NOT Bitwise OR... OR Reverse... Reverse Rotate... Rotate Shift... Shift Symbol To Bit... Sym->Bit Input/Output Models Token Name: Abbreviation: Converter... Converter FIFO Buffer... Buffer Lookup Table... Lookup

4 Signal Processing Models Token Name: Abbreviation: Comb Filter... Comb Fltr...27 Convolution... Convolve...36 Cross Correlator... XCorr...37 Detrend... Detrend...38 Discrete Cosine Transform... DCT...39 Discrete Hadamard Transform... DHT...40 Discrete Sine Transform... DST...42 Fourier Transform... FFT Cx...52 Interpolator... Interpolate...57 Real Input Fourier Transform... FFT Real...77 Operators Token Name: Abbreviation: Integrate and Dump... Integrate...54 Multiply Accumulate... M/Acc...69 Sine Cosine Table Lookup... Sin Cos...87 Square Root... Sqr Root...89 Operator/Linear System Models (SystemView token) Token Name: Abbreviation: Bit True DSP Filter... Filter

5 DSP Tokens Listed Alphabetically Token Name... Abbreviation...Group... Page Adder... Adder...Arithmetic...14 Adder (2 Port)... Adder 2...Arithmetic...17 Bit Extract... Xtract Bits...Bit Logic...22 Bit To Symbol... Bit->Sym...Bit Logic...25 Bitwise AND... AND...Bit Logic...20 Bitwise NOT... NOT...Bit Logic...73 Bitwise OR... OR...Bit Logic...75 Bitwise Exclusive OR... XOR...Bit Logic...95 Comb Filter... Comb Fltr...Signal Processing...27 Constant Multiply... Cnst Mltply...Arithmetic...30 Converter... Converter...Input/Output...33 Convolution... Convolv...Signal Processing...36 Cross Correlator... XCorr...Signal Processing...37 Detrend... Detrend...Signal Processing...38 Discrete Cosine Transform... DCT...Signal Processing...39 Discrete Hadamard Transform... DHT...Signal Processing...40 Discrete Sine Transform... DST...Signal Processing...42 Divider... Divide...Arithmetic...43 FIFO Buffer... Buffer...Input/Output...45 Bit True DSP Filter... Filter...Operator/Linear System...47 Fourier Transform... FFT Cx...Signal Processing...52 Integrate and Dump... Integrate...Operators...54 Interpolator... Interpolate...Signal Processing...57 Lookup Table... Lookup...Input/Output...61 Multiplier... Multiplier...Arithmetic...63 Multiplier (2 Port)... Multiplier 2...Arithmetic...86 Multiply Accumulate... M/Acc...Operators...69 Negate... Negate...Arithmetic...71 Real Input Fourier Transform... FFT Real...Signal Processing...77 Reciprocal... Reciprcl...Arithmetic...79 Reverse... Reverse...Bit Logic...81 Rotate... Rotate...Bit Logic...83 Shift... Shift...Bit Logic...85 Sine Cosine Table Lookup... Sin Cos...Operators...87 Square Root... Sqr Root...Operators...89 Subtract... Subtract...Arithmetic...91 Symbol To Bit... Sym->Bit...Bit Logic

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7 DSP DSP Library Introduction Congratulations on your choice of the SystemView Digital Signal Processing (DSP) Library. It is carefully designed to enhance and complement your SystemView software. The contains comprehensive tools to speed the design and simulation of modern DSP systems. SystemView s DSP library supports arithmetic modes used by popular DSP chips (including the C4x extended modes used in TI s floating-point DSPs). The user may also select conventional or extended IEEE floating-point arithmetic modes, and the capability is provided to specify bit length for both exponent and mantissa in floating-point operations. Complementing the critical low-level support for arithmetic modes, the SystemView DSP Library includes essential multiplier, adder, divider, and negate tokens, that are bit true DSP arithmetic operators. For example, designers can specify multipliers in any configuration of their choice, such as 16bit x 16bit, etc. The DSP library also provides a wide selection of high-level processing tools, including mixed radix FFTs, a complete FIR and IIR filter graphical design environment, and a family of block transforms such as the Hadamard and Discrete Cosine and Sine transforms. All functions in the DSP library are detailed in this manual in alphabetical order. Token descriptions include the token s operation and required user inputs. 7

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9 DSP DSP Library General Information Numbers A numerical value within the DSP library is described by numeric type, register size, and either fraction size or exponent size depending on the type. The relationships between numeric types, fraction size, register size, and exponent sizes are shown in table 1. The parenthesized number after the Numeric Type field is the integer code for that numeric type. The parenthesized numbers for Register Size, Fraction Size and Exponent Size are the default values. Note that the register size must exceed both the fraction size and the exponent size. Numeric Type (T) Register Size (N) Fraction Size (F) Exponent Size (K) Same as input (0) Unsigned integer (1) 1-52 (16) Signed integer (2) 1-52 (16) Signed fraction (3) 1-52 (16) 0-51 (15) --- IEEE single (4) IEEE double (5) IEEE general (6) 2-64 (64) (8) C4x short (7) C4x single (8) C4x extended (9) C4x general (10) 2-64 (40) (8) Table 1 9

10 Collectively, the unsigned integer, signed integer, and signed-fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Arithmetic operations for all fixed-point types are performed in two s complement. The ranges for each type of number are shown in table 2-A and 2-B, where n is the number of register bits, f is the number of fraction bits, i = n-f is the number of integer bits (sign included), k is the number of exponent bits, m = n-k is the number of mantissa bits (sign included), and ^ indicates exponentiation. Numeric Type Most Negative Least Normalized Negative Unsigned integer Signed integer -2^(n-1) Signed fixed-point -2^(i-1) ^(-f) Least Negative IEEE single e e e-045 IEEE double e e e-324 IEEE general -(1-2^-m)*2^(2^(k-1)) -2^(2-2^(k-1)) -2^(3-m-2^(k-1)) C4x short C4x single e e-039 C4x extended e e-039 C4x general -2^(2^(k-1)) --- -(1+2^(1-m))*2^(1-2^(k-1)) Table 2-A 10

11 DSP Numeric Type Least Positive Least Normalized Positive Most Positive Unsigned integer ^n-1 Signed integer ^(n-1)-1 Signed fixed-point 2^(-f) --- 2^(i-1)-2^(-f) IEEE single e e e+038 IEEE double e e e+308 IEEE general 2^(3-m-2^(k-1)) 2^(2-2^(k-1)) (1-2^-m)*2^(2^(k-1)) C4x short C4x single e e+038 C4x extended e e+038 C4x general 2^(1-2^(k-1)) --- (1-2^-m)*2^(2^(k-1)) Table 2-B Currently, SystemView passes IEEE double precision floating-point values between tokens. In this respect, tokens in the are the same, however, they act upon descriptor information passed along by SystemView for each input and pass on descriptor information for each output. The passed descriptor information includes numeric type; register size, and fraction or exponent size. In a small number of cases, the values passed between tokens are approximate. For example, let x be a general IEEE type specified as a 64-bit register, but with only an 8-bit exponent field. The remaining 64-8=56 bits compose the sign and mantissa of the x. However, since all data paths in SystemView pass IEEE double precision values with only 64-11=53 bits of sign and mantissa, the value x is then approximated within three bits of precision. The precision used for internal computations within SystemView DSP tokens remains exact. 11

12 For DSP library functions, the output description is created explicitly or implicitly. The data output description is explicitly specified in the parameter window. The implicit data output description occurs when the output type is explicitly specified as identical to that of the input, or when there are no function parameters that specify the output description. Generally, for single input functions, the implicit data output description is simply that of the input. For multiple input functions whose data output descriptions are implicitly specified, such as the divide function, there is a general method to select the data output description from a list of inputs. This method is simply stated as select the output description from the input description with the greatest span to minimize overflow conditions when converting input descriptions into an output description. The span is defined as the difference between the most positive and most negative representable value for a particular description. When the span is equal between inputs, the input with the higher DSP type is chosen, i.e., C4x selected over IEEE, selected over Signed Fixed Point, selected over Signed Integer, selected over Unsigned Integer. Most functions that resolve the output description through this method typically have inputs with the same description, e.g., the complex FFT function. If this method does not yield a desirable output description, convert all data input descriptions to the desired output description before using them. Unless explicitly stated, all inputs are converted to the output type before any internal operations take place. An exception is the square root function that returns the square root of the input value in its explicit output description. Flag outputs such as Overflow (OF), Carry (CF), Zero (ZF), Sign (SF) or Underflow (UF) from a DSP library token are special. Flag outputs have the output type of unsigned integer with a register size of one. A flag value of zero indicates a false condition, and a one indicates a true condition. The flag outputs describe the state of internal computations by the issuing token. All DSP library tokens set their flag outputs to zero (false) at the beginning of each time step. For example, if an Overflow output shows a value of one (true), then an overflow condition has occurred while performing computations within that token. The three areas where processing fixed-point and floating-point types differ include computational rounding, computational overflow, and conversion. 12

13 Computational Rounding Floating-point results are always rounded off to the nearest representable value for that numerical description. Fixed-point results are always rounded toward zero. For fixed-point types, results are usually exact with the exceptions of the divide and reciprocal functions, and the multiply operation of the signed fractional type. DSP Computational Overflow An overflow condition occurs when a result cannot be represented in the intended numerical description. If an overflow occurs in a fixed-point type of register length n bits, n least significant bits are retained as the result. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type (f=n- 1). If an overflow occurs in a floating-point type, the result is clipped to the minimum or maximum representable value for that numerical description. Conversion Conversion between fixed-point types can be chosen to be by bit or by numeric value. Conversion by bit, involves the assignment of bit positions starting from bit position zero, the least significant bit. If the target fixed-point type has more bit positions than the source fixed-point value, then the excess bits are assigned zeros if the source is an unsigned integer. Otherwise, the excess bits are assigned the most significant bit value (the sign bit) of the source fixed-point value. If the target fixed-point description has fewer bit positions, the excess bits from the source fixed-point value are discarded. Conversion between floating-point types, and conversion between floating-point types and fixed-point types are always by numeric value. The value assigned to the target description is to the nearest representable value of that target description. An overflow condition is declared for all conversions, if the source value lies outside the range of the target description. 13

14 Token Name: Adder Abbreviation: Adder Group: Arithmetic Synopsis: This token calculates the sum of one or more input values. See Also: Adder (2 Port), Constant Multiply, Divider, Integrator, Multiplier, Multiplier (2 Port), Multiply Accumulate, Negate, Reciprocal, Square Root, and Subtract Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table Exponent size (in bits) K Refer to the table Output type T Refer to the table Integer type conversions --- By bit or by value conversion method The relationships between the output types, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must always be greater than the exponent size or the fraction size. 14

15 Token Inputs: One or more numeric values DSP Token Outputs: Sum of inputs Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) Discussion: After all input values are converted to the output description, the sum of the converted input values is output. If an input and the sum output are both fixed-point types, the conversion can be made by bit or by numeric value (default). If an overflow occurs in a fixed-point type, the n least significant bits are retained as the result. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point calculation, the result is clipped to the minimum or maximum representable value. For floating-point types, the result is always rounded to the nearest representable value. If an overflow occurs, the overflow flag is set to 1; otherwise, it is set to 0. If the result is a floating-point value, the carry flag is set to 0. For a fixed-point result, if a carry out of the most significant bit occurs, the carry flag is set to 1; otherwise, it is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is set to 0. If the result is a floating-point number, the sign flag is set to 1 if the value is less than 0; otherwise, it is set to 0. For a fixed-point result, the sign flag is set to the value of its most significant bit. For a C4x type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a result is rounded to either zero or a denormalized number, the underflow flag is set to 1; otherwise, it is set to 0. 15

16 Examples: Adding the four bit unsigned integers 8 and 9 yields 1, with OF=1, CF=1, ZF=0, SF=0, UF=0. Adding the four bit signed integers -1 and 7 yields 6, with OF=0, CF=1, ZF=0, SF=0, UF=0. Adding the two bit fractions.5 and -.5 yields 0, with OF=0, CF=1, ZF=1, SF=0, UF=0. Adding the two IEEE doubles 1.e200 and 1.e300 yields 1.e300, with OF=0, CF=0, ZF=0, SF=0, UF=0. Adding the two C4x shorts -100 and -200 yields -256, with OF=1, CF=0, ZF=0, SF=1,UF=0. Token Name: Adder (2 Port) Abbreviation: Adder 2 16

17 Group: Arithmetic DSP Synopsis: This token calculates the sum of two input values and a carry-in bit. See Also: Adder, Constant Multiply, Divider, Integrator, Multiplier, Multiplier (2 Port), Multiply Accumulate, Negate, Reciprocal, Square Root, and Subtract Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table Exponent size (in bits) K Refer to the table Output type T Refer to the table Output latency --- In integral sample periods Integer type conversions --- By bit or by value conversion method The relationships between the output types, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must always be greater than the exponent size or the fraction size. Token Inputs: Input 0 addend Input 1 addend Input Carry bit 17

18 Token Outputs: Sum of inputs Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) Discussion: All inputs are placed into delay buffers to simulate output latency. The delayed inputs are converted to the output description. If input 0 or input 1 and the output sum are both fixed-point types, the conversion can be made by bit or by numeric value (default). The carry input must be of the unsigned type with register length of one bit. If the output description is a fixed-point type, the carry input is converted to the least significant bit of the output description. If the output description is a floating-point type, the carry input is interpreted as a floating-point zero or one. The sum of the converted delayed inputs is output. If an overflow occurs in a fixed-point type, the n least significant bits are retained as the result. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point calculation, the result is clipped to the minimum or maximum representable value. For floating-point types, the result is always rounded to the nearest representable value. If an overflow occurs, the overflow flag is set to 1; otherwise, it is set to 0. If the result is a floating-point value, the carry flag is set to 0. For a fixed-point result, if a carry out of the most significant bit occurs, the carry flag is set to 1; otherwise, it is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is 0. If the result is a floating-point number, the sign flag is set to 1 if the value is less than 0; otherwise, it is set to 0. For a fixed-point result, the sign flag is set to the value of its most significant bit. For a C4x type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a result is rounded to either zero or a denormalized number, the underflow flag is set to 1; otherwise, it is set to 0. 18

19 Examples: Adding the four bit unsigned integers 8 and 9 with carry input 0 yields 1, with OF=1, CF=1, ZF=0, SF=0, UF=0. DSP Adding the four bit unsigned integers 8 and 9 with carry input 1 yields 2, with OF=1, CF=1, ZF=0, SF=0, UF=0. Adding the four bit signed integers -1 and 7 with carry input 0 yields 6, with OF=0, CF=1, ZF=0, SF=0, UF=0. Adding the four bit signed integers -1 and 7 with carry input 1 yields 7, with OF=0, CF=1, ZF=0, SF=0, UF=0. Adding the two bit fractions.5 and -.5 with carry input 0 yields 0, with OF=0, CF=1, ZF=1, SF=0, UF=0. Adding the two bit fractions.5 and -.5 with carry input 1 yields.5, with OF=1, CF=1, ZF=0, SF=0, UF=0. Adding the two IEEE doubles 1.e200 and 1.e300 yields 1.e300, with OF=0, CF=0, ZF=0, SF=0, UF=0. Adding the two C4x shorts -100 and -200 yields -256, with OF=1, CF=0, ZF=0, SF=1, UF=0. Adding the two C4x shorts -10 and -20 with carry input 0 yields -30, with OF=0, CF=0, ZF=0, SF=1, UF=0. Adding the two C4x shorts -10 and -20 with carry input 1 yields -29, with OF=0, CF=0, ZF=0, SF=1, UF=0. 19

20 Token Name: Bitwise AND Abbreviation: AND Group: Bit Logic Synopsis: This token implements a bitwise AND on one or more fixed-point (i.e., unsigned integer, signed integer, or signed fraction type) inputs. See Also: Bit Extract, Bitwise NOT, Bitwise OR, Reverse, Rotate, Shift, Bitwise and Exclusive OR Parameters: None Token Inputs: One or more fixed-point values Token Outputs: Bitwise logical AND of input values Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) 20

21 Discussion: The result of the AND operation is defined on a bitwise basis as shown below. The bit variables, a i and b i are the i th bits of two operands and r i is the i th bit of the result where subscript i takes on values starting from zero. DSP a i b i r i If input descriptions differ in type, register or fraction size, the inputs are first converted by bit to a composite fixed-point output description. The output type is selected by finding the most complex fixed-point type in the inputs, i.e., signed fraction is selected over signed integer, which is selected over unsigned integer type. If the output is a signed fraction, the input description with the greatest number of integer bits is selected to provide the fraction size. The output register size is selected as the greatest register size of all input descriptions. The overflow flag is set to 0, and the carry flag is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is set to 0. The sign flag is set to the value of the most significant bit of the result. The underflow flag is set to 0. Examples: Applying AND to the four bit unsigned integers 8 and 9 yields 8, with ZF=0, SF=0. Applying AND to the four bit signed integers -1 and 7 yields 7, with ZF=0, SF=0. Applying AND to the two bit fractions.5 and -.5 yields.5, with ZF=0, SF=0. Applying AND to the single two bit integer -1, yields -1 with ZF+0, SF+1. 21

22 Token Name: Bit Extract Abbreviation: Xtract Bits Group: Bit Logic Synopsis: This token extracts a fixed-point valued bit string from the fixed-point input. See Also: Bitwise AND, Bitwise NOT, Bitwise OR, Reverse, Rotate, Shift, Bitwise and Exclusive OR Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table LSB position (from zero) LSBPos Extracted string input LSB position MSB position (from zero) MSBPos Extracted string input MSB position Output type T Refer to the table Include sign bit for output --- Input sign bit is inserted into the output Clamp output on overflow --- Output is clamped to extreme values. The relationships between the output types, register size, and fraction or exponent size are shown below. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must always be greater than the exponent size or the fraction size. 22

23 DSP Output Type Register Size Fraction Size Exponent Size Same as input Unsigned integer 1-52 (16) Signed integer 1-52 (16) Signed fraction 1-52 (16) 0-51 (15) --- Token Inputs: One fixed-point value Token Outputs: Bit string is extracted from the input and is converted by bit to the specified output description Discussion: A bit string is extracted from input bits that are delimited by parameters LSBPos, the least significant input bit position, and MSBPos, the most significant input bit position. Bit positions are numbered from zero that addresses the least significant bit. LSBPos and MSBPos must define a non-null bit string, that is wholly contained within the bit string of the input s two s complement representation. The resulting bit string has length MSBPos-LSBPos+1. This bit string is assigned by bit to the least significant bits of the output. If the output type is unsigned, zero is used to pad any output bits, otherwise the pad bits are set with a sign bit value. This value originates from the extracted string most significant bit, or from the input sign bit when the include sign bit option is enabled. The include sign bit option, works only with signed input types. When enabled, the clamp if overflow option allows setting the output to its extreme values, when the composed output bit string does not represent that bit string value. The value is extracted from the input bit LSBPos to the most significant input bit. For example, if the output is an unsigned type and the input bits above MSBPos are not all zero, the output is set to its most positive value. If the output is a signed type and the input bits above MSBPos are mixed zeroes and ones, the output is set to the most negative value if the input is negative, and to the most positive value if the input is positive. 23

24 Examples: Bit extracting with LSBPos=2 and MSBPos=3 the four bit unsigned integer 6 (0110 base 2) into a four bit unsigned integer yields 1 (0001 base 2). Bit extracting with LSBPos=0 and MSBPos=1 the four bit unsigned integer 6 (0110 base 2) into a three bit unsigned integer yields 2 (010 base 2). Bit extracting with LSBPos=0 and MSBPos=1 the four bit unsigned integer 6 (0110 base 2) with the clamp if overflow option enabled into a three bit unsigned integer yields 7 (111 base 2). Bit extracting with LSBPos=2 and MSBPos=3 the four bit signed integer -5 (1011 base 2) into a four bit signed integer yields -2 (1110 base 2). Bit extracting with LSBPos=0 and MSBPos=1 the four bit signed integer -5 (1011 base 2) with the include sign bit option enabled into a three bit signed integer yields -1 (111 base 2). Bit extracting with LSBPos=0 and MSBPos=1 the four bit signed integer -5 (1011 base 2) with the clamp if overflow option enabled into a three bit signed integer yields -4 (100 base 2). Bit extracting with LSBPos=0 and MSBPos=1 the four bit signed integer -5 (1011 base 2) with the include sign bit option and the clamp if overflow option enabled into a three bit signed integer yields -4 (100 base 2). 24

25 DSP Token Name: Bit To Symbol Abbreviation: Bit->Sym Group: Bit Logic Synopsis: This token converts a bit stream waveform into fixed-point symbol values. See Also: Symbol To Bit Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table Threshold --- Input values below this threshold is zero Output bit order --- First arriving bit is either LSB or MSB Output type T Refer to the table The relationships between the output types, register size, and fraction or exponent size are shown below. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must always be greater than the exponent size or the fraction size. Output Type Register Size Fraction Size Exponent Size Same as input Unsigned integer 1-52 (16) Signed integer 1-52 (16) Signed fraction 1-52 (16) 0-51 (15)

26 Token Inputs: Bit stream waveform Token Outputs: Symbol values generated from the input bit stream Discussion: Each input sample is resolved to a zero or one value. If the input is below the threshold parameter value, the input bit is considered zero. A sequence of one or more input bits defines a bit stream that is divided into non-overlapping symbol frames whose bit length is the output register size. If the input rate is 1 Hz, the symbol output rate will be 1/N Hz. From the bit sequence in each symbol frame, converting the bit sequence by bit produces a symbol. The output bit order parameter determines whether the first arriving bit in the symbol frame is considered to be the least significant or most significant bit of the symbol. The first output symbol is always zero. Examples: A left to right bit stream, base 2, is converted to 2 bit unsigned integer symbols with the most significant bit arriving first yields the symbol stream, base 10. With the least significant bit arriving first, the symbol stream becomes base

27 DSP Token Name: Comb Filter Abbreviation: Comb Fltr Group: Signal Processing Synopsis: This token performs the calculation, yt () = x( t mτ ) x( t ( m + n) τ ) Where x is the input, y is the output, t is the current input sample time, τ is input sample period, m is the output latency in integer number of input samples, and n is the feed forward delay in integer number of input samples See Also: Integrator Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table Exponent size (in bits) K Refer to the table Feed forward delay n In integral sample periods Output latency m In integral sample periods Output type T Refer to the table Integer type conversions --- By bit or by value conversion method The relationships between the output types, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must be greater than the exponent size or the fraction size. 27

28 Token Inputs: Numeric value Token Outputs: Comb filter response Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) Discussion: This token performs a derivative like operation on the input. The output flags are set by the subtract operation and are output with the subtraction result. If an overflow occurs in a fixed-point type, the n least significant bits are retained as the result. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point calculation, the result is clipped to the minimum or maximum representable value. For floating-point types, the result is always rounded to the nearest representable value. The overflow flag is set to 1 if an overflow occurs; otherwise, it is set to 0. If the result is a floating-point number, the carry flag is set to 0. For a fixed-point result, the carry flag is set to 1, if borrow into the most significant bit occurs. Otherwise, it is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is 0. If the result is a floating-point number, the sign flag is set to 1 if the value is less than 0; otherwise, it is set to 0. For a fixed-point result, the sign flag is set to the value of its most significant bit. For a non-ieee type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a result is rounded to either zero or a denormalized number, the underflow flag is set to 1; otherwise, it is set to 0. Examples: Subtracting the four bit unsigned integers 8 and 9 yields 15, with OF=1, CF=1, ZF=0, SF=0, UF=0. 28

29 Subtracting the four bit signed integers -1 and 7 yields -8, with OF=0, CF=1, ZF=0, SF=1 UF=0. DSP Subtracting the two bit fractions.5 and -.5 yields -1, with OF=1, CF=1, ZF=0, SF=1, UF=0. Subtracting the two IEEE doubles 1.e200 and 1.e300 yields -1.e300, with OF=1, CF=0, ZF=0, SF=1, UF=0. Subtracting the two C4x shorts -100 and -200 yields 100, with OF=0, CF=0, ZF=0, SF=0, UF=0. 29

30 Token Name: Constant Multiply Abbreviation: Cnst Mltply Group: Arithmetic Synopsis: This token calculates the product of the input and a constant valued input. See Also: Adder, Adder (2 Port), Divider, Integrator, Multiplier, Multiplier (2 Port), Multiply Accumulate, Negate, Reciprocal, Square Root, and Subtract Parameters: Parameter Symbol Definition Constant register size Nv Refer to the table Constant fraction size Fv Refer to the table Constant exponent size Kv Refer to the table Constant input value v Multiplier constant Output latency m In integral sample periods Constant type Tv Refer to the table Output type To Refer to the table The relationships between the output types, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must be greater than the exponent size or the fraction size. Token Inputs: One multiplicand 30

31 Token Outputs: Product of the input and the constant value Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) DSP Discussion: At initialization, the multiplier constant v is first converted into internal representation as specified by the parameters (Tv, Nv, Fv, Kv) and then converted into the output description. At execution, the input is converted to the output description and then multiplied by the constant input. The product and its output flags are delayed m integer number of input sample periods. If output type To is only partially specified, e.g., when the type is not specified as IEEE double, then register size and fraction or exponent size must be derived. If input type differs from constant input type, and if To is specified as same as input, then the output description is taken from the input or constant input whichever description has the greater span. If only one input has type To, then the output description is taken from that input. If both inputs and To are all fixed-point types, the output register size is the sum of input and constant input register sizes. Also, if To is a signed fraction type, the output fraction size is the sum of the input and constant input fraction sizes, otherwise the output fraction size is zero. This composite fixed-point output description prevents the occurrence of any overflow condition. If both inputs are floating-point and if To is either IEEE general or C4x general, then output register size is the larger of the input register sizes and the exponent size is the larger of the input exponent sizes. An error message is issued, if there is insufficient information to determine register size and fraction or exponent size. For example, an error message is generated if both input and constant input have fixed-point types and if To is selected as IEEE general or C4x general. 31

32 If an overflow occurs in a fixed-point result, the n least significant bits are retained. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point calculation, the result is clipped to the min or max representable value. Floating-point type result are always rounded to the nearest representable value. If overflow occurs, the flag is set to 1; otherwise, it is set to 0. The carry flag is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is 0. If the result is a floating-point number, the sign flag is set to 1 if the value is less than 0; otherwise, it is set to 0. For a fixed-point result, the sign flag is set to the value of its most significant bit. For a non-ieee type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a result is rounded to either zero or a denormalized number, the underflow flag is set to 1; otherwise, it is set to 0. Examples: Multiplying the two bit signed fractions -.5 and -.5 with signed fraction output type yields.25 with register size of 4 bits, fraction size of 2 bits, and OF=0, CF=0, ZF=0, SF=0, UF=0. 32

33 DSP Token Name: Converter Abbreviation: Converter Group: Input/Output Synopsis: This token converts an input value to an output value with a specific output description. See Also: Parameters: Parameter Symbol Definition Register size (in bits) N Refer to the table Fraction size (in bits) F Refer to the table Exponent size (in bits) K Refer to the table Output type T Refer to the table Integer type conversions --- By bit or by value conversion method The relationships between the output types, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. Default values are parenthesized. The register size must be greater than the exponent size or the fraction size. Token Inputs: Value to be converted 33

34 Token Outputs: Result of conversion Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) Discussion: This token converts an input value from one numeric description into another. Conversions between floating-point types and conversions between floating-point types and fixed-point types are always by numeric value. Conversion between fixedpoint types is optionally by bit or by numeric value (default). Since all fixed-point values are considered represented in two s complement, conversion by bit involves the assignment of bits from the least significant bit on. If the fixed-point output register size is larger than the input, the excess bits are assigned the input sign bit, if the input type is signed. Otherwise, they are assigned zero. The range for each type of number is shown in table 2-A and 2-B, where n is the number of register bits, f is the number of fraction bits, i = n-f is the number of integer bits (sign included), k is the number of exponent bits, m = n-k is the number of mantissa bits (sign included), and ^ indicates exponentiation. If an overflow occurs in a fixed-point result, the n least significant bits are retained. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point result, it is clipped to the minimum or maximum representable value. If an overflow occurs, the overflow flag is set to 1; otherwise, it is set to 0. The carry flag is set to 0. If the result is 0, the zero flag is set to 1; otherwise, it is set to 0. The sign flag is set to the value of the highest bit of the result for a fixed-point type result. For a floating-point type, if the result is negative, the sign flag is set to 1; otherwise, it is set to 0. 34

35 For a non-ieee type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a nonzero result is rounded to either zero or a denormalized number (i.e., values between the least positive and least negative normalized number) the underflow flag is set to 1; otherwise, it is set to 0. DSP Examples: Converting the four bit signed integer -5 to a two bit unsigned integer yields 3, with OF=1, CF=0, ZF=0, SF=0, UF=0. Converting the IEEE double 1.e-100 to an IEEE single yields 0, with OF=0, CF=0, ZF=1, SF=0, UF=1. Converting by bit the three bit signed fraction.25 to a three bit signed integer yields 1, with OF=0, CF=0, ZF=0, SF=0, UF=0. Converting by numeric value the three bit signed fraction.25 to a three bit signed integer yields 0, with OF=0, CF=0, ZF=1, SF=0, UF=0. Converting the three bit signed fraction.25 to an IEEE double yields.25, with OF=0, CF=0, ZF=0, SF=0, UF=0. 35

36 Token Name: Convolution Abbreviation: Convolve Group: Signal Processing Synopsis: This token performs the end around convolution of the two input sequences each of which are N samples long, where the subscripts are token modulo N to keep them in the interval 0 to N-1. G k N 1 = AB l ( l= 0 k l See Also: Cross Correlator, Fourier Transform Parameters: Parameter Symbol Definition FFT size N Data block size (2^n) Operation D Convolve or deconvolve Token Inputs: Response function B Data sequence, A Token Outputs: Output convolution sequence G Overflow flag (OF) Discussion: This token computes a fast convolution by taking the FFT of the input data blocks, multiplying these transforms and taking an inverse FFT. For the deconvolution operation, the FFT of the signal A is divided by the FFT of the B sequence. The data block size must be a power of two. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 36

37 DSP Token Name: Cross Correlator Abbreviation: XCorr Group: Signal Processing Synopsis: This token computes the end around cross correlation of two input sequences each of which are N samples long, z N 1 = AB k k l ( l+ ) l= 0 Where the subscripts are the token modulo N to keep them in the interval 0 to N-1. See Also: Convolution, Fourier Transform Parameters: Parameter Symbol Definition FFT size N Data block size (2^n) Token Inputs: Input sequence, A Input sequence, B Token Outputs: Output correlation sequence, z Overflow flag (OF) Discussion: This token computes a fast cross correlation of two sequences by calculating their FFTs, complex multiplying these transforms, and taking the real part of the inverse FFT. The number of points in the data block must be a power of two. This token is very useful in determining the time delay between two signals. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 37

38 Token Name: Detrend Abbreviation: Detrend Group: Signal Processing Synopsis: This token computes the mean and trend of the data in the specified time window. These values are subtracted from the input as requested. The output sequence is written as, yk = xk ( atk + b). If the mean only removal is requested, then the coefficient a, is set to zero and b is the calculated mean over the N previous data points. If mean and trend removal is requested, the coefficients aand b are determined via a linear least squares fit of x over the N previous data points. The coefficients, aand b, are updated at every new input. Parameters: Parameter Symbol Definition Window size N Number of points used to determine mean or trend Remove R Removes mean only or mean and trend from input data sequence Token Inputs: Input data sequence, x Token Outputs: Input data sequence with the mean and with or without the trend removed, y Overflow flag (OF) Discussion: This token removes either the mean, or the mean and trend from real data. If mean and trend removal is requested, the token uses an N point linear least squares fit within a moving window whose newest value is the input sample to be modified. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 38

39 DSP Token Name: Discrete Cosine Transform Abbreviation: DCT Group: Signal Processing Synopsis: The token computes the discrete cosine transform of input sequence N samples long. G =. 5[ g + ( 1) k g ] + g cos( π kl / N) k N 1 0 N 1 l= 1 See Also: Discrete Sine, Discrete Hadamard, Fourier, and Real Input Fourier Transform Parameters: Parameter Symbol Definition Number of samples N Transform block size (2^n +1) Transform direction D Computes Forward or Inverse Discrete Cosine Transform on input data sequence Token Inputs: Input sequence, g Token Outputs: Output sequence, G Overflow flag (OF) Discussion: This token performs a fast discrete cosine transform on N points, where N must be one more than a power of two. Note that the argument of the cosine differs by a factor of two, from the FFT. The cosine transform uses a constant and cosine functions as a complete function set on the interval 0 to 2 π. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 39

40 Token Name: Discrete Hadamard Transform Abbreviation: DHT Group: Signal Processing Synopsis: This token computes the discrete Hadamard transform of an input sequence N samples long, N 1 G = H ( k, l) k N g l l= 0 Where H N (k, l) are elements of the Hadamard matrix. See Also: Discrete Cosine Transform, Discrete Sine Transform, Fourier Transform, and Real Input Fourier Transform Parameters: Parameter Symbol Definition Number of samples N Transform size (2^n) Transform direction D Computes Forward or Inverse Discrete Hadamard Transform of the input data sequence Token Inputs: Input data sequence, g Token Outputs: Output data sequence, G Overflow flag (OF) 40

41 Discussion: This token performs the forward and inverse Hadamard transforms on N data points where N must be a power of two. DSP The Hadamard transform is best described in terms of the Hadamard matrix. For N=2 the matrix is simply, 1 1 H 2 = 1 1 From this matrix the higher order matrices are derived via the relation, [ H N ] 2 = H H N N H N H N This is a non-ordered Hadamard matrix. The rows are interchanged in SystemView so that the number of sign changes along each row increases from 0 to N-1. The inverse transform matrix is the same as the forward transform matrix with an additional normalization coefficient of 1/N. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 41

42 Token Name: Discrete Sine Transform Abbreviation: DST Group: Signal Processing Synopsis: The token computes the discrete sine transform of input sequence N samples long, G = g sin( π kl / N) k N 1 1 l= 1 See Also: Discrete Cosine, Discrete Hadamard, Fourier, and Real Input Fourier Transform Parameters: Parameter Symbol Definition Number of samples N Transform block size (2^n-1) Transform direction D Computes Forward or Inverse Discrete Sine Transform of the input data sequence Token Inputs: The sequence g to be transformed Token Outputs: The transformed sequence, G Overflow flag (OF) Discussion: This token performs a fast discrete sine transform on N data points where N must be one less than a power of two. The DST is not quite equivalent to the imaginary part of an FFT. Note that the argument of the sine differs by a factor of two from that of the FFT. The sine transform only uses sine functions as a complete function set on the interval 0 to 2 π. If an overflow or divide by zero occurs anywhere in the computation, the overflow output flag is set to 1; otherwise, it is set to 0. 42

43 DSP Token Name: Divider Abbreviation: Divide Group: Arithmetic Synopsis: This token calculates the quotient of two inputs to a given degree of precision and sets the appropriate output flags. See Also: Adder, Adder (2 Port), Constant Multiply, Integrator, Multiplier, Multiplier (2 Port), Multiply Accumulate, Negate, Reciprocal, Square Root, and Subtract Parameters: Parameter Symbol Definition Precision (bits) P Precision of the division Integer type conversions --- By bit or by value conversion method Token Inputs: Dividend Divisor Token Outputs: Quotient of the inputs Overflow flag (OF) Carry flag (CF) Zero flag (ZF) Sign flag (SF) Underflow flag (UF) 43

44 Discussion: The division is performed for a register size equivalent to the input exponent size plus the precision parameter value. The output description is determined by selecting the input description with the greater span. If both inputs are fixed-point, the output conversions can be performed by bit or by the default numeric value. If an overflow occurs in a fixed-point type, the n least significant bits are retained as the result. This is equivalent to taking the result mod 2 n for the integer types and mod 2 for the pure signed fraction type. If an overflow occurs in a floating-point calculation, the result is clipped to the minimum or maximum representable value. For floating-point types, the result is rounded to the nearest representable value. The overflow flag is set to 1 if overflow or divide by zero occurs, otherwise, it is 0. The carry flag is set to 0. If all the bits of the result are 0 the zero flag is set to 1; otherwise, it is set to 0. If the result is a floating-point number less than 0, the sign flag is set to 1; otherwise, 0. For fixed-point result, the sign flag is set to its most significant bit value. For a non-ieee type, if a nonzero result is rounded to zero, the underflow flag is set to 1; otherwise, it is set to 0. For an IEEE type, if a result is rounded to either zero or a denormalized number, the underflow flag is set to 1; otherwise, it is set to 0. Examples: Using Signed Fractions (6.2), dividing -5.0 by 2.0 with 3 bit precision yields -2, with OF=0, CF=0, ZF=0, SF=1, UF=0. Using Signed Fractions (6.2), dividing -5.0 by 2.0 with 4 bit precision yields -2.5, with OF=0, CF=0, ZF=0, SF=1, UF=0. Using single precision IEEE (32.8), dividing 1.0 by -3.0 with 4 bit precision yields , with OF=0, CF=0, ZF=0, SF=1, UF=0. Using single precision IEEE (32.8), dividing -1.0 by 3.0 with 8 bit precision yields , with OF=0, CF=0, ZF=0, SF=1, UF=0. 44

45 DSP Token Name: FIFO Buffer Abbreviation: Buffer Group: Input/Output Synopsis: This token acts as a FIFO buffer. Data is read into the buffer newest element, and the oldest buffer element is written out as directed by the input and output control lines. The held current buffer output and the count of the remaining samples in the FIFO buffer are output. See Also: Parameters: Parameter Symbol Definition Buffer (samples) N The size of the buffer holding the data Threshold (V) --- Separates a logic 1 from a logic 0 Token Inputs: Data read into the buffer Buffer input control Buffer output control Buffer clear control Token Outputs: Data written from the buffer Buffer count of the remaining buffer data 45

46 Discussion: The token reads data into the buffer when the input control is high and writes the oldest element from the buffer when the output control is high. When the buffer is full, data cannot be read in even if the output control line is high. After the write, the number of samples remaining in the buffer is also output. If the output control line goes low, the last output value is presented. When the reset control line is high, all buffer elements are set to zero. The threshold parameter separates the low and high values of the three control lines. A value below the threshold is considered low; otherwise, it is considered high. The data output descriptions, the type, register size, and fraction or exponent size, are the same as the data input descriptions. The buffer count output is an unsigned integer type with sufficient register size to represent the number of buffer elements. Typically, all buffer inputs have the same sample rate. If they are not, the sample rate of the buffer outputs is set to the sample rate having the first connected and nonfeedback input in this search order: output control line, reset line, input control line, data input. The output control line must be connected. If the output control line is a feedback input, then it must have the same sample rate as the buffer outputs. 46

47 Token Name: Bit True DSP Filter Abbreviation: Filter Group: Operator/Linear System (SystemView token) DSP Synopsis: Unlike the other tokens in the DSP Library, the Filter token resides in the System Operator Library as LinearSys. The DSP Library allows the Linear System token to use the various DSP numeric types supported by the DSP Library. This token implements FIR, IIR, and Laplace system designs. See Also: Refer to Chapter 6 in the SystemView User s Guide, Filters and Linear Systems. Parameters: Parameter Symbol Definition Coefficient Register size Nc Refer to the table Coefficient Fraction size Fc Refer to the table Coefficient Exponent size Kc Refer to the table Coefficient Output type Tc Refer to the table Coeff I-type conversions --- By bit or by value conversion method Coefficient Auto Scale --- Normalize to maximum fixed point value Output Register size No Refer to the table Output Fraction size Fo Refer to the table Output Exponent size Ko Refer to the table Output type To Refer to the table Output I-type conversions --- By bit or by value conversion method 47

48 The relationships between the output or coefficient type, register size, and fraction or exponent size are shown in table 1. Collectively, the unsigned integer, signed integer, and signed fraction types are referred to as fixed-point types, while the IEEE and C4x types are referred to as floating-point types. The default values are parenthesized. The register size must be greater than the exponent size or the fraction size. Token Inputs: Input signal Token Outputs: Output of the filter Overflow flag (OF) Discussion: The DSP mode of operation for the Linear System token can be enabled or disabled by two methods. Referring to the following figure, one could select the DSP Mode menu and toggle Enable DSP Arithmetic Mode or press the top button in the DSP Mode box. The button is labeled the state of the DSP mode of operation, Enabled or Disabled. Similarly, the automatic scaling of fixed point coefficients can be enable by selecting the DSP Mode menu and toggle the Enable Quantization Auto Scale or by pressing the Auto Scale button in the DSP Mode box. Automatic scaling of fixed-point coefficients involves normalizing the intended set of coefficient values to the minimum of the most positive representable value and the absolute value of the most negative representable value for (Tc, Nc, Fc, Kc). 48

49 DSP To describe the filter coefficient values, i.e., specifying parameters (Tc, Nc, Fc, Kc) select the Coefficient Arithmetic Mode from the DSP mode menu and the following figure will appear. Make your choices and press the OK button to activate any changes. This parameter form can also be reached by pressing the activated Specify button in the DSP Mode box. 49

50 At token initialization all coefficient values are converted to the entered description (Tc, Nc, Fc, Kc) and then converted to the working or output description (To, No, Fo, Ko). If the coefficient, type Tc and the working type To are both fixed-point types, one can elect conversion to the working value by bit or by numeric value. The working description parameters, (To, No, Fo, Ko), are made by selecting the Output Arithmetic Mode from the DSP mode menu and the following figure will appear. Make your choices and press the OK button to activate any changes. This parameter form can also be reached by pressing the activated Specify button in the DSP Mode box. 50

51 DSP All inputs values are converted to the working (or output) description (To, No, Fo, Ko) before filter computations in (To, No, Fo, Ko) occur. If the input type and the working type are both fixed-point types, one can elect conversion to the working value by bit or by numeric value. A fresh Linear System token will automatically prompt for both coefficient and working (or output) descriptions. If an overflow or divide by zero occurs anywhere in the computation, the overflow flag is set to 1; otherwise, it is set to 0. 51