EE319 K Lecture 7. Address mode review Assembler, Debugging Psuedo ops 16 bit timer finite state machines. University of Texas ECE

Transcription

1 EE319 K Lecture 7 Address mode review Assembler, Debugging Psuedo ops 16 bit timer finite state machines University of Texas ECE

2 Texas and execution A $24 EEPROM $F800 $F801 $86 $F802 $24 $F803 }ldaa #36 The TExaS simulation of this instruction shows the following two cycles. Opcode fetch R 0xF801 0x86 from EEPROM Operand fetch R 0xF802 0x24 from EEPROM

3 Addressing modes Direct Page addressing mode uses an 8-bit address access from addresses 0 to $00FF called zero-page. on the 9S12 they reference the I/O ports the < operator forces direct addressing I/O EEPROM A $57 $0035 $0036 $57 $0037 $F800 $F801 $96 $F802 $24 $F803 }ldaa 36 Figure Example of the direct-page addressing mode. The TExaS 9S12 simulation this instruction shows the following three cycles. Opcode fetch R 0xF801 0x96 from EEPROM Operand fetch R 0xF802 0x24 from EEPROM Fetch using EARR 0x0024 0x57 from I/O

4 Addressing Modes Extended addressing uses a 16-bit address size of data depends on the op code (which register is uses) access all memory and I/O devices outside Motorola family this addressing mode is called direct the > operator forces extended addressing RAM EEPROM A $62 $0800 $0801 $62 $0802 $F800 $F801 $B6 $F802 $08 $F803 $01 }ldaa $0801 The TExaS 9S12 simulation of this instruction shows the following four cycles. Opcode fetch R 0xF801 0xB6 from EEPROM Operand fetch R 0xF802 0x08 from EEPROM Operand fetch R 0xF803 0x01 from EEPROM Fetch using EARR 0x0801 0x62 from RAM

5 Addressing modes Indexed mode is useful pointers into data structures parameters on the stack. local variables on the stack. 16-bit addition (leax, leay, leas), e..g., leax 10,x ; RegX=RegX+10 Indexed addressing mode fixed offset with the 16-bit registers: X, Y, SP, or PC 5-bit (-16 to +15), 9-bit (-256 to +255), or 16-bit unsigned (0 to 65535) or signed ( to )

6 Indexed Address modes Auto Pre/Post Decrement/Increment Indexed uses the 16-bit registers: X, Y, or SP. register is modified either before (pre) or after (post) amount added to (subtracted from) 1 to 8 In each case assume RegY is initially Post-increment examples: staa 1,Y+ [2345]=RegA, then RegY=2346 staa 4,Y+ [2345]=RegA, then RegY=2349 Pre-increment examples: staa 1,+Y RegY=2346, then [2346]=RegA staa 4,+Y RegY=2349, then [2349]=RegA Post-decrement examples: staa 1,Y- [2345]=RegA, then RegY=2344 staa 4,Y- [2345]=RegA, then RegY=2341 Pre-decrement examples: staa 1,-Y RegY=2344, then [2344]=RegA staa 4,-Y RegY=2341, then [2341]=RegA

7 Lab 2 The code to hand execute $3800 org $3800 $3800 Sum rmb 2 ;16-bit signed result $0003 SIZE equ 3 $4000 org $4000 $4000 CE401A main ldx #Array ;pointer to array $4003 CD0000 ldy #0 ;Sum=0 $4006 7D3800 sty Sum $4009 A630 loop ldaa 1,x+ ;get data from array $400B B704 sex a,d ;promote to 16-bits $400D F33800 addd Sum $4010 7C3800 std Sum ;Sum=Sum+data $4013 8E401D cpx #Array+SIZE $ F1 bne loop ;done? $ E done stop $401A F414D8 Array fcb -12,20,-40 ;array of data $FFFE org $FFFE ;reset vector $FFFE 4000 fdb main

8 Lab 2 Examples of the first 2 instructions. Instruction: ldx #$401F R/W Addr Data Changes R $4000 $CE PC=$4001, IR=$CE R $4001 $40 PC=$4002 R $4002 $1A PC=$4003, X=$401A The second instruction is Instruction: ldy #0 R/W Addr Data Changes R $4003 $CD PC=$4004, IR=$CD R $4004 $00 PC=$4005 R $4005 $00 PC=$4006, Y=$0000 The third instruction is Instruction: sty Sum R/W Addr Data Changes R $4006 $7D PC=$4007, IR=$7D R $4007 $38 PC=$4008 R $4008 $00 PC=$4009, EAR=$3800 W $3800 $00 W $3801 $00

9 Assembly Language Programming Assembly language development editor source code assembler crossassembler object code loader debugger

10 Assembly Language Programming Errors that occur during the assembly process 1) Label previously defined error: label occurs multiple times 2) Undefined opcode error: operation does not exist 3) Operand error: syntax error within the operand expression error undefined symbol in expression addressing mode error size of allocated storage too big, e.g., ds 100*1000 4) Phasing error: value of symbol changes from pass1 to pass2 5) Can't program address error 6) Branch too far error: destination address is too far away 7) Illegal string termination: e.g., "Hello World!

11 Assembly Language Programming Assembler pseudo-ops Pseudo-ops are specific commands to the assembler or assembly directive A B C Meaning org org.org Specific absolute address to put subsequent object code = equ Define a constant symbol set Define or redefine a constant symbol dc.b db fcb.byte Allocate byte(s) of storage with initialized values fcc Create an ASCII string (no termination character) dc.w dw fdb.word Allocate word(s) of storage with initialized values dc.l dl.long Allocate 32-bit long word(s) of storage with initialized values ds ds.b rmb.blkb Allocate bytes of storage without initialization ds.w.blkw Allocate bytes of storage without initialization ds.l.blkl Allocate 32-bit words of storage without initialization end end.end Signifies the end of the source code (TExaS ignores these)

12 Assembly Language Programming Equate symbol to a value <label> equ <expression> (<comment>) <label> = <expression> (<comment>) Redefinable equate symbol to a value <label> set <expression> (<comment>) More information about local variables in Chapter 8. Form constant byte (<label>) fcb <expr>(,<expr>,...,<expr>) (<label>) dc.b <expr>(,<expr>,...,<expr>) (<label>) db <expr>(,<expr>,...,<expr>) (<label>).byte <expr>(,<expr>,...,<expr>) str1 fcb "Hello World",0 Str2 fcb Hello World,0 str3 fcb \Hello World\,0

13 Assembly Language Programming Form constant character string (<label>) fcc <del><string><del> LABEL1 FCC 'ABC' LABEL2 fcc "Jon Valvano " LABEL4 fcc \Welcome to FunCity!\ Form double byte (<label>) fdb <expr>(,<expr>,...,<expr>) (<label>) dc.w <expr>(,<expr>,...,<expr>) (<label>) dw <expr>(,<expr>,...,<expr>) (<label>).word <expr>(,<expr>,...,<expr>) org $FFFE fdb main Define 32-bit constant (<label>) dc.l <expr>(,<expr>,...,<expr>) (<label>) dl <expr>(,<expr>,...,<expr>) (<label>).long <expr>(,<expr>,...,<expr>) S1 dl ,$ S2.long 1,1000, , S3 dc.l -1,0,1

14 Assembly Language Programming Set program counter origin org <expression> (<comment>).org <expression> (<comment>) Reserve multiple bytes (<label>) rmb <expression> (<comment>) (<label>) ds <expression> (<comment>) (<label>) ds.b <expression> (<comment>) (<label>).blkb <expression> (<comment>) Reserve multiple words (<label>) ds.w <expression> (<comment>) (<label>).blkw <expression> (<comment>) ds.l Reserve multiple 32-bit words (<label>) ds.l <expression> (<comment>) (<label>).blkl <expression> (<comment>) End of program (optional) end (<comment>).end (<comment>)

15 16 bit timers The register interfaces Addr Bit Bit 0 Name $0044 Bit Bit 8 TCNT $0045 Bit Bit 0 TCNT $0046 TEN TSWAI TSFRZ TFFCA TSCR1 $004D TOI TCRE PR2 PR1 PR0 TSCR2 $004F TOF TFLG2 PR2 PR1 PR0 Divide by TCNT clock w/4 MHz clk TCNT clock w/24 MHz clk ns 42 ns ns 84 ns µs 168ns µs 333ns µs 667ns µs 1.33 µs µs 2.67 µs µs 5.33 µs

16 Timers Timer_Wait EndT=TCNT+input positive EndT-TCNT negative rts ****Timer_Wait********** * Time delay function * Input: RegD is the time to wait * (in 125ns cycles) * Outputs: none * error: input must < Timer_Wait addd TCNT value at end Wloop cpd TCNT EndT<Tcnt? bpl Wloop rts

17 Timers Fixed time delay using the timer ****Timer_Init********** * Initialize Timer * Input: none * Outputs: none * error: none Timer_Init movb #$80,TSCR1 enable TCNT rts ****Timer_Wait********** * Time delay function * Input: RegD time to wait (125ns cycles) * Outputs: none * error: input must be less than Timer_Wait adddtcnt TCNT at end of delay Wloop cpd TCNT is EndT<TCNT bpl Wloop rts Examples, assume TCNT = 31 (can be any value), Reg D = 4000 (means 1ms, in 250-ns units) the addd will make RegD = 4031 (remains fixed for the rest of the subroutine)

18 Timers Real time systems Bounded latency Input interface: input interface latency RDRF -> Read SCIDRL Output interface: output interface latency TDRE -> Write SCIDRL Periodic process (square wave, Labs 7 and 9): software activity occurs at a periodic rate, Dt let t n be the nth time the process executes goal to make t n t n-1 = Dt dt=jitter Dt-dt < t i t i-1 < Dt+dt for all i