CS61CL Machine Structures. Lec 5 Instruction Set Architecture

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1 CS61CL Machine Structures Lec Instruction Set Architecture David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

2 What is Computer Architecture? Applications Compiler Instr. Set Proc. Operating System Firmware I/O system App photo Instruction Set Architecture Datapath & Control Digital Design Circuit Design Layout & fab Semiconductor Materials Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation Die photo 9/23/09 cs61cl f09 lec 2

3 Forces on Computer Architecture Technology Programming Languages Applications Computer Architecture Operating Systems History (A = F / M) 9/23/09 cs61cl f09 lec 3

4 The Instruction Set: a Critical Interface software instruction set hardware Properties of a good abstraction Lasts through many generations (portability) Used in many different ways (generality) Provides convenient functionality to higher levels Permits an efficient implementation at lower levels 9/23/09 cs61cl f09 lec 4

ture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct

5 Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions 9/23/09 cs61cl f09 lec

which such information flow is controlled.

6 Computer Organization Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units,...) Ways in which these components are interconnected Information flows between components Logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level (RTL) Description Logic Designer's View ISA Level FUs & Interconnect 9/23/09 cs61cl f09 lec 6

7 Fundamental Execution Cycle Instruction Fetch Instruction Decode Obtain instruction from program storage Determine required actions and instruction size Processor regs Memory program Operand Fetch Locate and obtain operand data F.U.s Data Execute Result Store Next Instruction Compute result value or status Deposit results in storage for later use Determine successor instruction von Neuman bottleneck 9/23/09 cs61cl f09 lec 7

8 Elements of an ISA Set of machine-recognized data types bytes, words, integers, floating point, strings,... Operations performed on those data types Add, sub, mul, div, xor, move,. Programmable storage regs, PC, memory Methods of identifying and obtaining data referenced by instructions (addressing modes) Literal, reg., absolute, relative, reg + offset, Format (encoding) of the instructions Op code, operand fields, Current Logical State of the Machine Next Logical State of the Machine 9/23/09 cs61cl f09 lec 8

9 Administrative Issues HW3 due before midnight HW4 will go out before morning, due next Wednesday Project 1 due midnight Friday 10/2 Midterm 1 the following wed alternate on Monday 6-7 pm need to instructor in advance foo.c16 instructions data structure Format foo.o instructions Parse foo.syms symbol asm source sym table data structure 9/23/09 cs61cl f09 lec 9

10 r0 r1 r31 PC lo hi Example: MIPS R Arithmetic logical Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access Control LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR J, JAL, JR, JALR Data types? Format? Addressing Modes? 32-bit instructions on word boundary BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL 9/23/09 cs61cl f09 lec 10

11 Address Space : reserved : code <= instructions PC : : static data heap <= externs regs gp sp <= malloc 7FFFFFFF: stack <= Local variables <= OS, etc. unused FFFFFFFF: 9/23/09 UCB CS61CL F09 Lec 3 11

12 MIPS Instruction Format R: Reg-Reg op 6 rs rt rd shamt funct 6 I: Reg-Imed op rs rt immediate 6 16 J: Jump op immediate 6 26 Reg-Reg instructions (op == 0) add, sub, and, or, nor, xor, slt R[rd] := R[rs] funct R[rt]; pc:=pc+4 sll. srl, sra R[rd] := R[rt] shft shamt Reg-Immed (op!= 0) addi, andi, ori, xori, lui, R[rt] := R[rs] op Im16 addiu, slti, sltiu lw, lh, lhu, lb, lbu R[rt] := Mem[ R[ rs ] + signex(im16) ]* sw, sh, sb Mem[ R[ rs ] + signex(im16) ] := R[rt] 9/23/09 cs61cl f09 lec 12

13 Addressing Modes How is the operand located? Effective Address Calculation Immediate op rs rt im16 Register Direct op rs rt addr reg 0 Absolute op rs rt addr 31 mem 0 Register Indirect op rs rt addr reg 0 mem 0 2 n -1 Base + offset op rs rt addr reg 0 31 mem /23/09 cs61cl f09 lec 13

14 Data Structure Access to Addressing Mode Pointer dereference: *p Struct Field: S.foo Array Element A[i] Pointer deref to field p->foo Pointer to array (*A)[i] Array of pointers *(A[i]) Pointer to pointer **P Array of ptrs to struct A[i]->foo 9/23/09 cs61cl f09 lec 14

15 Computer Number Systems We all take positional notation for granted D k-1 D k-2 D 0 represents D k-1 B k-1 + D k-2 B k D 0 B 0 where B { 0,, B-1 } We all understand how to compare, add, subtract these numbers Add each position, write down the position bit and possibly carry to the next position Computers represent finite number systems Generally radix 2 B k-1 B k-2 B 0 represents B k-1 2 k-1 + B -2 2 k B where B { 0,1 } 9/23/09 cs61cl f09 lec 1

16 Unsigned Numbers - Addition Example: = Unsigned binary addition Is just addition, base 2 Add the bits in each position and carry /23/09 cs61cl f09 lec 16

17 Twos Complement number wheel B k-1 B k-2 B 0 represents -B k-1 2 k-1 + B -2 2 k B Easy to determine sign, Only one representation for 0 Addition and subtraction just as in unsigned case Simple comparison: A < B iff A B < 0 One more negative number than positive number 9/23/09 cs61cl f09 lec 17

18 Sign Extension -0*2 7 + B B 2 + B B B B B Positive Number 0xxxxxxx xxxxxxx -0* *2 7 + B B 2 + B B B B B Negative Number B B 2 + B B B B B xxxxxxx xxxxxxx B B 2 + B B B B B /23/09 cs61cl f09 lec 18

19 MIPS Instruction Format R: Reg-Reg op 6 rs rt rd shamt funct 6 I: Reg-Imed op 6 rs rt immediate 16 J: Jump op 6 Addr 26 Reg-Reg instructions (op == 0) Reg-Immed (op!= 0) Jumps j PC := PC addr 00 jal PC := PC addr 00; R[31] := PC + 4 jr PC := R[rs] 9/23/09 cs61cl f09 lec 19

20 MIPS Instruction Format R: Reg-Reg op 6 rs rt rd shamt funct 6 I: Reg-Imed op 6 rs rt immediate 16 J: Jump op 6 Addr 26 Reg-Reg instructions (op == 0) Reg-Immed (op!= 0) Jumps Branches BEQ, BNE PC := (R[rs]?= R[rt])? PC + signex(im16) : PC+4 BLT, BGT, BLE, BGTE are pseudo ops Move and LI are pseudo ops too 9/23/09 cs61cl f09 lec 20

21 Evolution of Instruction Sets Single Accumulator (EDSAC 190) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 193) Separation of Programming Model from Implementation High-level Language Based (Stack) Concept of a Family (B ) (IBM ) General Purpose Register Machines Complex Instruction Sets Load/Store Architecture (Vax, Intel ) (CDC 6600, Cray ) RISC ix86? (MIPS,Sparc,HP-PA,IBM RS6000, 1987) 9/23/09 cs61cl f09 lec 21

22 Dramatic Technology Advance Prehistory: Generations 1 st Tubes 2 nd Transistors 3 rd Integrated Circuits 4 th VLSI. Discrete advances in each generation Faster, smaller, more reliable, easier to utilize Modern computing: Moore s Law Continuous advance, fairly homogeneous technology 9/23/09 cs61cl f09 lec 22

23 Moore s Law Cramming More Components onto Integrated Circuits Gordon Moore, Electronics, 196 # on transistors on cost-effective integrated circuit double every 18 months 9/23/09 cs61cl f09 lec 23

24 Technology Trends: Microprocessor Capacity Moore s Law Itanium II: 241 million Pentium 4: million Alpha 21264: 1 million Pentium Pro:. million PowerPC 620: 6.9 million Alpha 21164: 9.3 million Sparc Ultra:.2 million CMOS improvements: Die size: 2X every 3 yrs Line width: halve / 7 yrs 9/23/09 cs61cl f09 lec 24

25 Technology Trends Clock Rate: Transistor Density: ~3% Chip Area: ~1% ~30% per year Transistors per chip: ~% Total Performance Capability: ~100% by the time you graduate... 3x clock rate (>10 GHz) 10x transistor count (100 Billion transistors) 30x raw capability plus 16x dram density, 32x disk density (60% per year) Network bandwidth, 9/23/09 cs61cl f09 lec 2

26 Performance Trends MIPS R3000 9/23/09 cs61cl f09 lec 26

27 Processor Performance (1.3X before, 1.X now) 1.4X/yr 9/23/09 cs61cl f09 lec 27

28 Definition: Performance Performance is in units of things per sec bigger is better If we are primarily concerned with response time performance(x) = 1 execution_time(x) " X is n times faster than Y" means Performance(X) Execution_time(Y) n = = Performance(Y) Execution_time(Y) 9/23/09 cs61cl f09 lec 28

29 Metrics of Performance Application Answers per day/month Programming Language Compiler ISA (millions) of Instructions per second: MIPS (millions) of (FP) operations per second: MFLOP/s Datapath Control Function Units Transistors Wires Pins Megabytes per second Cycles per second (clock rate) 9/23/09 cs61cl f09 lec 29

Instruction Set Principles. (Appendix B)

Instruction Set Principles. (Appendix B) Instruction Set Principles (Appendix B) Outline Introduction Classification of Instruction Set Architectures Addressing Modes Instruction Set Operations Type & Size of Operands Instruction Set Encoding