Compilation & linkage. Compilation & linkage. Make. Compilation & linkage. Explicit rules. What makefile contains

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1 Linkage: g++ read main list o Compilation: g++ -c read main list read read read main main list list list If only one file is modified, do we have to recompile all over again? No. The Makefile uses the dependencie read read read main main list list list If read is modified, what should be done? We have to recreate only a subset of the files! read main list Make Make is a program who s main aim is to update other programs in a smart way. smart = Build only out-of-date files (use timestamps). Use the dependency graph for this. You tell make what to do by writing a makefile read read main list list What makefile contains Explicit rules Implicit rules Variable definitions Directives Comments Explicit rules Rule Syntax: targets : prerequisites <tab> command <tab>... Targets: Usually files Prerequisites: Other files that the targets depend on Command: What to execute (shell command) 1

2 Makefile example: Example : read main list g++ main read list o main: main read list g++ -c main read: read read g++ -c read read main list makefile names make looks automatically for : makefile, Makefile Override by using f : make f MyMakefile list: list list g++ -c list read read main list list How Make works? Make works as follows: Given a target: Find the rule for it Check if the rule prerequisites are up to date By recursive application on each of them If one of the prerequisites is newer than target, run the command in rule body. Example Makefile: : read main list g++ main read list o main: main read list g++ -c main read: read read g++ -c read list: list list g++ -c list Running make: make read modified Check Check read Do: g++ -o read Check: main Do: g++ -o main Target: list Do: <nothing> Do: g++ main read list o Comments # comments are easy Variables Make maintains variables Case sensitive Traditionally use capital letters FOO = 1 CFLAGS = -g TARGETS = list main read Rules can use variables main: main read list 2

3 Automatic Variables Set automatically by Make, depend on current rule - target $^ - list of all the prerequisites including the directories they were found $< - first prerequisite in the prerequisite list. $< is often used when you want just the file in the command, while the prerequisites list contains many too $? - all the prerequisites that are newer than the target Setting Variables Using = will expend variables recursively: CFLAGS = $(include_dirs) O include_dirs = -Ifoo -Ibar This means you cant do: CFLAGS = $(CFLAGS) -O #error! You can append to it instead: CFLAGS += -O You can override variables when you run make: Using Wildcards Automatic Wildcard (*,?) expansion in: Targets Prerequisites Commands clean: rm -f * # good objects = * # no good # instead use wildcard function # of make objects := $(wildcard *) # good Implicit rules We saw explicit rules so far, e.g: list: list list g++ -c list Implicit rules (many kinds): Example, creation by suffices. Create files from files : $* g++ -c o $* - the match without the suffix (e.g. list) $@ - file for which the match was made (e.g. list) Now we can write: : $* g++ -c o Implicit Rules : read main list g++ main read list o main: read list read: read list: list The dependencies of main on main are specified in the rule Where make finds Prerequisites? Default: current directory Better design: separate object & binaries from source code Use variable VPATH to look for prerequisites. You can set it in the makefile start to several directories: VPATH = src:../headers #separate by : There is also vpath (lower case!) which 3

4 Auto variables & Directory Search Commands are executed by the shell. You must be carefull the shell will find what make found. Use $^ for this VPATH = src:../headers foo : foo defs hack cc -c $(CFLAGS) $< -o $@ Note that foo might be actually src/foo $@ expands to full pathname This version will not work: foo : foo defs hack cc -c $(CFLAGS) foo -o $@ Directory Search for Link Libraries Example: foo : foo -lcurses cc $^ -o $@ -lname tells make that name is a library. Library name expansions are set by the.libpatterns variable. Default is: lib%.so lib%.a replace % with lib name. This means make first looks for libname.so then for libname.a. The path in which it looks for liberaries is: Built In Implicit Rule Make has a set of default implicit rules for compiling C C++ Fortran Built-in implicit rules make liberal use of certain predefined variables command used to compile a C source file actually says `$(CC) -c $(CFLAGS) $(CPPFLAGS)' Variables Controling Built-in Commands Name of programs CC - Program for compiling C programs CXX Program for compiling C++ programs Arguments for programs: CFLAGS Extra flags to give to the C compiler. CPPFLAGS Extra flags to give to the C preprocessor and programs that use it (the C and Fortran compilers). CXXFLAGS Extra flags to give to the C++ compiler. LDFLAGS Extra flags to give to compilers when they are supposed to invoke the linker, `ld'. Implicit Rules Revisted Suffix Rules (old!): : Suffix rules cannot have any prerequisites of their own: : foo # won t work as you expect!!! Suffix rules use.suffixes from suffix. Implicit Rules Revisted You might prefer to work with a Pattern rule: %: % foo Here you can also use empty commands, as it uses the defaults ones. Control the default by changing the variables %: % foo # this is the same as above! 4

5 clean: rm * temp Phony Targets Target not really the name of a file. No file will be created. What happens when there is a clean file in our path?.phony is a built in target name. Its list of prerequisites tells make which targets should not be treated as files. Phony clean This will work even clean file actually exist:.phony: clean clean: rm * temp When one phony target is a prerequisite of another, it serves as a subroutine of the other.phony: cleanall cleanobj cleanall : cleanobj cleandiff rm program cleanobj : Phony all If no target is specified make executes the first explicit rule it finds. It is common to name it all. This is usually used to build all possible programs that are in the makefile with just one make call. all : prog2 prog3.phony : all : utils cc -o utils prog2 : prog2 Writing Rules A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and commands to use to create or update the target. The order of rules is not significant, except for determining the default goal: the target for make to consider, if you do not otherwise specify one. The default goal is the target of the first rule in the first makefile. If the first rule has multiple targets, only the first target is taken as the default. There are two exceptions: a target starting with a period is not a default unless it contains one or more slashes, `/', as well; and, a target that defines a pattern rule has no effect on the default goal. (See section Defining and Redefining Pattern Rules.) Therefore, we usually write the makefile so that the first rule is the one for compiling the entire program or all the programs described by the makefile (often with a target called `all'). See section Arguments to Specify the Goals. Rule Syntax targets : prerequisites <tab> command <tab>... 5